TWI451552B - Integrated circuit structures - Google Patents

Description

Integrated circuit structure

The present invention relates to an integrated circuit structure, and more particularly to a transistor including a III-V compound semiconductor and a method of manufacturing the same.

The speed of the metal-oxidation-semiconductor (MOS) transistor is closely related to the drive current of the MOS transistor, and the drive current of the MOS transistor is closely related to the mobility of the charge. For example, when the electron mobility is high in the channel region, the NMOS transistor has a high driving current, whereas when the hole mobility is high in the channel region, the PMOS transistor has a high driving current.

A compound semiconductor material composed of a group III and group V element (commonly referred to as a group III-V compound semiconductor) can be used as a good candidate material to form an NMOS transistor because of its high electron mobility. Therefore, III-V compound semiconductors are often used to form NMOS transistors. In order to reduce the manufacturing cost, a method of forming a PMOS transistor using a group III-V compound semiconductor material has been developed. Fig. 1 is a view showing a conventional crystal in which a III-V compound semiconductor is used in combination. In the process of forming the multilayer blanket material formed on a silicon based substrate 1, wherein said multilayer material comprises a buffer layer is formed of GaAs 2, the In _x Al _1-x As (where x is between, but is not equal to 0 and 1) form a gradient of the buffer layer 3, formed by the bottom of in _0.52 Al _0.48 As barrier layer 4, passage 5 formed by the in _0.7 Al _0.3 As, the top formed by the in _0.52 Al _0.48 As barrier layer 6. An etch stop layer 7 formed of InP, and a contact layer 8 formed of In _0.53 Ga _0.47 As. A first etching step is performed to etch through the contact layer 8 and stop at the etch stop layer 7 to form a first recess. Next, a second etching step is performed to etch through the etch stop layer 7 and etch into a portion of the top barrier layer 6 to form a second recess. Next, a gate structure (made of metal) 10 is formed in the second recess. The transistor resulting from the above process has the advantage that the resulting quantum well is composed of a bottom barrier layer, a via, and a top barrier layer.

However, the above transistors still have many disadvantages. It is very difficult to dope high concentration impurities into the III-V compound semiconductor. For example, Si may be implanted or in-situ doped in GaAs as a dopant, whereas the maximum doping concentration of germanium is only between 10 ¹⁷ /cm ³ and 10 ¹⁸ /cm ³ . In addition, the low energy density of the conduction band results in a high source/drain resistance that avoids an improvement in the final transistor drive current. Accordingly, there is a need in the art for methods and structures that overcome the aforementioned shortcomings of the prior art.

Embodiments of the present invention provide an integrated circuit structure including: a substrate; a channel is disposed over the substrate, wherein the channel includes a first III-V compound semiconductor material composed of a group III element and a group V element a gate structure is disposed on the channel; and a source/drain region is adjacent to the channel, wherein the source/drain region comprises a group IV region selected from a group substantially comprising 矽, 锗, and Combination of the above.

An embodiment of the present invention further provides an integrated circuit structure including: a semiconductor substrate; a channel is disposed on the semiconductor substrate, wherein the channel includes a first III-V group composed of a group III element and a group V element a compound semiconductor material; a gate structure is disposed on the channel; a gate spacer is located on a sidewall of the gate structure; a recess adjacent to the channel, the recess having a bottom lower than a bottom of the channel; and a a source/drain region is located in the recess, wherein the source/drain region includes a group IV region selected from a group substantially comprising 矽, 锗, and combinations thereof, and wherein the source/汲The polar region is doped with an n-type dopant or a p-type dopant.

An embodiment of the invention further provides an integrated circuit structure comprising: a substrate; a fin structure is disposed on the substrate, wherein the fin structure comprises a first III- composed of a group III element and a group V element. a group V compound semiconductor material; a gate structure is partially disposed directly on the fin structure, and an additional portion is disposed on the other end of the fin structure; and a source/drain region is adjacent to the fin structure, Wherein the source/drain region comprises a group IV region selected from a group substantially comprising lanthanum, cerium, and combinations thereof.

In order to make the invention more apparent, the following detailed description of the embodiments and the accompanying drawings are as follows:

The following is a detailed description of the embodiments and examples accompanying the drawings, which are the basis of the present invention. In the drawings or the description of the specification, the same drawing numbers are used for similar or identical parts. In the drawings, the shape or thickness of the embodiment may be expanded and simplified or conveniently indicated. In addition, the components of the drawings will be described separately, and it is noted that the components not shown or described in the drawings are known to those of ordinary skill in the art, and in particular, The examples are merely illustrative of specific ways of using the invention and are not intended to limit the invention.

Embodiments of the present invention provide novel transistors comprising a compound semiconductor material (generally referred to as a III-V compound semiconductor) composed of Group III and Group V elements, and a method of forming the novel transistor. And an embodiment of the intermediate stage of the manufacturing method has been illustrated by way of illustration. In the embodiments of the present invention, various similar elements are used to denote similar elements.

Referring to Figure 2, a substrate 20 is provided. Substrate 20 can be a semiconductor substrate comprised of germanium, germanium, SiGe, and/or other semiconductor materials. An insulating structure such as a shallow trench isolation (STI) region 30 is formed in the substrate 20.

Referring to FIG. 3, a portion of the substrate 20 is etched to form a recess 22 between the sidewalls of the opposing two shallow trench isolation (STI) regions 30. Next, as shown in FIG. 4A, a plurality of layers of material including a bottom barrier layer 24, a channel layer 26, and a top barrier layer 28 are epitaxially grown in the recess 22. In one embodiment, the channel layer 26 has a first bandgap, and the bottom barrier layer 24 and the top barrier layer 28 have a second energy gap greater than the first energy gap. Accordingly, a quantum well is formed by the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28. The second energy gap is greater than the first energy gap by a range of about 0.1 eV, although larger or smaller energy gaps may also apply. Suitable materials for the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28 may be selected by comparing energy gaps of semiconductor materials having high carrier mobility, including, but not limited to, semiconductor materials.矽, 锗, GaAs, InP, GaN, InGaAs, InAs, InSb, InAlAs, GaSb, AlSb, AlP, GaP, and combinations of the above materials. The channel layer 26 can be formed by a first group III-V compound semiconductor material composed of a group III element and a group V element. In a comparative embodiment, channel layer 26 includes In _0.7 Ga _0.3 As, while bottom barrier layer 24 and top barrier layer 28 comprise In _0.52 Al _0.48 As. In other embodiments, channel layer 26 includes InGaAs, while bottom barrier layer 24 and top barrier layer 28 comprise GaAs. In still other embodiments, the channel layer 26 includes InAs, and the bottom barrier layer 24 and the top barrier layer 28 comprise InAlAs. The bottom barrier layer 24 can have a thickness ranging from about 5 nm to 10000 nm, the channel layer 26 can have a thickness ranging from about 2 nm to 50 nm, and the top barrier layer 28 can have a thickness ranging from about 5 nm. Nm to 500 nm. However, it should be understood that all of the dimensions mentioned herein are merely illustrative and may vary with different forming techniques.

Optionally, an additional buffer layer is formed over the substrate 20 and underlying a capping semiconductor layer, such as the bottom barrier layer 24. The buffer layer may have a lattice constant between the lattice constant of the substrate 20 and the lattice constant of the capping semiconductor layer such that the lattice constant transition from the bottom layer to the top layer is less abrupt. By forming the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28 between the shallow trench isolation (STI) regions 30, the defects generated in the re-grown layer are significantly less.

Figure 4B shows an alternative embodiment in which the layers 24, 26, 28 are formed on the semiconductor substrate 20 in a blanket pattern.

Fig. 5 is a schematic cross-sectional view showing the formation of a gate structure and a gate spacer 36. The gate structure includes a gate dielectric layer 32 and a gate electrode 34. The gate dielectric layer 32 can be formed of conventional dielectric materials such as hafnium oxide, tantalum nitride, hafnium oxynitride, the above-described multilayer materials, and combinations of the foregoing. Gate dielectric layer 32 can also be constructed of a high dielectric constant (high-k) dielectric material. Examples of the high-k dielectric material may have a k value greater than about 4.0, or even greater than 7.0, and may include alumina, cerium oxide, cerium oxynitride, cerium lanthanum, zirconium hydride, cerium oxide, cerium oxide, titanium oxide, Cerium oxide, and combinations of the above materials. The gate electrode 34 may be composed of doped polysilicon, metal, metal nitride, metal telluride, and the like. The gate spacer 36 may be composed of tantalum oxide, tantalum nitride, and combinations of the above materials, and the gate spacer 36 is a structure known in the art, and thus a detailed description thereof will be omitted herein.

Referring to Figure 6, a recess 38 is formed. In a comparative embodiment, an etch step is used so that the sidewalls of the recess 38 are vertically aligned with the outer edge of the gate spacer 36. As an example, the sidewalls of the recess 38 described herein are vertically aligned with the outer edge of the gate spacer 36, and those of ordinary skill in the art will appreciate that the limitations are intended to encompass process variations and process variations. The misalignment caused by Jiahua. The bottom surface of the recess 38 may be lower than the bottom surface of the channel layer 26.

Referring to FIG. 7A, a Group IV semiconductor material is epitaxially grown in the recess 38, thereby forming a source and drain region 42 (hereinafter collectively referred to as a source/drain region). In one embodiment, the source/drain regions 42 may be comprised of germanium, germanium, or germanium (SiGe). If the final transistor is to be an NMOS transistor, the source/drain region 42 may be doped with an n-type dopant such as phosphorus, arsenic, antimony, and combinations of the above dopants. If the resulting transistor is to be a PMOS transistor, the source/drain region 42 may be doped with a p-type dopant such as boron, indium, and combinations of the above dopants. The n-type dopant or p-type dopant may be in-situ doped in the epitaxial growth process of the source/drain region 42 or in the epitaxial growth source/drain region After 42, the implantation step is performed. The doping concentration of the n-type or p-type dopant may range from about 1 x 10 ¹⁸ /cm ³ to 1 x 10 ²¹ /cm ³ . In this embodiment, the source/drain regions 42 may also be referred to as a group IV semiconductor region 46.

Figure 7B shows an alternative embodiment in which the epitaxially grown source/drain regions 42 comprise epitaxially grown III-V compound semiconductor regions 44 (hereinafter collectively referred to as buffer layers), and Group IV semiconductor regions 46. On the buffer layer 44. The buffer layer 44 may be composed of a III-V compound semiconductor including, but not limited to, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the above materials, and the above multiple layers of materials. . The buffer layer 44 can have a horizontal portion on the bottom of the recess 38 (Fig. 6) and a vertical portion on the sidewall of the recess 38. In one embodiment, the buffer layer 44 includes a gradient composition having a composition in which the lower portion gradually changes to a desired higher portion. Furthermore, the lower portion of the buffer layer 44 may have a lattice constant closer to the lattice constant of the channel layer 26, and the higher portion of the buffer layer 44 may have a lattice constant closer to the group IV semiconductor region. The lattice constant of 46. The lattice constant between the buffer layer 44 and the substrate 20 does not match and may gradually increase from the bottom of the buffer layer 44 to the top of the buffer layer 44.

Comparative In an embodiment, the channel layer 26 is composed of In _0.7 Ga _0.3 As embodiment, while the source / drain regions 42 are formed of Ge, In _0.7 Ga _0.3 As and Ge having a lattice constant between Mismatch about For four percent. In view of this, the buffer layer 44 may have an indium content of less than 0.7%. The buffer layer 44 may also be formed of a multilayer structure composed of unevenness, for example, In _0.2 Ga _0.8 As or a gradient layer having a percentage of sound gradually increasing from the bottom toward the top.

The buffer layer 44 can be doped. If the final transistor is to be an NMOS transistor, the doped impurities include germanium (Si). Conversely, if the final transistor is to be a PMOS transistor, the doped impurities include zinc (Zn) and/or bismuth (Be).

It can be observed that the germanium in the source/drain region 42 has a larger lattice mismatch than the lattice mismatch of the III-V compound semiconductor in the channel layer 26. The larger lattice mismatch results in a high defect density and results in a high junction leakage current. By forming the buffer layer 44, the lattice mismatch between the channel layer 26 and the adjacent source/drain regions 42 can be reduced, resulting in reduced junction leakage current.

Next, as shown in Figures 8A and 8NB, a germanide region 50 (which may also be or include a germanide) is formed on the source/drain region 42. Since the source/drain region 42 includes germanium and/or germanium, the germanide can be formed by blanket forming a metal layer; an annealing step is performed to cause the germanium and underlying germanium and/or germanium Reacting; and removing unreacted portions of the metal layer. Thus, the fabrication of the transistor 52 has been completed.

Referring to FIG. 9, the quantum well formed by the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28 may be replaced by the channel layer 54. The channel layer 54 may be composed of a III-V compound semiconductor material such as GaAs, InP, GaN, InGaAs, InAs, InSb, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, and combinations thereof.

Figure 10 shows an alternative embodiment similar to the embodiment shown in Figures 8A and 8NB, except that the gate dielectric layer is not formed. The gate electrode 34 is in direct contact with the top barrier layer 28. In this example, a depletion region (not shown) between the gate electrode 34 and the top barrier layer 28 due to a Schottky barrier acts as a gate dielectric layer.

Figure 11 shows a similar structure as shown in Figure 9, in which no gate dielectric layer is formed. Again, in Figures 9 through 11, the source/drain regions 42 may include only the doped 矽/锗/SiGe regions adjacent to the channel layer 26 (or 54), or doped 矽/锗/ The buffer layer 44 of the SiGe region and the bottom layer.

The embodiments discussed in the above paragraphs can be applied to fin field effect transistors (FinFETs). Referring to FIG. 12, a fin structure 60, a gate dielectric layer 32, a gate electrode 34, and a gate spacer 36 (not shown) are formed. The details of the formation of the fin structure 60 are disclosed in the co-pending application of the present application: U.S. Patent Application Serial No. 61/182,550, issued May 29, 2009, entitled "Gradient Ternary or Quaternary Multiple-Gate transistor", here Used as a reference. Fin structure 60 may comprise a III-V compound semiconductor material.

Next, as shown in Fig. 13, the structure in which the fin structure 60 is exposed is removed. The portion of the fin structure 60 covered by the gate electrode 34 and the gate spacer 36 can be protected from being etched into a recess. In Fig. 14, the source/drain regions 42 are grown epitaxially and are formed of substantially the same materials as discussed in the previous paragraph. Likewise, the source/drain regions 42 may include a buffer layer 44 between the group IV semiconductor regions 46, or only include a group IV semiconductor region.

Figures 15-17 are schematic cross-sectional views showing alternative embodiments, wherein the cross-sectional views are derived from the vertical section along the cutting line A-A' in Figure 14. In Fig. 15, a gate dielectric layer is not formed. Gate electrode 34 is in direct contact with fin structure 60. In this example, a depletion region (not shown) between the gate electrode 34 and the top barrier layer 28 due to a Schottky barrier acts as a gate dielectric layer.

Referring to FIG. 16, a quantum well is formed by a fin structure 60 (hereinafter collectively referred to as a central fin) and a semiconductor layer 64 on the sidewalls and top surface of the fin structure 60. The semiconductor layer 64 has an energy gap greater than that of the fin structure 60, such as greater than about 0.1 eV. Furthermore, the fin structure 60 and the material of the semiconductor layer 64 have been disclosed in the co-pending application of the present application: U.S. Patent Application Serial No. 61/182,550, issued May 29, 2009, entitled "Gradient Ternary or Quaternary Multiple- Gate transistor".

Figure 17 shows a similar structure as shown in Figure 15, in which no gate dielectric layer is formed. Again, in Figures 15 through 17, although the source/drain regions 42 are not shown in cross-sectional schematic, they may be formed of substantially the same material as described in Figure 14.

Embodiments of the present invention have the technical features of multiple advantages. By further growing the 矽/锗 source/drain regions 42, existing deuteration techniques can be used to reduce the source/drain resistance and improve the drive current of the final transistor. The buffer layer 44 has the effect of alleviating the lattice constant conversion between the channel and the source/drain region of the transistor, thus resulting in an effect of reducing the defect density and reducing the junction leakage current.

The present invention has been disclosed in the above various embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes and refinements without departing from the spirit and scope of the invention. . Therefore, the scope of the invention is defined by the scope of the appended claims.

1. . .矽 base

2. . . The buffer layer

3. . . Gradient buffer layer

4. . . Bottom barrier layer

5. . . aisle

6. . . Top barrier

7. . . Etch stop layer

8. . . Contact layer

9. . . Source/bungee

10. . . Gate structure

20. . . Base

twenty two. . . Concave

twenty four. . . Bottom barrier layer

26‧‧‧Channel layer

28‧‧‧Top barrier

30‧‧‧Shallow Trench Isolation (STI) Zone

32‧‧‧ gate dielectric layer

34‧‧‧gate electrode

36‧‧‧gate gap

38‧‧‧ recessed

42‧‧‧Source/bungee area

44‧‧‧buffer layer

46‧‧‧IV semiconductor region

50‧‧‧ Telluride area

52‧‧‧Optoelectronics

54‧‧‧channel layer

60‧‧‧Fin structure

64‧‧‧Semiconductor layer

1 is a schematic view showing a conventional III-V compound semiconductor material composed of a group III element and a group V element;

2, 3, 4A, 4B, 5, 6, 7A, 7B, 8A, 8B, 9-11 are schematic cross-sectional views showing stages of the process in the process of fabricating a transistor according to an embodiment of the present invention;

12 to 14 are schematic perspective views showing respective process stages in a process for fabricating a fin field effect transistor (FinFET) according to an embodiment of the present invention;

15 to 17 are cross-sectional views showing a fin field effect transistor (FinFET) according to an embodiment of the present invention.

30. . . Shallow trench isolation (STI) region

34. . . Gate electrode

36. . . Gate gap

42. . . Source/drain region

44. . . The buffer layer

46. . . Group IV semiconductor region

50. . . Telluride region

54. . . Channel layer

Claims (12)

An integrated circuit structure comprising: a substrate; a channel on the substrate, wherein the channel comprises a first III-V compound semiconductor material composed of a group III element and a group V element; a gate structure And a source/drain region adjacent to the channel, wherein the source/drain region comprises a group IV region selected from a group substantially comprising 矽, 锗, and combinations thereof The source/drain region further includes a buffer layer between the channel and the group IV region adjacent to the channel and the group IV region. The integrated circuit structure of claim 1, wherein the bottom surface of the source/drain region is lower than the bottom surface of the channel. The integrated circuit structure of claim 1, further comprising a gate spacer on a sidewall of the gate structure, and wherein an outer edge of the gate spacer is vertically aligned with the source/汲The inner side wall of the pole area. The integrated circuit structure of claim 1, wherein the group IV region is composed of a group IV semiconductor material doped with an impurity, wherein the buffer layer comprises a second III-V compound semiconductor material having A lattice constant is between the lattice constant of the channel and the lattice constant of the group IV region. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode, and wherein all of the gate electrodes are located above the channel. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode, and wherein the gate electrode comprises a portion directly on the channel, and the additional portion is located in the pair of channels To the side. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode in contact with a lower semiconductor layer. An integrated circuit structure comprising: a semiconductor substrate; a channel on the semiconductor substrate, wherein the channel comprises a first III-V compound semiconductor material composed of a group III element and a group V element; a gate a structure is disposed on the channel; a gate spacer is located on a sidewall of the gate structure; a recess adjacent to the channel, the recess having a bottom lower than a bottom of the channel; a source/drain region is located In the recess, wherein the source/drain region comprises a group IV region selected from a group substantially comprising germanium, germanium, and combinations thereof, and wherein the source/drain region is doped with an n-type a dopant or a p-type dopant; and a buffer layer comprising a vertical portion between the channel and the group IV region. The integrated circuit structure of claim 8, wherein the buffer layer comprises a second III-V compound semiconductor material in the recess, and wherein the buffer layer comprises a second III-V compound Semi-guide The bulk material has a lattice constant between a first lattice constant of the channel and a second lattice constant of the group IV region. The integrated circuit structure of claim 9, wherein the buffer layer has a gradient composition, a lattice constant of a first portion closer to the channel is closer to the first lattice constant, and is closer to the IV The lattice constant of the second portion of the family region is closer to the second lattice constant. An integrated circuit structure comprising: a substrate; a fin structure on the substrate, wherein the fin structure comprises a first III-V compound semiconductor material composed of a group III element and a group V element; a portion of the gate structure is disposed directly on the fin structure, and an additional portion is disposed on the other end of the fin structure; and a source/drain region is adjacent to the fin structure, wherein the source/drain The region includes a group IV region selected from a group consisting essentially of yttrium, lanthanum, and combinations thereof, wherein the source/drain region further includes a buffer layer between the fin structure and the group IV region and Adjacent to the fin structure and the group IV region. The integrated circuit structure of claim 11, wherein the fin structure comprises: a central fin structure formed of the first first III-V compound semiconductor material; and a semiconductor layer including a first portion Directly on the central fin structure, and a second portion on the opposite side wall of the central fin structure The energy gap of the semiconductor layer is greater than the energy gap of the central fin structure.