US20080001173A1 - BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS - Google Patents
BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS Download PDFInfo
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- US20080001173A1 US20080001173A1 US11/767,188 US76718807A US2008001173A1 US 20080001173 A1 US20080001173 A1 US 20080001173A1 US 76718807 A US76718807 A US 76718807A US 2008001173 A1 US2008001173 A1 US 2008001173A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Definitions
- the present invention relates to semiconductor structures and methods of fabricating the same. More particularly, the present invention relates to a III-V compound semiconductor-containing heterostructure which can be used as a buried channel of a field effect transistor (FET). The present invention also provides a method of fabricating such a III-V compound semiconductor-containing heterostructure. In addition, the present invention also provides a method of forming a FET which includes the inventive heterostructure as a buried channel.
- FET field effect transistor
- HEMTs high electron mobility transistors
- InP substrates have produced maximum transconductance g m values over 2 S/mm (see, D. Xu et al., IEEE Elec. Dev. Let., 20, 206 (1999)), and have been shown to compare favorably in terms of a power-delay product (see, D. H. Kim et al., IEDM Tech. Dig., 787, (2005)).
- FETs lnGaAs-channel field effect transistors
- MOSFETs metal oxide semiconductor field effect transistors
- III-V compound semiconductor-containing heterostructure which provides (i) surface passivation in conjunction with compatibility with high k gate dielectrics, (ii) quantum well engineering for scalability beyond 22 nm CMOS technology, and (iii) low resistance in the source/drain regions.
- the present invention provides a III-V compound semiconductor-containing heterostructure (i.e., a quantum well structure) which can be used as a buried channel for FETs.
- the inventive III-V compound semiconductor-containing heterostructure addresses the surface passivation problem mentioned above.
- the inventive IIII-V compound semiconductor-containing heterostructure can be scaled beyond the 22 nm CMOS technology.
- the inventive III-V compound semiconductor-containing heterostructure when present in MOSFET including a selective epitaxial layer in the source/drain regions, can aide in reducing the resistance in the source/drain regions of the FET.
- III-V compound semiconductor denotes a semiconductor material that includes at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements.
- the III-V compound semiconductors are binary, ternary or quaternary alloys including III/V elements.
- III-V compound semiconductors that can be used in the present invention include, but are not limited to alloys of InGaAs, InAIAs, InAlAsSb, InAlAsP and InGaAsP.
- the inventive III-V compound semiconductor-containing heterostructure comprises, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer and a III-V compound semiconductor barrier layer.
- the barrier layer and the buffer layer are comprised of a III-V semiconductor material that each has a wider band gap than that of the III-V compound semiconductor channel layer. That is, the barrier layer and the buffer layer are each composed of a III-V compound semiconductor having a band gap that is larger than the band gap of the III-V compound semiconductor in the channel layer.
- the term “band gap” refers to the energy difference between the top of the valence band (i.e., E V ) and the bottom of the conduction band (i.e., E C ).
- the buffer layer also has a wide band gap as compared to the channel layer.
- the barrier and buffer layers Since a wide band gap material is used for the barrier and buffer layers and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. Typically, the carriers are confined in the channel layer when typical gate bias conditions are applied.
- inventive III-V compound semi conductor-containing heterostructure used for a buried channel MOSFET minimizes the stringent requirements for dielectric/III-V interfacial properties.
- prior art MOSFET structures including a surface channel III-V structure a high density of traps at the dielectric/III-V interface exists which prevents the formation of an inversion layer.
- inventive III-V compound semiconductor-containing heterostructure used for a buried channel MOSFET has a higher carrier mobility compared to conventional surface channel III-V containing MOSFET structure due to a reduction in carrier scattering.
- inventive III-V compound semiconductor-containing heterostructure comprises:
- the barrier layer includes a doped region which is located in a lower region of the barrier layer that abuts the interface with the underlying III-V compound semiconductor channel layer; such a doped region is referred to in the art as a delta doped region.
- the dopant atom may be an n-type dopant (i.e., an element from Group IV or VI of the Periodic Table of Elements) or a p-type dopant (i.e., an element from Group II or VI of the Periodic Table of Elements).
- the concentration of dopant within the doped region is typically from about 10 11 to about 10 15 atoms/cm 2 , with a concentration of dopant within the doped region from about 10 11 to about 10 13 atoms/cm 2 being more typical.
- a III-V compound semiconductor cap layer can be located atop the III-V compound semiconductor barrier layer.
- the cap layer is typically, but not always necessarily, a doped layer.
- the dopant within the III-V compound semiconductor cap layer can be an n-type dopant or a p-type dopant, with an n-type dopant being more typical for an n-MOSFET.
- the doping within the cap layer is evenly distributed throughout the entire vertical thickness of the layer.
- the concentration of dopant with the cap layer is typically from about 10 17 to about 10 21 atoms/cm 3 , with a concentration of dopant within the cap layer from about 10 18 to about 10 20 atoms/cm 3 being more typical.
- the cap layer may comprise the same or different III-V compound semiconductor as the channel layer.
- the cap layer and the channel layer comprise the same material elements, but are of a different alloy composition.
- the barrier layer and the buffer layer are comprised of an alloy of InAlAs, while the channel layer is comprised of an alloy of InGaAs.
- alloy of InAlAs it is meant a composition of In x Al 1-x As wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52.
- alloy of InGaAs it is meant a composition of In y Ga 1-y As wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In a highly preferred embodiment of the present invention, y is 0.7.
- each of the III-V compound semiconductor layers is a single crystal material of typical commercial quality.
- typical commercial quality it is meant that each of the III-V compound semiconductor layers have a defect density on the order of about 10 5 atoms/cm 2 or less, with a defect density of less than about 5000 atoms/cm 2 being more typical.
- the typical commercial quality of the III-V compound semiconductor layers is a result of utilizing an epitaxial growth process such as, for example, molecular beam epitaxy (MBE) or metalorgano chemical vapor deposition (MOCVD).
- MBE molecular beam epitaxy
- MOCVD metalorgano chemical vapor deposition
- the present invention also is directed to structures, such as, for example FETs, that contain the inventive III-V compound semiconductor-containing heterostructure as a buried channel.
- the semiconductor structure includes:
- the cap layer mentioned above is a patterned III-V compound semiconductor cap layer that, if present, is located atop the III-V compound semiconductor barrier layer.
- the patterned cap layer has an opening that extends to a surface of the underlying barrier layer.
- the dielectric material is present in the exposed barrier layer.
- the dielectric material is present on the surface of the patterned cap layer as well as within the opening covering the exposed sidewalls of the patterned cap layer and the exposed bottom portion of the barrier layer.
- the width of the opening defines the gate length.
- the channel length is less than or equal to 260 nm.
- the structure has a positive threshold voltage.
- the dielectric material having a dielectric constant of greater than 4.0 is referred to herein as a high k dielectric.
- the high k dielectric has a dielectric constant of about 7.0 or greater, with a dielectric constant of about 10.0 or greater being even more typical.
- the dielectric constants mentioned herein are relative to a vacuum, unless otherwise stated.
- the high k dielectric employed in the present invention includes, but is not limited to an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides.
- the high k dielectric is comprised of HfO 2 , ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , a pervoskite oxide, HfSiO z , HfAlO z or HfAlO a N b .
- the high k dielectric is a Hf-based dielectric material.
- the gate conductor of the present invention includes any conductive material such as, for example, polysilicon, polysilicon germanium, conductive metals, conductive metal alloys, conductive silicides, conductive nitrides and combinations or multilayers thereof.
- the gate conductor is a conductive metal, with Al, Pt, Au, W and Ti being highly preferred.
- the selection of metal gates is advantageous since conductive metals have different workfunctions that permit one to adjust the threshold voltage of the device.
- the source and drain contacts which are on either side of the gate conductor, are typically comprised of a conductive material including one of the conductive materials mentioned above for the gate conductor.
- the barrier may include a thin passivation layer.
- the thin passivation layer may comprise a thin layer of a chemical oxide.
- the passivation layer may include a thin layer of amorphous Si/SiO 2 or Ge/Si/SiO 2 .
- the present invention also relates to a method of fabricating such structures.
- the method includes:
- the substrate may also be a semiconductor substrate or a material stack comprising at least a semiconductor substrate,
- a fourth step of epitaxially growing is performed that forms a III-V compound semiconductor cap layer on the surface of the barrier layer.
- the method includes the steps of:
- FIG. 1 is a pictorial representations (through a cross sectional view) illustrating a heterostructure of the present invention which is suitable for use in a buried channel MOSFET.
- FIG. 2 is a pictorial representation (through a cross sectional view) illustrating another heterostructure of the present invention which is suitable for used in a buried-channel MOSFET; this heterostructure represents a highly preferred embodiment.
- FIG. 3 is a pictorial representation (through a cross sectional view) illustrating a buried channel MOSFET using the heterostructure shown in FIG. 2
- FIG. 4 is an energy band gap diagram and interface state density distribution corresponding to the structure of FIG. 3 in the gate region.
- FIG. 5 is a plot of drain current (mAmps/mm) vs. drain-to-source voltage (V) of a long channel MOSFET with L g 5 microns.
- FIG. 8 is a plot of capacitance ( ⁇ F/cm 2 ) vs. gate voltage (V) of an inventive buried channel MOSFET.
- FIG. 9 is a plot of mobility (cm 2 /Vs) vs. carrier sheet density (10 12 cm ⁇ 2 ) of an inventive buried channel MOSFET using 100 khz C-V data.
- FIG. 13 is a plot of gate current (mAmps/mm) vs. gate voltage (V) comparing the gate leakage characteristics of a 260 nm MOSFET with a 200 nm prior art HEMT.
- the present invention which provides a heterostructure including a III-V semiconductor barrier layer and a III-V compound semiconductor channel layer, FETs including the heterostructure as a buried channel structure and methods of fabricating such structures, will now be described in greater detail by referring to the following description and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that in the drawings like reference numerals are used in describing like materials.
- the present invention provides a III-V compound semiconductor-containing heterostructure that includes a III-V compound semiconductor buffer layer having a first band gap, a III-V compound semiconductor channel layer having a second band gap located on an upper surface of the buffer layer, and a III-V compound semiconductor barrier layer having a third band gap located on an upper surface of the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap.
- An optional, yet preferred, III-V compound semiconductor cap layer can be present atop the barrier layer. When present, the optional cap layer is typically doped, preferably with an n-type dopant for an N-MOSFET.
- III-V compound semiconductor denotes a semiconductor material that includes at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements.
- each of the III-V compound semiconductor layers is a binary, ternary or quaternary III-V containing compound.
- III-V compound semiconductors that can be used in the present invention include, but are not limited to alloys of InGaAs, InAlAs, InAlAsSb, InAlAsP and InGaAsP.
- FIG. 1 illustrates the inventive III-V compound semiconductor-containing heterostructure 12 in accordance with a first embodiment of the present invention formed atop a surface of a semiconductor substrate 10 .
- the inventive heterostructure 12 shown in FIG. 1 includes a III-V compound semiconductor buffer layer 14 having a first band gap, a III-V compound semiconductor channel layer 16 having a second band gap located on an upper surface of the III-V compound semiconductor buffer layer, and a III-V compound semiconductor barrier layer 18 having a third band gap located on an upper surface of the III-V compound semiconductor barrier layer 16 .
- the barrier layer 18 includes a delta doped region 18 A that is located in a lower region of barrier layer 18 abutting next to, but not in direct contact with, the interface (INT) with the underlying channel layer 16 .
- the dopant atom present in the delta doped region 18 A may be an n-type dopant (i.e., an element from Group IV or VI of the Periodic Table of Elements) or a p-type dopant (i.e., an element from Group II or IV of the Periodic Table of Elements).
- the concentration of dopant within the delta doped region 18 A is typically from about 10 11 to about 10 15 atoms/cm 2 , with a concentration of dopant within the delta doped region 18 A from about 10 11 to about 10 13 atoms/cm 2 being even more typical.
- the semiconductor substrate 10 employed in the present invention includes any semiconductor material including, for example, Si, SiGe, SiGeC, SiC, Ge alloys, Ga, GaAs, InAs, InP, Ge and all other III-V compound semiconductors.
- the semiconductor substrate 10 may comprise a layered semiconductor material such as, for example, a semiconductor-on-insulator.
- the semiconductor substrate 10 may be doped, undoped or contain doped and undoped regions therein.
- the semiconductor substrate 10 may have a single crystal orientation or it may have surface regions that have different crystal orientations.
- the semiconductor substrate 10 may be strained, unstrained or a combination thereof.
- the band gap of the barrier layer i.e., the third band gap
- the band gap of the channel layer i.e., the second band gap
- the term “band gap” refers to the energy difference between the top of the valence band (i.e., E V ) and the bottom of the conduction band (i.e., E C ).
- the barrier layer 18 is comprised of a III-V compound semiconductor having a band gap value that is from about 0.5 to about 10 times larger than the band gap of the III-V compound semiconductor material used in the channel layer 16 .
- the barrier layer 18 is comprised of a III-V compound semiconductor having a band gap value that is from about 1 to about 5 times larger than the band gap of the III-V compound semiconductor material used in the channel layer 16 .
- FIG. 4 shows a typical band diagram of a MOSFET including the inventive heterostructure shown in FIG. 2 .
- E C and E V are as defined above, E F representes the Fermi level and D it represesents the interface state density.
- the band gap of the buffer layer 14 (i.e., the first band gap) is also larger than that of the channel layer 16 ; this also helps to confine the electrons within the channel layer as well.
- the buffer layer 14 is comprised of a III-V compound semiconductor having a band gap value that is from about 0.5 to about 10 times larger than the band gap of the III-V compound semiconductor material used in the channel layer 16 . More typically, the buffer layer 14 is comprised of a III-V compound semiconductor having a band gap value that is from about 1 to about 5 times larger than the band gap of the III-V compound semiconductor material used in the channel layer 16 .
- band gap of the buffer layer and the band gap of the barrier layer which are larger than the band gap of the channel layer, do not necessarily have the same value.
- the barrier layer and the buffer layer as well
- a narrow band gap material is used for the channel layer
- carriers are confined to the channel layer under certain gate bias range. Typically, the carriers are confined in the channel layer when typical gate bias conditions are applied.
- the barrier layer 18 and the buffer layer 14 are comprised of an alloy of InAlAs, while the channel layer 16 is comprised of an alloy of InGaAs.
- alloy of InAlAs it is meant a composition of InxAl 1-x As wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52.
- alloy of InGaAs it is meant a composition of In y Ga 1-y As wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In an even highly preferred embodiment of the present invention, y is 0.7.
- In 0.32 Al 0.48 As is an ideal high band gap material for the barrier layer 18 since it has low electron affinity, about 4.03 eV, and it results in a high conduction band offset relative to the channel layer 16 .
- a high barrier for electrons between the barrier layer 18 and the channel 16 is achieved by using In 0.7 Ga 0.3 As as the low band gap material for the channel layer 16 .
- In 0.7 Ga 0.3 As channel can have electron mobility of greater than 10,000 cm 2 /Vs at room temperature.
- In 0.7 Ga 0.3 As has a higher electron affinity, 4.65 eV, than that of In 0.52 Al 0.48 As which can further increase the conduction band offset.
- oxidation of InAlAs poses a challenge which needs to be addressed via proper surface passivation prior to gate dielectric deposition.
- each of the III-V compound semiconductor layers employed in the present invention is a single crystal material of typical commercial quality.
- typical commercial quality it is meant that each of the III-V compound semiconductor layers have a defect density on the order of about 10 5 atoms/cm 2 or less, with a defect density of less than about 5000 atoms/cm 2 being more typical.
- the typical commercial quality of the III-V compound semiconductor layers is a result of utilizing an epitaxial growth process such as, for example, molecular beam epitaxy (MBE) or metalorgano chemical vapor deposition (MOCVD). That is, each of the III-V compound semiconductor layers are formed by an epitaxial growth process that produces a high quality, single crystal III-V film.
- MBE molecular beam epitaxy
- MOCVD metalorgano chemical vapor deposition
- each of the III-V compound semiconductor layers of the preset invention may be performed in the same or different apparatus. Moreover, each of the III-V compound semiconductor layers can be formed without breaking vacuum during the deposition of each of the layers. Alternatively, vacuum may be broken during the formation of an individual III-V compound semiconductor layer.
- III-V compound semiconductors are epitaxially grown utilizing III/V-containing precursors that are well known to those skilled in the art. When the vacuum between the deposition of each of the III-V layers is not broken, the precursors can be switched to provide the next layer. In some embodiments, a graded III-V compound semiconductor layer can be formed.
- a delta doped region 18 A is formed into the lower region of the barrier layer 18 A
- an in-situ doping deposition process can be used in which the dopant atom is introduced during the initial formation of the barrier layer and following the formation of a desired thickness of the delta doped region (typically on the order of about 0.1 to about 2.0 nm), the dopant is removed from the precursor stream and the barrier layer 18 formation continues.
- the delta doped region 18 A can be formed utilizing ion implantation after the barrier layer 18 has been formed. The conditions of such an implant are selected to provide a delta doped region next to, but not in contact with, the interface of the underlying channel layer 16 .
- Each of the individual III-V compound semiconductor layers shown in FIG. 1 are thin (providing a total thickness of less than 600 nm).
- the buffer layer 14 has a thickness from about 25 to about 500 nm, with a thickness from about 100 to about 300 nm being even more typical.
- the channel layer 16 of the inventive structure has a thickness from about 1 to about 15 nm, with a thickness from about 5 to about 10 nm being even more typical.
- the thickness of the barrier layer 18 of the inventive structure is from about 0.1 to about 10 mn, with a thickness from about 0.5 to about 10 nm being even more typical.
- the applicants have formed a functional buried channel In 0.7 Ga 0.3 As MOSFETs with a HfO 2 gate dielectric using a structure similar to that in FIG. 1 , and have shown that these devices operate with much reduced gate leakage compared to Schottky-gated devices. Extracted drift mobility of 6600 cm 2 V-s, at an apparent carrier density of 3.2 ⁇ 10 12 cm ⁇ 2 was obtained.
- FIG. 2 illustrates a preferred heterostructure 12 ′ that is formed atop a semiconductor substrate 10 .
- the preferred heterostructure 12 ′ comprises a buffer layer 14 , a channel layer 16 , a non-doped barrier layer 18 and a III-V compound semiconductor cap layer 20 .
- the III-V semiconductor cap layer 20 is typically, but not always necessarily, a doped layer.
- the dopant within the III-V compound semiconductor cap layer 20 can be an n-type dopant or a p-type dopant, with an n-type dopant being more typical for an MOSFET.
- the doping within the cap layer 20 is evenly distributed throughout the entire vertical thickness of the layer.
- the concentration of dopant with the cap layer 20 is typically from about 10 17 to about 10 21 atoms/cm 3 , with a concentration of dopant within the cap layer from about 10 18 to about 10 20 atoms/cm 3 being more typical.
- the cap layer 20 may comprise the same or different III-V compound semiconductor as the channel layer 16 .
- the cap layer 20 comprises the same III-V compound semiconductor elements, but different alloy composition, as the channel layer 16 except for the presence of dopants within the cap layer 20 .
- the cap layer 20 is also a single crystal material of typical commercial quality since an epitaxial growth process such as MBE or MOCVD is used in forming the same.
- the doping of the cap layer 20 typically occurs during the deposition of the cap layer Alternatively, the dopants can be introduced into the cap layer 20 post deposition by ion implantation or outdiffusion from a doped layer that is formed atop the cap layer 20 .
- the thickness of the cap layer 20 is from about 5 to about 50 nm, with a thickness from about 15 to about 30 nm being even more typical.
- the barrier layer 18 and the buffer layer 14 are comprised of an alloy of InAlAs, while the channel layer 16 and the cap layer 20 are comprised of an alloy of InGaAs.
- the cap layer 20 is heavily doped with an n-type dopant.
- alloy of InAlAs it is meant a composition of In x Al 1-x As wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52.
- alloy of InGaAs it is meant a composition of In y Ga 1-y As wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In a highly preferred embodiment of the present invention, y is 0.7.
- FIG. 3 illustrates a FET (i.e., MOSFET) structure of the present invention including the heterostucture 12 ′ shown in FIG. 2 (with the cap layer patterned into patterned cap layer 20 ′ having at least one opening 21 ) atop semiconductor substrate 10 .
- FET i.e., MOSFET
- FIG. 3 illustrates a FET (i.e., MOSFET) structure of the present invention including the heterostucture 12 ′ shown in FIG. 2 (with the cap layer patterned into patterned cap layer 20 ′ having at least one opening 21 ) atop semiconductor substrate 10 .
- the FET shown in FIG. 3 includes the heterostructure 12 ′ of FIG. 2
- the present invention also contemplates a FET in which the heterostructure 12 of FIG. 1 is used.
- the dielectric material to be described herein below
- the FET 50 shown in FIG. 3 includes a semiconductor substrate 10 as described above, a heterostructure 12 ′ as described above including a patterned cap layer 20 having an opening 21 that exposes a surface of the barrier layer 18 , located on an upper surface of the semiconductor substrate 10 , a dielectric material 30 located on the upper surface of the patterned cap layer 20 as well as within the opening 21 covering the sidewalls of the patterned cap layer 20 ′ and the exposed surface of the barrier layer 18 , a gate conductor 32 located on a portion of said dielectric material 30 and above said opening 21 , and source contact 34 and a drain contact 36 abutting the outer edges of the dielectric material 30 and extending into at least the channel layer 16 ; in the drawing the source/drain contacts ( 34 , 36 ) extend into the buffer layer 14 .
- L g denotes the gate length which is defined by the distance of the remaining cap layer 20 ′ extending from the opening 21 to either the source or drain contact ( 34 , 36 ).
- the channel length is less than or equal to 260 nm.
- the structure has a positive threshold voltage.
- the dielectric material 30 employed in the present invention has a dielectric constant of greater than 4.0; such a dielectric material is referred to hereafter as a high k dielectric.
- a dielectric constant of about 7.0 or greater typically, the high k dielectric 30 has a dielectric constant of about 7.0 or greater, with a dielectric constant of about 10.0 or greater being even more typical.
- the dielectric constants mentioned herein are relative to a vacuum, unless otherwise stated.
- the high k dielectric 30 employed in the present invention includes, but is not limited to an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides.
- the high k dielectric 30 is comprised of HfO 2 ZrO 2 , A 1 2 0 3 , TiO 2 , La 2 O 3 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , a pervoskite oxide, HfSiO z , HfAlO z or HfAlO a N b .
- the high k dielectric 30 is a Hf-based dielectric material.
- the high k dielectric 30 is formed utilizing a conventional deposition process including, but not limited to molecular beam epitaxy (MBE), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition and other like deposition processes.
- MBE molecular beam epitaxy
- CVD chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- ALD atomic layer deposition
- PVD physical vapor deposition
- chemical solution deposition chemical solution deposition and other like deposition processes.
- the thickness of the high k dielectric 30 may vary depending on the deposition technique employed in fabricating the same as well as the composition and number of dielectrics of the high k dielectric. Typically, the high k dielectric 30 has a thickness from about 0.5 to about 20 nm, with a thickness from about 1 to about 10 nm being highly preferred.
- the gate conductor 32 of the present invention includes any conductive material such as, for example, polysilicon, polysilicon germanium, conductive metals, conductive metal alloys, conductive silicides, conductive nitrides and combinations or multilayers thereof.
- the metallic gate conductor can be doped so as to shift the workfunction of the gate conductor.
- dopant ions include As, P, B, Sb, Bi, Al, Ga, Ti or mixtures thereof. The same dopants are also used with polysilicon or polySiGe mentioned above.
- the gate conductor 32 is a conductive metal, with Al, Pt, Au, W and Ti being highly preferred. The selection of metal gates is advantageous since conductive metals have different workfunctions that permit one to adjust the threshold voltage of the device.
- the gate conductor 32 is formed by a conventional deposition process such as, for example, CVD, PECVD, PVD, plating, thermal or ebeam evporation and sputtering.
- the gate conductor may be patterned by lithography and etching.
- the gate conductor 32 is formed by a conventional lift-off process.
- the source and drain contacts ( 34 , 36 ), which are on either side of the gate conductor 32 , are typically comprised of a conductive material including one of the conductive materials mentioned above for the gate conductor 32 .
- the contacts are formed by lithography, etching a trench into the gate dielectric 30 and filling the trench with a conductive material.
- the barrier layer 18 may include a thin passivation layer (not shown).
- the thin passivation layer may comprise a thin layer of a chemical oxide.
- the passivation layer may include a thin layer of amorphous Si/SiO 2 or Ge/Si/SiO 2 .
- the thin passivation layer has a thickness from about 0.5 to about 30 nm.
- the optional passivation layer is formed by cleaning the surface of the barrier layer 18 to remove any residual layers (e.g., native oxides), foreign particles, and any residual metallic surface contamination and to temporarily clean the barrier surface. Any residual oxide is removed in a solution of hydrofluoric acid, for example. Other wet etching solutions can also be used to form the optional passivation layer. Alternatively, treatment with a hydrogen plasma alone, or in conjunction with a chemical wet etchant may also be used to form the optional passivation layer.
- any residual oxide is removed in a solution of hydrofluoric acid, for example.
- Other wet etching solutions can also be used to form the optional passivation layer.
- treatment with a hydrogen plasma alone, or in conjunction with a chemical wet etchant may also be used to form the optional passivation layer.
- the dielectric material 30 not protected by the gate conductor 32 can be removed and a selective epitaxial semiconductor layer can be formed adjacent the gate conductor to provides raised source/drain regions that lower the source/drain series resistance.
- selective epitaxial semiconductor layers that can be used include, but are not limited to InGaAs having an In content that varies from 40 to 80% or Ge.
- an undoped In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As quantum well layer structure was used as shown in FIG. 2 .
- the layer structure was grown on an InP substrate, and consisted of a 300 nm In 0.52 Al 0.48 As buffer layer, a 10 nm strained In 0.7 Ga 0.3 As channel, a 10 nm In 0.52 Al 0.48 As top barrier layer and a 25 nm n+ ⁇ In 0.53 Ga 0.47 As cap layer. Aside from the top In 0.53 Ga 0.47 As layer which was etched away in the gate region; all layers were not-intentionally doped.
- Long and short channel MOSFETs with metal gates and high k dielectrics were fabricated using the above layer structure.
- Long-channel ring FET devices were made by patterning the heterostructure using optical lithography followed by selectively etching the InGaAs cap layer to form a gate recess area. After gate dielectric deposition, Ohmic contacts (i.e., source/drain contacts) were then formed. The gate regions were then defined by optical lithography and metal lift off.
- the short-channel device fabrication included an additional mesa isolation step before the gate lithography.
- the gate recess was patterned by electron-beam lithography, where gate lengths as short as 260 nm were fabricated.
- the long-channel devices utilized MBE-deposited HfO 2 and had Al gates, while the short-channel devices had ALD-Al 2 O 3 as a gate dielectric and Al or Pt as the gate conductors.
- the devices showed good saturation and pinch off characteristics. A series resistance of 128 ⁇ was observed despite, the long channel length, an issue that may, in part, be due to non-optimized contact formation.
- the sub-threshold characteristics and corresponding transconductance are shown in FIGS. 6A-6B .
- the drain current on-off ratio was approximately 10 4 , and the devices had a sub-threshold slope of 150 mV/decade.
- the gate leakage characteristics are shown in FIG. 7 , and were compared with prior art HEMTs.
- the gate leakage current density of the MOSFET was more than 200 ⁇ lower than the Schottky-gated devices.
- the capacitance-voltage results for the MOSFETs are shown in FIG. 8 .
- the effective-oxide thickness (EOT) extracted from the data was 4.4+0.3 nm, The interface state density for these device was in the high 10 12 cm ⁇ 2 /eV range, and this value could account for the non-ideal sub-threshold slope.
- the resulting mobility vs. sheet density plot is shown in FIG. 9 .
- a peak mobility of 1100 cm 2 /Vs was determined at a carrier density of 2.6 ⁇ 10 12 cm ⁇ 2 . Further improvements should be possible through optimization of the interface properties.
- the gate leakage as in FIG. 13 shows considerable improvement over previous HEMT devices.
Abstract
Description
- This application claims benefit of U.S. Provisional Application Ser. No. 60/816,050, filed Jun. 23, 2006, the entire contents of which are incorporated herein by reference.
- The present invention relates to semiconductor structures and methods of fabricating the same. More particularly, the present invention relates to a III-V compound semiconductor-containing heterostructure which can be used as a buried channel of a field effect transistor (FET). The present invention also provides a method of fabricating such a III-V compound semiconductor-containing heterostructure. In addition, the present invention also provides a method of forming a FET which includes the inventive heterostructure as a buried channel.
- Compound semiconductors are receiving renewed attention for use as channel materials for advanced ultra large scale integration (ULSI) digital logic applications due to their high electron hole mobility. For example, the InGaAs/InAlAs material system is one of the most promising material systems for this application due to its large conduction-band offsets and high carrier mobility. Schottky-gated InGaAs high electron mobility transistors (HEMTs) grown on InP substrates have produced maximum transconductance gm values over 2 S/mm (see, D. Xu et al., IEEE Elec. Dev. Let., 20, 206 (1999)), and have been shown to compare favorably in terms of a power-delay product (see, D. H. Kim et al., IEDM Tech. Dig., 787, (2005)).
- Despite these promising results, for ULSI applications, lnGaAs-channel field effect transistors (FETs) will ultimately need to incorporate high dielectric constant (k) dielectrics as the gate dielectric in order to meet current leakage requirements.
- Previous work on InGaAs-channel metal oxide semiconductor field effect transistors (MOSFETs) has mainly focused on surface-channel device geometries. See, for example, F. Ren, IEEE. Elec. Dev. Let., 19, 309 (1998). Such devices, however, require the formation of an extremely high quality semiconductor/dielectric interface in order to preserve a low interface state density near the surface-layer conduction band edge.
- Despite the above advances in the art, integration of InGaAs-channels for FET applications still requires breakthrough in the following areas (i) surface passivation in conjunction with compatibility with high k gate dielectrics, (ii) quantum well engineering for scalability beyond 22 nm CMOS technology, and (iii) low resistance in the source/drain regions. To date, the applicants are unaware of any prior art III-V compound semiconductor-containing structure that satisfies the three requirements mentioned above.
- In view of the above, there exists a need for providing a III-V compound semiconductor-containing heterostructure which can be used as a buried channel for FETs, including MOSFETs.
- There also exists a need for providing a III-V compound semiconductor-containing heterostructure which provides (i) surface passivation in conjunction with compatibility with high k gate dielectrics, (ii) quantum well engineering for scalability beyond 22 nm CMOS technology, and (iii) low resistance in the source/drain regions.
- The present invention provides a III-V compound semiconductor-containing heterostructure (i.e., a quantum well structure) which can be used as a buried channel for FETs. The inventive III-V compound semiconductor-containing heterostructure addresses the surface passivation problem mentioned above. In addition, the inventive IIII-V compound semiconductor-containing heterostructure can be scaled beyond the 22 nm CMOS technology. Moreover, the inventive III-V compound semiconductor-containing heterostructure, when present in MOSFET including a selective epitaxial layer in the source/drain regions, can aide in reducing the resistance in the source/drain regions of the FET.
- In the present invention, the term “III-V compound semiconductor” denotes a semiconductor material that includes at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. Typically, the III-V compound semiconductors are binary, ternary or quaternary alloys including III/V elements. Examples of III-V compound semiconductors that can be used in the present invention include, but are not limited to alloys of InGaAs, InAIAs, InAlAsSb, InAlAsP and InGaAsP.
- The inventive III-V compound semiconductor-containing heterostructure comprises, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer and a III-V compound semiconductor barrier layer. In the present invention, the barrier layer and the buffer layer are comprised of a III-V semiconductor material that each has a wider band gap than that of the III-V compound semiconductor channel layer. That is, the barrier layer and the buffer layer are each composed of a III-V compound semiconductor having a band gap that is larger than the band gap of the III-V compound semiconductor in the channel layer. The term “band gap” refers to the energy difference between the top of the valence band (i.e., EV) and the bottom of the conduction band (i.e., EC). Typically, the buffer layer also has a wide band gap as compared to the channel layer.
- Since a wide band gap material is used for the barrier and buffer layers and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. Typically, the carriers are confined in the channel layer when typical gate bias conditions are applied.
- The inventive III-V compound semi conductor-containing heterostructure used for a buried channel MOSFET minimizes the stringent requirements for dielectric/III-V interfacial properties. In contrast and in prior art MOSFET structures including a surface channel III-V structure, a high density of traps at the dielectric/III-V interface exists which prevents the formation of an inversion layer.
- In addition, the inventive III-V compound semiconductor-containing heterostructure used for a buried channel MOSFET has a higher carrier mobility compared to conventional surface channel III-V containing MOSFET structure due to a reduction in carrier scattering.
- In general terms, the inventive III-V compound semiconductor-containing heterostructure comprises:
- a III-V compound semiconductor buffer layer having a first band gap;
- a III-V compound semiconductor channel layer having a second band gap located on an upper surface of said buffer layer; and
- a III-V compound semiconductor barrier layer having a third band gap located on an upper surface of the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap.
- In some embodiments of the present invention, the barrier layer includes a doped region which is located in a lower region of the barrier layer that abuts the interface with the underlying III-V compound semiconductor channel layer; such a doped region is referred to in the art as a delta doped region. When a doped region is present in the barrier layer, the dopant atom may be an n-type dopant (i.e., an element from Group IV or VI of the Periodic Table of Elements) or a p-type dopant (i.e., an element from Group II or VI of the Periodic Table of Elements). The concentration of dopant within the doped region is typically from about 1011 to about 1015 atoms/cm2, with a concentration of dopant within the doped region from about 1011 to about 1013 atoms/cm2 being more typical.
- In yet another embodiment of the present invention, a III-V compound semiconductor cap layer can be located atop the III-V compound semiconductor barrier layer. When the III-V semiconductor cap layer is present, the cap layer is typically, but not always necessarily, a doped layer. The dopant within the III-V compound semiconductor cap layer can be an n-type dopant or a p-type dopant, with an n-type dopant being more typical for an n-MOSFET. Unlike the delta doped region described above, the doping within the cap layer is evenly distributed throughout the entire vertical thickness of the layer. The concentration of dopant with the cap layer is typically from about 1017 to about 1021 atoms/cm3, with a concentration of dopant within the cap layer from about 1018 to about 1020 atoms/cm3 being more typical.
- The cap layer may comprise the same or different III-V compound semiconductor as the channel layer. In a preferred embodiment of the present invention, the cap layer and the channel layer comprise the same material elements, but are of a different alloy composition.
- In still another embodiment of the present invention, the barrier layer and the buffer layer are comprised of an alloy of InAlAs, while the channel layer is comprised of an alloy of InGaAs. By “alloy of InAlAs” it is meant a composition of InxAl1-xAs wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52. By “alloy of InGaAs” it is meant a composition of InyGa1-yAs wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In a highly preferred embodiment of the present invention, y is 0.7.
- In a further embodiment of the present invention, each of the III-V compound semiconductor layers is a single crystal material of typical commercial quality. By “typical commercial quality” it is meant that each of the III-V compound semiconductor layers have a defect density on the order of about 105 atoms/cm2 or less, with a defect density of less than about 5000 atoms/cm2 being more typical. The typical commercial quality of the III-V compound semiconductor layers is a result of utilizing an epitaxial growth process such as, for example, molecular beam epitaxy (MBE) or metalorgano chemical vapor deposition (MOCVD).
- In addition to the above III-V compound semiconductor-containing heterostructure, the present invention also is directed to structures, such as, for example FETs, that contain the inventive III-V compound semiconductor-containing heterostructure as a buried channel. In this aspect of the present invention, the semiconductor structure includes:
- a semiconductor substrate having an upper surface;
- a buried channel structure located on said upper surface of said semiconductor substrate, wherein said buried channel structure comprises a III-V compound semiconductor buffer layer having a first band gap, a III-V compound semiconductor channel layer having a second band gap located on an upper surface of said buffer layer, and a III-V compound semiconductor barrier layer having a third band gap located on an upper surface of the III-V compound semiconductor channel, wherein said first and third band gaps are larger than the second band gap;
- a dielectric material having a dielectric constant of greater than 4.0 located on said buried channel structure and in contact with at least a portion of said barrier layer;
- a gate conductor located on a portion of said dielectric material; and
- a source contact and a drain contact which are in contact with at least said channel layer.
- Most of the embodiments mentioned above for the heterostructure apply here as well for the FET-containing structure as well.
- It is noted that in the inventive FET structure, the cap layer mentioned above is a patterned III-V compound semiconductor cap layer that, if present, is located atop the III-V compound semiconductor barrier layer. In embodiments in which the patterned cap layer is present, the patterned cap layer has an opening that extends to a surface of the underlying barrier layer. The dielectric material is present in the exposed barrier layer. In some embodiments, the dielectric material is present on the surface of the patterned cap layer as well as within the opening covering the exposed sidewalls of the patterned cap layer and the exposed bottom portion of the barrier layer. In the embodiment including the patterned cap, the width of the opening defines the gate length. In one embodiment, the channel length is less than or equal to 260 nm. In some embodiments, the structure has a positive threshold voltage.
- The dielectric material having a dielectric constant of greater than 4.0 is referred to herein as a high k dielectric. Typically, the high k dielectric has a dielectric constant of about 7.0 or greater, with a dielectric constant of about 10.0 or greater being even more typical. The dielectric constants mentioned herein are relative to a vacuum, unless otherwise stated. Specifically, the high k dielectric employed in the present invention includes, but is not limited to an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides. In one embodiment, it is preferred that the high k dielectric is comprised of HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, a pervoskite oxide, HfSiOz, HfAlOz or HfAlOaNb. Preferably, the high k dielectric is a Hf-based dielectric material.
- The gate conductor of the present invention includes any conductive material such as, for example, polysilicon, polysilicon germanium, conductive metals, conductive metal alloys, conductive silicides, conductive nitrides and combinations or multilayers thereof. Preferably, the gate conductor is a conductive metal, with Al, Pt, Au, W and Ti being highly preferred. The selection of metal gates is advantageous since conductive metals have different workfunctions that permit one to adjust the threshold voltage of the device.
- The source and drain contacts, which are on either side of the gate conductor, are typically comprised of a conductive material including one of the conductive materials mentioned above for the gate conductor.
- In some embodiments of the present invention, the barrier may include a thin passivation layer. When present, the thin passivation layer may comprise a thin layer of a chemical oxide. Alternatively, the passivation layer may include a thin layer of amorphous Si/SiO2 or Ge/Si/SiO2.
- In addition to the above structures, the present invention also relates to a method of fabricating such structures. With respect to the inventive III-V compound semiconductor-containing heterostructure, the method includes:
- first epitaxially growing a III-V compound semiconductor buffer layer having a first band gap on an upper surface of a substrate;
- second epitaxially growing a III-V compound semiconductor channel layer having a second band gap on an upper surface of the buffer layer; and
- third epitaxially growing a III-V compound semiconductor barrier layer having a third band gap on an upper surface of the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap.
- The substrate may also be a semiconductor substrate or a material stack comprising at least a semiconductor substrate, In other embodiments, a fourth step of epitaxially growing is performed that forms a III-V compound semiconductor cap layer on the surface of the barrier layer.
- With respect to the inventive FET, the method includes the steps of:
- forming a buried channel structure atop a semiconductor substrate, wherein said forming includes first epitaxially growing a III-V compound semiconductor buffer layer having a first band gap on an upper surface of said semiconductor substrate, second epitaxially growing a III-V compound semiconductor channel layer having a second band gap on an upper surface of the buffer layer, and third epitaxially growing a III-V compound semiconductor barrier layer having a third band gap on an upper surface of the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap;
- forming a dielectric material having a dielectric constant of greater than 4.0 on said buried channel structure and in contact with at least a portion of said barrier layer;
- forming a gate conductor on a portion of said dielectric material; and
- forming a source contact and a drain contact which are in contact with at least said channel layer.
- Many of the above-mentioned embodiments are also applicable in forming the inventive FET structure.
-
FIG. 1 is a pictorial representations (through a cross sectional view) illustrating a heterostructure of the present invention which is suitable for use in a buried channel MOSFET. -
FIG. 2 is a pictorial representation (through a cross sectional view) illustrating another heterostructure of the present invention which is suitable for used in a buried-channel MOSFET; this heterostructure represents a highly preferred embodiment. -
FIG. 3 is a pictorial representation (through a cross sectional view) illustrating a buried channel MOSFET using the heterostructure shown inFIG. 2 -
FIG. 4 is an energy band gap diagram and interface state density distribution corresponding to the structure ofFIG. 3 in the gate region. -
FIG. 5 is a plot of drain current (mAmps/mm) vs. drain-to-source voltage (V) of a long channel MOSFET with Lg5 microns. -
FIGS. 6A-6B are plots of the drain current (mAmps/mm) vs. gate-to-source (V) and extrinsic transconductance gm (mS/mm) vs. gate-to-source (V), respectively, of a long channel MOSFET with Lg=5 microns. -
FIG. 7 is a plot of gate current (A/cm2) vs. gate voltage (V) of a long channel MOSFET (Lg=5 microns) with a prior art HEMT device. -
FIG. 8 is a plot of capacitance (μF/cm2) vs. gate voltage (V) of an inventive buried channel MOSFET. -
FIG. 9 is a plot of mobility (cm2/Vs) vs. carrier sheet density (1012 cm−2) of an inventive buried channel MOSFET using 100 khz C-V data. -
FIG. 10 is a plot of drain current (mAmps/mm) vs. drain-to-source voltage (V) of a short channel MOSFET with Lg=260 nm. -
FIG. 11 is a plot of drain current (mAmps/mm) vs. drain-to-source voltage (V) of a short channel MOSFET with Lg=260 nm of a enhancement mode (EM) and a depletion mode (DM) short channel MOSFET with Lg=260 nm. -
FIG. 12 . is a plot of transconductance (mS/mm) vs. gate-to-source (V) of a short channel MOSFET with Lg=260 nm. -
FIG. 13 is a plot of gate current (mAmps/mm) vs. gate voltage (V) comparing the gate leakage characteristics of a 260 nm MOSFET with a 200 nm prior art HEMT. - The present invention, which provides a heterostructure including a III-V semiconductor barrier layer and a III-V compound semiconductor channel layer, FETs including the heterostructure as a buried channel structure and methods of fabricating such structures, will now be described in greater detail by referring to the following description and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that in the drawings like reference numerals are used in describing like materials.
- In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention.
- It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also he present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
- As stated above, the present invention provides a III-V compound semiconductor-containing heterostructure that includes a III-V compound semiconductor buffer layer having a first band gap, a III-V compound semiconductor channel layer having a second band gap located on an upper surface of the buffer layer, and a III-V compound semiconductor barrier layer having a third band gap located on an upper surface of the III-V compound semiconductor channel layer, wherein said first and third band gaps are larger than the second band gap. An optional, yet preferred, III-V compound semiconductor cap layer can be present atop the barrier layer. When present, the optional cap layer is typically doped, preferably with an n-type dopant for an N-MOSFET.
- In the present invention, the term “III-V compound semiconductor” denotes a semiconductor material that includes at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. Typically, each of the III-V compound semiconductor layers is a binary, ternary or quaternary III-V containing compound. Examples of III-V compound semiconductors that can be used in the present invention include, but are not limited to alloys of InGaAs, InAlAs, InAlAsSb, InAlAsP and InGaAsP.
- Reference is first made to
FIG. 1 which illustrates the inventive III-V compound semiconductor-containingheterostructure 12 in accordance with a first embodiment of the present invention formed atop a surface of asemiconductor substrate 10. Theinventive heterostructure 12 shown inFIG. 1 includes a III-V compoundsemiconductor buffer layer 14 having a first band gap, a III-V compoundsemiconductor channel layer 16 having a second band gap located on an upper surface of the III-V compound semiconductor buffer layer, and a III-V compoundsemiconductor barrier layer 18 having a third band gap located on an upper surface of the III-V compoundsemiconductor barrier layer 16. - In the embodiment illustrated, the
barrier layer 18 includes a delta doped region 18A that is located in a lower region ofbarrier layer 18 abutting next to, but not in direct contact with, the interface (INT) with theunderlying channel layer 16. The dopant atom present in the delta doped region 18A may be an n-type dopant (i.e., an element from Group IV or VI of the Periodic Table of Elements) or a p-type dopant (i.e., an element from Group II or IV of the Periodic Table of Elements). The concentration of dopant within the delta doped region 18A is typically from about 1011 to about 1015 atoms/cm2, with a concentration of dopant within the delta doped region 18A from about 1011 to about 1013 atoms/cm2 being even more typical. - The
semiconductor substrate 10 employed in the present invention includes any semiconductor material including, for example, Si, SiGe, SiGeC, SiC, Ge alloys, Ga, GaAs, InAs, InP, Ge and all other III-V compound semiconductors. Thesemiconductor substrate 10 may comprise a layered semiconductor material such as, for example, a semiconductor-on-insulator. Thesemiconductor substrate 10 may be doped, undoped or contain doped and undoped regions therein. Thesemiconductor substrate 10 may have a single crystal orientation or it may have surface regions that have different crystal orientations. Thesemiconductor substrate 10 may be strained, unstrained or a combination thereof. - In accordance with the present invention, the band gap of the barrier layer (i.e., the third band gap) is larger (wider) than the band gap of the channel layer (i.e., the second band gap). As stated above, the term “band gap” refers to the energy difference between the top of the valence band (i.e., EV) and the bottom of the conduction band (i.e., EC). Typically, the
barrier layer 18 is comprised of a III-V compound semiconductor having a band gap value that is from about 0.5 to about 10 times larger than the band gap of the III-V compound semiconductor material used in thechannel layer 16. More typically, thebarrier layer 18 is comprised of a III-V compound semiconductor having a band gap value that is from about 1 to about 5 times larger than the band gap of the III-V compound semiconductor material used in thechannel layer 16.FIG. 4 shows a typical band diagram of a MOSFET including the inventive heterostructure shown inFIG. 2 . In the band diagram EC and EV are as defined above, EF representes the Fermi level and Dit represesents the interface state density. - The the band gap of the buffer layer 14 (i.e., the first band gap) is also larger than that of the
channel layer 16; this also helps to confine the electrons within the channel layer as well. Typically, thebuffer layer 14 is comprised of a III-V compound semiconductor having a band gap value that is from about 0.5 to about 10 times larger than the band gap of the III-V compound semiconductor material used in thechannel layer 16. More typically, thebuffer layer 14 is comprised of a III-V compound semiconductor having a band gap value that is from about 1 to about 5 times larger than the band gap of the III-V compound semiconductor material used in thechannel layer 16. - It is noted that the band gap of the buffer layer and the band gap of the barrier layer, which are larger than the band gap of the channel layer, do not necessarily have the same value.
- Since wide band gap materials are used for the barrier layer (and the buffer layer as well) and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. Typically, the carriers are confined in the channel layer when typical gate bias conditions are applied.
- In a preferred embodiment of the present invention, the
barrier layer 18 and thebuffer layer 14 are comprised of an alloy of InAlAs, while thechannel layer 16 is comprised of an alloy of InGaAs. By “alloy of InAlAs” it is meant a composition of InxAl1-xAs wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52. By “alloy of InGaAs” it is meant a composition of InyGa1-yAs wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In an even highly preferred embodiment of the present invention, y is 0.7. - In0.32Al0.48As is an ideal high band gap material for the
barrier layer 18 since it has low electron affinity, about 4.03 eV, and it results in a high conduction band offset relative to thechannel layer 16. A high barrier for electrons between thebarrier layer 18 and thechannel 16 is achieved by using In0.7Ga0.3As as the low band gap material for thechannel layer 16. In0.7Ga0.3As channel can have electron mobility of greater than 10,000 cm2/Vs at room temperature. In addition, In0.7Ga0.3As has a higher electron affinity, 4.65 eV, than that of In0.52Al0.48As which can further increase the conduction band offset. However, oxidation of InAlAs poses a challenge which needs to be addressed via proper surface passivation prior to gate dielectric deposition. - It is noted that each of the III-V compound semiconductor layers employed in the present invention is a single crystal material of typical commercial quality. By “typical commercial quality” it is meant that each of the III-V compound semiconductor layers have a defect density on the order of about 105 atoms/cm2 or less, with a defect density of less than about 5000 atoms/cm2 being more typical. The typical commercial quality of the III-V compound semiconductor layers is a result of utilizing an epitaxial growth process such as, for example, molecular beam epitaxy (MBE) or metalorgano chemical vapor deposition (MOCVD). That is, each of the III-V compound semiconductor layers are formed by an epitaxial growth process that produces a high quality, single crystal III-V film. The deposition of each of the III-V compound semiconductor layers of the preset invention may be performed in the same or different apparatus. Moreover, each of the III-V compound semiconductor layers can be formed without breaking vacuum during the deposition of each of the layers. Alternatively, vacuum may be broken during the formation of an individual III-V compound semiconductor layer.
- The III-V compound semiconductors are epitaxially grown utilizing III/V-containing precursors that are well known to those skilled in the art. When the vacuum between the deposition of each of the III-V layers is not broken, the precursors can be switched to provide the next layer. In some embodiments, a graded III-V compound semiconductor layer can be formed.
- When a delta doped region 18A is formed into the lower region of the barrier layer 18A, an in-situ doping deposition process can be used in which the dopant atom is introduced during the initial formation of the barrier layer and following the formation of a desired thickness of the delta doped region (typically on the order of about 0.1 to about 2.0 nm), the dopant is removed from the precursor stream and the
barrier layer 18 formation continues. Alternatively, the delta doped region 18A can be formed utilizing ion implantation after thebarrier layer 18 has been formed. The conditions of such an implant are selected to provide a delta doped region next to, but not in contact with, the interface of theunderlying channel layer 16. - Each of the individual III-V compound semiconductor layers shown in
FIG. 1 are thin (providing a total thickness of less than 600 nm). Typically, thebuffer layer 14 has a thickness from about 25 to about 500 nm, with a thickness from about 100 to about 300 nm being even more typical. Thechannel layer 16 of the inventive structure has a thickness from about 1 to about 15 nm, with a thickness from about 5 to about 10 nm being even more typical. The thickness of thebarrier layer 18 of the inventive structure is from about 0.1 to about 10 mn, with a thickness from about 0.5 to about 10 nm being even more typical. - The applicants have formed a functional buried channel In0.7Ga0.3As MOSFETs with a HfO2 gate dielectric using a structure similar to that in
FIG. 1 , and have shown that these devices operate with much reduced gate leakage compared to Schottky-gated devices. Extracted drift mobility of 6600 cm2V-s, at an apparent carrier density of 3.2×1012 cm−2 was obtained. - Reference is now made to
FIG. 2 which illustrates apreferred heterostructure 12′ that is formed atop asemiconductor substrate 10. Thepreferred heterostructure 12′ comprises abuffer layer 14, achannel layer 16, anon-doped barrier layer 18 and a III-V compoundsemiconductor cap layer 20. - The III-V
semiconductor cap layer 20 is typically, but not always necessarily, a doped layer. The dopant within the III-V compoundsemiconductor cap layer 20 can be an n-type dopant or a p-type dopant, with an n-type dopant being more typical for an MOSFET. Unlike the delta doped region 18A described above, the doping within thecap layer 20 is evenly distributed throughout the entire vertical thickness of the layer. The concentration of dopant with thecap layer 20 is typically from about 1017 to about 1021 atoms/cm3, with a concentration of dopant within the cap layer from about 1018 to about 1020 atoms/cm3 being more typical. - The
cap layer 20 may comprise the same or different III-V compound semiconductor as thechannel layer 16. In a preferred embodiment of the present invention, thecap layer 20 comprises the same III-V compound semiconductor elements, but different alloy composition, as thechannel layer 16 except for the presence of dopants within thecap layer 20. - The
cap layer 20 is also a single crystal material of typical commercial quality since an epitaxial growth process such as MBE or MOCVD is used in forming the same. The doping of thecap layer 20 typically occurs during the deposition of the cap layer Alternatively, the dopants can be introduced into thecap layer 20 post deposition by ion implantation or outdiffusion from a doped layer that is formed atop thecap layer 20. - The thickness of the
cap layer 20 is from about 5 to about 50 nm, with a thickness from about 15 to about 30 nm being even more typical. - In a preferred embodiment of the
heterostructure 12′ shown inFIG. 2 , thebarrier layer 18 and thebuffer layer 14 are comprised of an alloy of InAlAs, while thechannel layer 16 and thecap layer 20 are comprised of an alloy of InGaAs. Thecap layer 20 is heavily doped with an n-type dopant. By “alloy of InAlAs” it is meant a composition of InxAl1-xAs wherein x is from about 0 to about 1, and more preferably from about 0.4 to about 0.6. In one highly preferred embodiment of the present x is 0.52. By “alloy of InGaAs” it is meant a composition of InyGa1-yAs wherein y is from about 0 to about 1, and more preferably y is from about 0.3 to about 0.8. In a highly preferred embodiment of the present invention, y is 0.7. - Reference is now made to
FIG. 3 which illustrates a FET (i.e., MOSFET) structure of the present invention including theheterostucture 12′ shown inFIG. 2 (with the cap layer patterned into patternedcap layer 20′ having at least one opening 21) atopsemiconductor substrate 10. It is emphasized that although the FET shown inFIG. 3 includes theheterostructure 12′ ofFIG. 2 , the present invention also contemplates a FET in which theheterostructure 12 ofFIG. 1 is used. When theheterostructure 12 shown in FIG. I is employed, the dielectric material (to be described herein below) is directly present on an upper surface of thebarrier layer 18. - The
FET 50 shown inFIG. 3 includes asemiconductor substrate 10 as described above, aheterostructure 12′ as described above including a patternedcap layer 20 having anopening 21 that exposes a surface of thebarrier layer 18, located on an upper surface of thesemiconductor substrate 10, adielectric material 30 located on the upper surface of the patternedcap layer 20 as well as within theopening 21 covering the sidewalls of the patternedcap layer 20′ and the exposed surface of thebarrier layer 18, agate conductor 32 located on a portion of saiddielectric material 30 and above saidopening 21, andsource contact 34 and adrain contact 36 abutting the outer edges of thedielectric material 30 and extending into at least thechannel layer 16; in the drawing the source/drain contacts (34, 36) extend into thebuffer layer 14. - In
FIG. 3 , Lg denotes the gate length which is defined by the distance of the remainingcap layer 20′ extending from theopening 21 to either the source or drain contact (34, 36). In one embodiment, the channel length is less than or equal to 260 nm. In some embodiments, the structure has a positive threshold voltage. - The
dielectric material 30 employed in the present invention has a dielectric constant of greater than 4.0; such a dielectric material is referred to hereafter as a high k dielectric. Typically, thehigh k dielectric 30 has a dielectric constant of about 7.0 or greater, with a dielectric constant of about 10.0 or greater being even more typical. The dielectric constants mentioned herein are relative to a vacuum, unless otherwise stated. Specifically, thehigh k dielectric 30 employed in the present invention includes, but is not limited to an oxide, nitride, oxynitride and/or silicates including metal silicates, aluminates, titanates and nitrides. In one embodiment, it is preferred that thehigh k dielectric 30 is comprised of HfO2 ZrO2,A1 2 0 3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, a pervoskite oxide, HfSiOz, HfAlOz or HfAlOaNb. Preferably, thehigh k dielectric 30 is a Hf-based dielectric material. - The
high k dielectric 30 is formed utilizing a conventional deposition process including, but not limited to molecular beam epitaxy (MBE), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition and other like deposition processes. - The thickness of the
high k dielectric 30 may vary depending on the deposition technique employed in fabricating the same as well as the composition and number of dielectrics of the high k dielectric. Typically, thehigh k dielectric 30 has a thickness from about 0.5 to about 20 nm, with a thickness from about 1 to about 10 nm being highly preferred. - The
gate conductor 32 of the present invention includes any conductive material such as, for example, polysilicon, polysilicon germanium, conductive metals, conductive metal alloys, conductive silicides, conductive nitrides and combinations or multilayers thereof. When metallic-containing gate conductors are employed, the metallic gate conductor can be doped so as to shift the workfunction of the gate conductor. Illustrative examples of dopant ions include As, P, B, Sb, Bi, Al, Ga, Ti or mixtures thereof. The same dopants are also used with polysilicon or polySiGe mentioned above. Preferably, thegate conductor 32 is a conductive metal, with Al, Pt, Au, W and Ti being highly preferred. The selection of metal gates is advantageous since conductive metals have different workfunctions that permit one to adjust the threshold voltage of the device. - The
gate conductor 32 is formed by a conventional deposition process such as, for example, CVD, PECVD, PVD, plating, thermal or ebeam evporation and sputtering. The gate conductor may be patterned by lithography and etching. Alternatively, thegate conductor 32 is formed by a conventional lift-off process. - The source and drain contacts (34, 36), which are on either side of the
gate conductor 32, are typically comprised of a conductive material including one of the conductive materials mentioned above for thegate conductor 32. The contacts are formed by lithography, etching a trench into thegate dielectric 30 and filling the trench with a conductive material. - In some embodiments of the present invention, the
barrier layer 18 may include a thin passivation layer (not shown). When present, the thin passivation layer may comprise a thin layer of a chemical oxide. Alternatively, the passivation layer may include a thin layer of amorphous Si/SiO2 or Ge/Si/SiO2. The thin passivation layer has a thickness from about 0.5 to about 30 nm. - The optional passivation layer is formed by cleaning the surface of the
barrier layer 18 to remove any residual layers (e.g., native oxides), foreign particles, and any residual metallic surface contamination and to temporarily clean the barrier surface. Any residual oxide is removed in a solution of hydrofluoric acid, for example. Other wet etching solutions can also be used to form the optional passivation layer. Alternatively, treatment with a hydrogen plasma alone, or in conjunction with a chemical wet etchant may also be used to form the optional passivation layer. - In some embodiment, the
dielectric material 30 not protected by thegate conductor 32 can be removed and a selective epitaxial semiconductor layer can be formed adjacent the gate conductor to provides raised source/drain regions that lower the source/drain series resistance. Examples of selective epitaxial semiconductor layers that can be used include, but are not limited to InGaAs having an In content that varies from 40 to 80% or Ge. - In the following example, an undoped In0.7Ga0.3As/In0.52Al0.48As quantum well layer structure was used as shown in
FIG. 2 . The layer structure was grown on an InP substrate, and consisted of a 300 nm In0.52Al0.48As buffer layer, a 10 nm strained In0.7Ga0.3As channel, a 10 nm In0.52Al0.48As top barrier layer and a 25 nm n+−In0.53Ga0.47As cap layer. Aside from the top In0.53Ga0.47As layer which was etched away in the gate region; all layers were not-intentionally doped. - Device Fabrication
- Long and short channel MOSFETs with metal gates and high k dielectrics were fabricated using the above layer structure. Long-channel ring FET devices were made by patterning the heterostructure using optical lithography followed by selectively etching the InGaAs cap layer to form a gate recess area. After gate dielectric deposition, Ohmic contacts (i.e., source/drain contacts) were then formed. The gate regions were then defined by optical lithography and metal lift off. The short-channel device fabrication included an additional mesa isolation step before the gate lithography. In addition, the gate recess was patterned by electron-beam lithography, where gate lengths as short as 260 nm were fabricated. The long-channel devices utilized MBE-deposited HfO2 and had Al gates, while the short-channel devices had ALD-Al2O3 as a gate dielectric and Al or Pt as the gate conductors.
- Long-channel MOSFETs
- The DC output characteristics of a typical buried In0.7Ga0.3As channel MOSFET with Lg=5 μm are shown in
FIG. 5 . The devices showed good saturation and pinch off characteristics. A series resistance of 128 Ω was observed despite, the long channel length, an issue that may, in part, be due to non-optimized contact formation. The sub-threshold characteristics and corresponding transconductance are shown inFIGS. 6A-6B . The devices operate in enhancement mode and had a threshold voltage of 0.25 V, as determined by linear extrapolation from the peak transconductance at Vds=50 mV. The drain current on-off ratio was approximately 104, and the devices had a sub-threshold slope of 150 mV/decade. The extrinsic transconductance, gmext, had a peak value of 23 mS/mm at Vds=1.2 V. The gate leakage characteristics are shown inFIG. 7 , and were compared with prior art HEMTs. The gate leakage current density of the MOSFET was more than 200× lower than the Schottky-gated devices. The capacitance-voltage results for the MOSFETs are shown inFIG. 8 . The effective-oxide thickness (EOT) extracted from the data was 4.4+0.3 nm, The interface state density for these device was in the high 1012 cm−2/eV range, and this value could account for the non-ideal sub-threshold slope. After correcting for the series resistance, the effective drift mobility and the sheet density were calculated from the Cg vs. Vgs (100 kHz) and linear Id-Vgs characteristics (Vds=50 mV). The resulting mobility vs. sheet density plot is shown inFIG. 9 . A peak mobility of 1100 cm2/Vs was determined at a carrier density of 2.6×1012 cm−2. Further improvements should be possible through optimization of the interface properties. - Short-Channel MOSFETs
- As shown in
FIG. 10 , the short-channel MOSFETs (Lg=260 nm) had good saturation characteristics, but had high series resistance due to long access regions and non-ideal contacts. Depending upon the gate metal utilized, the devices were made to operate in both enhancement mode (Vt=+0.5 V), and depletion mode (Vt=−0.2 V), as shown inFIGS. 11 and 12 . The enhancement-mode devices had on-off ratio of approximately 103 at Vds=50 mV, and sub threshold slope of approximately 200 mV/dec (See,FIG. 11 ). For these devices, gmext, had a peak value of 43 mS/mm at Vds=1.2 V. The gate leakage as inFIG. 13 shows considerable improvement over previous HEMT devices. - While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
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Also Published As
Publication number | Publication date |
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WO2007149581A8 (en) | 2009-02-26 |
WO2007149581A3 (en) | 2008-08-28 |
WO2007149581A2 (en) | 2007-12-27 |
US20080296622A1 (en) | 2008-12-04 |
US7964896B2 (en) | 2011-06-21 |
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