JPH06209019A - Hetero junction field-effect transistor - Google Patents

Abstract

PURPOSE:To realize a high speed and low noise by providing an undoped semiconductor layer wherein energy level of a conductive band is lower than energy level of a channel layer between a channel layer and a barrier layer at a specified thickness. CONSTITUTION:An i-InAlAs buffer layer 7 and a p-InGaAs buffer layer 6 are formed on an InP substrate, and an n-InGaAs channel layer 1, an i-InAs carrier storage layer 2, an i-InAlAs barrier layer 3 and an i-InGaAs cap layer 4 are formed thereon at thicknesses of 15, 1, 10, and 5nm, respectively. After a gate electrode 9 is formed and a surface thereof is coated with an SiO2 film 8, the SiO2 film 8 is removed only in an ohmic layer formation region. The channel layer 1 in the ohmic layer formation region is etched using the SiO2 film 8 as a mask. An ohmic layer 5 is formed by selectively forming the n-InGaAs layer 5 using the SiO2 film 8 as a mask, and an ohmic electrode (Ti/Au) 10 is formed thereon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heterojunction field effect transistor, and more particularly to a device structure which has high speed and low noise.

[0002]

BACKGROUND OF THE INVENTION GaAs MESFET (Me tal S emicondu
To shorten the gate length in order to improve the performance of the ctor FET ),
Although it is necessary to thin the channel as the gate length is shortened, in order to keep the threshold voltage (Vth) constant, it is necessary to thin the layer and simultaneously increase the concentration of the channel. However, increasing the concentration of the channel deteriorates the Schottky characteristics of the gate electrode, and the gate forward direction allowable voltage (Vf) and the gate breakdown voltage (BVg
There is a problem that causes a decrease in s). A method for dealing with the problem of Vf and BVgs lowering by inserting another semiconductor layer having a large band gap between the channel and the gate electrode has been reported in Japanese Patent Laid-Open No. 3786/50. An example of a device structure according to the prior art is shown in FIG. By providing the i-Al ₀₃ Ga ₀₇ As barrier layer 3 on the n-GaAs channel layer 1 to form a heterojunction structure, it is possible to improve Vf by about 0.3V and BVgs by about 1V.

[0003]

In the above-mentioned prior art heterojunction FET, the barrier layer 3 is provided to suppress the decrease in Vf and BVgs due to the increase in the concentration of the channel, but the decrease in carrier mobility results. Channel current noise
It is impossible to suppress the increase of (hereinafter, simply referred to as noise). Actually, since the travel distance of carriers is shortened by shortening the gate length, the decrease in mobility and the increase in noise are deducted, and both do not become a big problem, but if the concentration of the channel is increased, it should be mitigated. If it is possible, the heterojunction FET of the prior art described above can achieve higher performance by improving the mobility and reducing the Ids noise. Therefore, the purpose of the present invention is to increase the doping concentration (N _D ) of the channel.
The object is to provide a heterojunction FET that achieves higher speed and lower noise than the conventional one by suppressing the increase amount of.

[0004]

The above-mentioned object is to provide an undoped semiconductor layer whose energy level (E _C ) of the conduction band is lower than E _{C of the} channel layer in the case of an n-channel, to form a channel layer and a barrier layer. It can be achieved by providing a thickness of 1 to 10 atomic layers in between. Further, the undoped semiconductor layer in the case of p-channel energy level of the valence band (E _V) is above than E _V of the channel layer (hereinafter, referred to as a carrier accumulation layer) between the channel layer and the barrier layer It can be achieved by providing a thickness of 1 to 10 atomic layers.

[0005]

The Vth of the heterojunction FET is such that the barrier layer thickness is d ₁ and the channel layer thickness is d _2, and the dielectric constants of the barrier layer and the channel layer are ε, ignoring the difference in relative dielectric constant between them. Then, in the case of n channel, the formula (1) is used, and in the case of p channel,
It can be approximated by equation (2).

[0006] Here, φ _Bn , φ _Bp : Schottky barrier height N _{D of} gate electrode, N _A : Carrier concentration of channel ΔE _C : Band discontinuity of conduction band between barrier layer and channel layer ΔE _V : Barrier layer and channel Band discontinuity in the valence band of a layer Conventionally, when d ₂ was made small, the third term of equation (1) or (2) was maintained by increasing N _D or N _A. . In the present invention, the carrier accumulation layer increases ΔE _{C in} the equation (1) or ΔE _{V in the} equation (2), so that the third term can be reduced by the change in ΔE _C or ΔE _V , and Vth can be reduced. It is possible to reduce the amount of increase in N _D or N _A required to keep it constant. By reducing N _D or N _A , carrier mobility is improved and noise is reduced. Therefore, the FET of the present invention can achieve higher speed and lower noise than conventional FETs.

However, the semiconductor material used for the carrier storage layer is often lattice-mismatched with the channel layer, and dislocations, defects, etc. may be induced at the junction with the channel layer. It is necessary to control the thickness to about 1 to 10 atomic layers. With this thickness, the crystal lattice of the carrier storage layer can be lattice matched with the channel layer,
Generation of dislocations and defects can be suppressed.

Since the carrier storage layer also has the effect of attracting the carriers of the channel layer to the gate side, the present invention reduces the transconductance (gm) due to the reduction of the effective channel depth (the distance between the gate electrode and the channel). There is also an effect that the improvement of the short channel effect can be achieved by improving the leakage current to the substrate side (substrate current).

The effect of the present invention will be described below with reference to FIG. This figure is an energy band diagram of InAlAs / InGaAs HIGFET, and the HIGFET shows different operation modes depending on the application condition of the gate voltage (Vgs). If Vgs is less than the flat band voltage (V _{F B} ) of the channel, then HI
The GFET becomes a MESFET mode in which Ids is controlled by the expansion of the depletion layer due to the Schottky junction of the gate.
When Vgs is larger than V _FB , Ids is controlled by the amount of carriers accumulated at the interface between the channel layer 1 and the barrier layer M
The ISFET (M etal I nsulator S emiconductor FET) mode.

FIG. 4A shows the case of Vgs <V _FB , i-
Assuming that the thickness of the InAlAs barrier layer 3 is 10 nm, the thickness of the n-InGaAs channel layer 1 is 15 nm, and the thickness of the p-GaAs (3 × 10 ¹⁶ / cm ³ ) buffer layer 6 is 300 nm, the carrier storage layer 2 is If not provided, the doping concentration of the channel layer 1 must be N _D = 4 × 10 ¹⁸ / cm ³ in order to adjust Vth to −0.6V. However, as the carrier storage layer 2, i-
When InAs is inserted in a two-atom layer, N _D can be reduced to 3 × 10 ¹⁸ / cm ³ , and the electron mobility is improved by about 8%.

An increase of 8% in electron mobility has the effect of improving gm by several% (depending on the voltage application condition) and reducing Ids noise by about 4%.

FIG. 4B shows the case where Vgs = _VFB , and some electrons move from the channel layer 1 to the InAs layer 2. Since the mobility of the undoped InAs layer 2 is higher than that of the impurity-doped channel layer 1, the overall electron velocity is increased by the amount of the electrons moved to the InAs layer 2, and the noise is also reduced by the increased amount of the electron velocity. . Therefore, in this mode, in addition to the reduction of N _{D in} the channel layer, some electrons are undoped InAs
Since the effect of moving to the layer 2 is also added, the improvement of gm and the reduction of noise are larger than in the case of FIG.

FIG. 4C shows the case of Vgs> V _FB . In this mode, most of the electrons are attracted to the InAs layer 2, so the effective channel depth (distance between the gate electrode and the channel) is The effect of shortening is also added to further improve gm as compared with the case of FIG.

[0014]

【Example】

[Embodiment 1] As one embodiment of the present invention, InAlAs / InG
DC of aAs structure (D oped C hannel) -HIGFET ( H etero
The device cross-sectional view of the structure I nsulated G ate FET) shown in FIG. The figure is an n-channel HIGFET, and the manufacturing process will be described with reference to FIG.

(A) An i-InAlAs buffer layer 7 and a p-InGaAs (2 × 10 ¹⁶ / cm ³ ) buffer layer 6 are grown on an InP substrate, and n-InGaAs (2 × 10 ¹⁸ / cm ³ ) is grown thereon. ) Channel layer 1, i-
InAs carrier storage layer 2, i-InAlAs barrier layer 3, i
-InGaAs cap layers 4 are formed by MBE (Molecular Beam Epitaxial) with a thickness of 15, 1, 10, 5 nm respectively.

[0016] After performing element isolation by (b) wet etching to form a gate electrode (WSix) 9, after the surface is coated with the SiO ₂ film 8, only ohmic layer forming region by dry etching the SiO ₂ film 8 To remove.

(C) After etching the channel layer 1 in the ohmic layer forming region using the SiO ₂ film 8 as a mask, annealing is performed to recover etching damage.

(D) n-InG using the SiO ₂ film 8 as a mask
The ohmic layer 5 is formed by selectively growing the aAs (1 × 10 ¹⁹ / cm ³ ) layer 5 by MOVPE (metal organic chemical vapor deposition) method, and the ohmic electrode (Ti / Au) 10 is formed thereon. The HIGFET of the present invention is completed by wiring.

It is possible to use n-InAs instead of i-InAs for the carrier storage layer 2, but this causes deterioration of the pinch-off characteristics of the FET. In this case, therefore, the concentration of the n-InAs layer is lower than that of the channel layer 1. It is desirable to keep it within one digit.

As the barrier layer 3, it is also possible to use a p-InAlAs layer having a low concentration such that the entire layer is depleted by the junction with the n-InGaAs layer 1.

In this embodiment, InAlAs / InAs / InGaAs is used.
As described in the structure, the carrier storage layer 2 has IAs as well as InAs.
It is also possible to use nSb, GaSb, or the like, and the channel layer 1 can be made of a material such as GaAs, InP, or GaSb. The barrier layer 3 is made of AlGaAs, AlAs, InG.
It is also possible to use materials such as aP, AlGaP, InGaAsP, AlGaSb, and AlGaSb.

Although the above embodiment has been described for the case of an n-channel, the present invention can be applied to a p-channel FET.

[Embodiment 2] In Embodiment 1, the case of the HIGFET structure was described, but the present invention is a heterojunction ME.
It is also possible to apply the SFET or JFET (J unction FET), in the case of the heterojunction MESFET barrier layer 3
May have the same conductivity type as the channel layer 1.

In this case, the carrier storage layer 2 can reduce the doping concentration of the channel layer 1 and the barrier layer 3, and the carrier mobility can be improved and the noise can be reduced by reducing the doping concentration (see FIG. 4A). Can be achieved.

In the case of a JFET, the barrier layer 3 may have a conductivity type opposite to that of the channel layer 1. In this case, the effect that the carrier storage layer attracts carriers to the gate side (see FIG. 4C) improves gm. Can be achieved.

[Third Embodiment] The present invention can also be applied to a MISFET, for example, i-GaA is used for the channel layer 1.
s, or a low concentration of p-GaAs, is used for the barrier layer 3 with Ca.
N channel MISFET using F ₂ or AlN layer
Then, by providing the i-InAs carrier storage layer 2, electrons can be attracted to the gate side and gm can be improved.

When an insulating film such as SiO ₂ or Si ₃ N ₄ is used for the barrier layer 3, InAs has a smaller interface state with the insulating film than GaAs. Therefore, by providing the i-InAs carrier storage layer 2, GaAs is formed. And InGaAs channel layer 1 and barrier layer 3
It is possible to reduce the interface state between and, and it is possible to achieve further noise reduction.

The barrier layer 3 may be made of an amorphous semiconductor other than the insulating film.

[Embodiment 4] Although the above embodiment has been described in the case of a compound semiconductor, the present invention can be applied to a Si-based semiconductor, and a JFET using Si or SiC for the channel layer 1 or In the MISFET, a carrier storage layer 2 made of SiGe is formed at the interface between the channel layer 1 and the barrier layer 3.
By providing 10 to 10 atomic layers, gm can be improved.

[0030]

According to the present invention, it becomes possible to reduce the doping concentration of the channel of the heterojunction FET.
It is possible to speed up ET and reduce noise.

[Brief description of drawings]

FIG. 1 is a sectional view of a HIGFET according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the HIGFET of FIG.

FIG. 3 is a sectional view of a conventional heterojunction FET.

FIG. 4 is an energy band diagram for explaining the effect of the present invention.

[Explanation of symbols]

1 ... Channel layer, 2 ... Carrier storage layer, 3 ... Barrier layer,
4 ... Cap layer, 5 ... Ohmic layer, 6, 7 ... Buffer layer,
8 ... Insulating film, 9 ... Schottky electrode, 10 ... Ohmic electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H01L 29/808 7376-4M H01L 29/80 C (72) Inventor Junji Shigeta 1 Higashi Koikeku, Kokubunji, Tokyo 280-chome, Central Research Laboratory, Hitachi, Ltd.

Claims (4)

[Claims] 1. A first semiconductor layer having n-type conductivity and a second semiconductor made of a semiconductor having an electron affinity smaller than that of the first semiconductor layer.
A semiconductor layer and a heterojunction field effect transistor having a gate electrode formed on a side of the second semiconductor layer opposite to the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are Between the first semiconductor layer and an impurity having an electron affinity higher than that of the first semiconductor layer and not intentionally doped with impurities or having an n-type conductivity at a lower concentration than that of the first semiconductor layer. A heterojunction field effect transistor, characterized in that the third semiconductor layer having a thickness of 1 to 10 atomic layers is provided. 2. A first semiconductor layer of p-type conductivity type, a second semiconductor layer made of a semiconductor having a larger sum of electron affinity and energy gap than that of the first semiconductor layer, and the second semiconductor layer. In the heterojunction field effect transistor having a gate electrode formed on the side opposite to the first semiconductor layer, between the first semiconductor layer and the second semiconductor layer more than the first semiconductor layer. A third semiconductor layer formed of a semiconductor having a small sum of electron affinity and energy gap and not intentionally doped with impurities or doped with impurities exhibiting p-type conductivity at a concentration lower than that of the first semiconductor layer. Is provided with a thickness of 1 to 10 atomic layers. 3. An n-type conductive first semiconductor layer, a potential barrier layer made of an insulator or an amorphous semiconductor, and a potential barrier layer formed on a side of the potential barrier layer opposite to the first semiconductor layer. In a heterojunction field effect transistor having a gate electrode, a heterojunction field effect transistor is made of a semiconductor having an electron affinity higher than that of the first semiconductor layer and is not intentionally doped with impurities between the first semiconductor layer and the potential barrier layer, or The second semiconductor layer doped with impurities exhibiting n-type conductivity at a concentration lower than that of the first semiconductor layer is
A heterojunction field effect transistor, which is provided with a thickness of 10 atomic layers. 4. A first semiconductor layer of p-type conductivity type, a potential barrier layer made of an insulator or an amorphous semiconductor, and a potential barrier layer formed on the opposite side of the first semiconductor layer. In a heterojunction field effect transistor having a gate electrode, the heterojunction field effect transistor is made of a semiconductor having a sum of electron affinity and energy gap smaller than that of the first semiconductor layer and intentionally containing impurities between the first semiconductor layer and the potential barrier layer. A second semiconductor layer, which is not doped or is doped with an impurity exhibiting p-type conductivity in a concentration lower than that of the first semiconductor layer, is provided in a thickness of 1 to 10 atomic layers. Junction field effect transistor.