TW201117342A - Integrated circuit structures - Google Patents

Abstract

An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit structure, and more particularly to a transistor including a ΙΠ·ν group compound semiconductor and a method of manufacturing the same. 3 [Prior Art] There is a close correlation between the speed of a metal-oxide semiconductor (MOS) transistor and the driving current of an M〇s transistor, and the driving current of the M〇s transistor and the rate of charge mobility are Closely related. For example, when the electron mobility is high in the channel region, the NM〇s transistor has a high voltage. When the hole mobility is high in the channel region, the PMOS% solar field has a driving current of 咼.

A compound semiconductor material composed of a group III and group V element (generally referred to as a group III-V compound semiconductor) is used as a good candidate material because of having a high electron shift to form a 嶋S transistor. Since the = ι ι ι ν 化合物 化合物 常 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了 了Fig. 1 is a view showing a conventional crystal of a compound semiconductor of a compound semiconductor. During the formation process, a multilayer material is blanket formed on the -11 substrate i, basin

The y layer material includes a buffer layer 2 formed of GaAs, a top barrier formed by a gradient buffer layer 3, 4 ' In-A1-As S formed by & A and TtX being, but not equal to G and U The layer 6, the (10) butterfly etch stop layer 7, and the contact layer 〇 503-A34280TWF/jamngwo 3 201117342 formed by In〇53Ga〇47As, the contact layer 8 is stopped and the stop layer 7 is formed to form - A concave. Next, a real step is to etch through the etch to terminate the acoustic x layer 7 and etch into the top barrier layer to form a second recess. Next, a gate structure (consisting of metal) 10 is formed in the second recess. The upper crystal has the advantage that the resulting quantum well is composed of a bottom barrier layer, a via, and a top barrier layer. The above-mentioned transistors still have many disadvantages. It is very difficult to dope high concentration impurities into the III-V compound semiconductor. For example, Si implantation or in_situ can be mixed in GaAs as a replacement iron and the maximum doping concentration is only between 1〇n/cm3 and 1〇1Vcm3^. In addition, the low energy density of the conduction band results in a high source/drain resistance that avoids an improvement in the final transistor drive current. Therefore, there is a need in the industry for methods and structures that overcome the aforementioned shortcomings of the prior art. SUMMARY OF THE INVENTION Embodiments of the present invention provide an integrated circuit structure including: a substrate; a channel is disposed on the substrate, wherein the channel includes a first group compound semiconductor composed of a Ιπ group element and a V group element a material; a gate structure is disposed on the channel; and a source/drain region is adjacent to the channel, wherein the source/drain region includes a group IV region selected from a group substantially comprising 矽, 锗, And combinations of the above.

An embodiment of the present invention further provides an integrated circuit structure, comprising: a semiconductor substrate; a channel is disposed on the semiconductor substrate, wherein the channel comprises a first IIIV 〇 503- composed of a group III element and a group V element. A34280TWF/jamngwo 4 201117342 Group compound semiconductor material · The pole gap is located on the channel in the pole structure; one, the recess is the right one. a side wall of the structure; a recess adjacent to the pass-out pole domain μ portion is lower than the bottom of the channel; and a source//and pole & field is located in the recess, the complex region is selected from the The group is 'on:', the extreme drain region includes -1ν and the vertical (four)m includes 矽, 锗, and combinations of the above, and, in the source/drain region. A hetero-type dopant or a p-type dopant further provides an integrated circuit structure including: a two-fin structure on the substrate, wherein the off-type. Included by the group III element and the v group, : two = body: 枓, a part of the idle pole structure is directly set to the additional part set on the ... and - source / secret area adjacent to the fin type bungee area including a 1 ¥ The family secrets H ώ /, source / record, and the above-mentioned combination domain are selected from the group, in order to make the invention more obvious (4), the following is a special _, and with the drawing The detailed description is as follows: - [Embodiment] Hereinafter, examples of the embodiments will be described in detail with reference to the accompanying drawings, which are considered as reference. The same drawing numbers are used in the similar or identical parts in the drawings or the description of the specification. In the drawings, the shape or thickness of the embodiment can be expanded and simplified or conveniently marked. In addition, the parts of the various elements in the drawings will be described separately, = It is noted that the elements not shown or described in the drawings are the technology of the art 2 0503-A34280TWF/jamngw〇 5 201117342

Forms known to those of ordinary skill in the art are those which disclose the particular mode of use of the invention and the method of making the novel transistor. Embodiments of the intermediate stages of the manufacturing method are not described. In the embodiments of the invention, various reference numerals are used to indicate similar elements. _凊 Referring to Figure 2, a substrate 20 is provided. Substrate 20 can be a half-conductor substrate composed of tantalum, niobium, SiGe, and/or other semiconductor materials. An insulating structure such as a shallow trench isolation (STI) region 30 is formed in the substrate 2A. Referring to Figure 3, a portion of the substrate 2 is etched to form a recess 22 between the sidewalls of the opposing two shallow trench isolation (STI) regions 30. Next, as shown in FIG. 4A, a plurality of layers of material including a bottom barrier layer 24, a channel layer 26, and a top barrier layer 28 are epitaxially grown in the recess 22. In one embodiment, the channel layer 26 has a first bandgap, and the bottom barrier layer 24 and the top barrier layer 28 have a second energy gap greater than the first energy gap. Accordingly, a quantum well is formed by the bottom barrier layer 24, the channel layer 26, and the top 4 barrier layer 28. The second energy gap is larger than the first energy gap by about 1. 1 eV ’ However, a larger or smaller gap can also be applied. Suitable materials for the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28 may be selected by comparing energy gaps of semiconductor materials having high carrier mobility, including, but not limited to, semiconductor materials. Yu, Shi Xi, 锗, GaAs, InP, GaN, InGaAs, InAs, InSb, InAlAs,

GaSb, AlSb, A1P, GaP, and combinations of the above materials. The channel layer 26 0503-A34280TWF/jamngwo 6 201117342 is formed by the group - ηι-ν grouping of the family of 疋 和 and ¥ = elements. In a comparative embodiment, the channel layer '% 〇-3AS and the bottom barrier layer 24 and the top barrier layer 28 comprise n〇.52Al0.48As. In other embodiments, the channel layer % and the bottom barrier layer 24 and the top barrier layer 28 include other vias 'the channel layer 26 including InAs' and the bottom portion 24 and the top barrier layer 28 include InAUs ==:~ to _""The second two have a ", the spoon 2 is fine to 5 〇 fine, the top barrier layer μ can have a degree of dry circumference of about 5 nm ^ 5 〇 () nm. However, it should be understood that all dimensions mentioned herein are for illustrative purposes only and that the techniques of forming may vary. . Optionally, an additional buffer layer is formed over the substrate 2 and over the underlying semiconductor layer, such as under the bottom barrier layer 24. = can have a lattice constant between the base 2 〇 lattice 2: turn only less dog. By the shallow trench isolation 4, the channel layer 26, and the top barrier layer 28, the defects generated in the new growth layer are significantly less. Figure 4 shows an alternative embodiment in which the layers 24, '' are formed in a blanket pattern on the semiconductor substrate 2''. Fig. 5 shows a cross-sectional view showing the gate structure and the gate spacer %. The gate structure includes a gate dielectric layer 32 and an open electrode 34. The thyristor layer 32 may be composed of a conventional dielectric material such as oxidized oxide, nitrogen, oxycide, a multilayer material as described above, and combinations of the foregoing. °5〇3-A34280TWF/jamngwo ? 201117342 The interlayer dielectric layer 32 may also be composed of a high dielectric constant (M_ dielectric material. Examples of the high_k dielectric material may have a k value of even greater than 7.0, and may include oxidation Aluminium, . . . 石 铪 铪 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 梦 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛 钛Metal material, and similar materials. The interpole spacer 36 may be composed of a combination of oxidized stone, cerium nitride, and the like, and the gate spacer 36 is a structure known in the art, and thus A detailed description thereof is omitted. Referring to Fig. 6, a recess 38 is formed. In a comparative embodiment, an -etching step is used, so that the sidewall of the recess 38 is vertically aligned with the outer edge of the gate spacer 36. As an embodiment, the sidewalls of the recessed % described herein are aligned with the outer (four) of the gate spacer 36, and those of ordinary skill in the art should understand that the qualifications are intended to encompass process variations and process variations. Misalignment caused by Jiahua The bottom surface of the recess 38 may be lower than the bottom surface of the channel layer 26. Referring to Figure 7A, a Group IV semiconductor material is epitaxially grown in the recess 38, thereby forming a source and drain region 42 (hereinafter referred to as a source) In the embodiment, the source/drain region 42 may be composed of germanium, germanium, or germanium (SiGe). If the final transistor is to be an NMOS transistor, the source The pole/drain region 42 may be doped with an η-type dopant such as phosphorus, arsenic, antimony, and combinations of the above dopants. If the final transistor is to be a PMOS transistor, the source/drain region 42 may Doping a p-type dopant, such as boron, indium, and a combination of the above dopants. The η-type dopant or ρ-type dopant may be epitaxial with the source/drain region 42 0503-A34280TWF/jamngwo 8 201117342 In-situ doping in the process, or after the stray growth source/nomogram region 42 is performed. The η-type or p-type dopant The doping concentration may range from about lxl 〇 18/cm 3 to l x l 021 / cm 3 . In this embodiment, the source/drain region 42 may also be referred to as a group IV semiconductor region 46. 7B shows an alternative embodiment in which the epitaxially grown source/drain regions 42 comprise epitaxially grown III-V compound semiconductor regions 44 (hereinafter collectively referred to as buffer layers), and the group IV semiconductor regions 46 are The buffer layer 44 may be composed of a III-V compound semiconductor, and φ includes, but is not limited to, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination of the above materials. And the above multilayer materials. The buffer layer 44 can have a horizontal portion on the bottom of the recess 38 (Fig. 6) and a vertical portion on the side wall of the recess 38. In one embodiment, the buffer layer 44 includes a gradient composition having a composition in which the lower portion gradually changes to a desired higher portion. Furthermore, the lower portion of the buffer layer 44 may have a lattice constant closer to the lattice constant of the channel layer 26, and the upper portion of the buffer layer 44 may have a lattice constant closer to the Group IV semiconductor. The lattice constant of region 46. The lattice constant between the buffer layer 44 and the substrate 20 does not match and may gradually increase from the bottom of the buffer layer 44 to the top of the buffer layer 44. In a comparative embodiment, the channel layer 26 is composed of In0.7Ga0.3As, and the source/drain region 42 is composed of germanium. The lattice constant does not match between In〇.7Ga〇.3As and germanium. The sex is about four percent. In view of this, the buffer layer 44 may have an indium content of less than 0.7%. The buffer layer 44 may also be formed of a multi-layered structure composed of unevenness, for example, In0.2Ga0.8As or a gradient layer having a percentage of sound gradually increasing from the bottom toward the top. 0503-A34280TWF/jamngwo 9 201117342 The buffer layer 44 can be doped. If the final transistor is to be an NM〇s f crystal, the doped impurities include Shi Xi (Si). Conversely, if the final transistor is to be a PM〇S transistor, the doped impurities include zinc (Zn) and/or beryllium (Be). It can be observed that the germanium in the source/drain region 42 has a larger lattice mismatch than the lattice mismatch of the m_v compound semiconductor in the channel layer 26. The larger lattice mismatch results in a high defect density and results in a high junction leakage current. By forming the buffer layer 44', the lattice mismatch between the channel layer 26 and the adjacent source/drain regions can be reduced, resulting in reduced junction leakage current. Second, as shown in Figures 8A and 8NB. The germanide region 5 〇 (which may also be or include a germanide) is formed on the source/drain region 42. Since the source/drain region 42 includes germanium and/or germanium, the formation of germanide The method can form a metal layer by blanket; applying an annealing step to react the only layer with the ruthenium and/or ruthenium of the underlayer; and removing the unreacted portion of the metal layer. The transistor 52 is fabricated. Referring to Fig. 9, the quantum well composed of the bottom barrier layer 24, the channel layer 26, and the top barrier layer 28 may be replaced by a channel layer 54. The channel layer 54 may be made of a ΙΠ·ν compound semiconductor material. Composition, for example

GaAs, InP, GaN, InGaAs, InAs, InSb, InAlAs, GaSb,

AlSb, AlAs, A1P, GaP, and combinations of the above materials. Figure 10 shows an alternative embodiment similar to the embodiment shown in Figures 8a and 8NB, except that the gate dielectric layer is not formed. The gate electrode 34 is in direct contact with the top barrier layer 28. In this example, the depletion region (not shown) caused by the Schottky barrier 0503-A34280TWF/jamngwo 201117342 (SchoUky barrier) between the gate electrode 34 and the top barrier layer 28 functions as a gate dielectric layer. Figure 11 shows a similar structure as shown in Figure 9, in which no gate dielectric layer is formed. Again, in Figures 9 through 11, the source/drain regions 42 may include only the doped 矽/锗/siGe regions adjacent to the channel layer % (or 54), or doped 矽/锗/ The buffer layer 44 of the SiGe region and the bottom layer. The embodiments discussed in the above paragraphs can be applied to fin field effect transistors (FinFETs). Referring to Fig. 12, a junction structure 60, a gate dielectric layer 32, a gate electrode 34, and a gate spacer 36 (not shown) are formed. The details of the formation of the fin structure 60 are disclosed in the co-pending application of the present application: U.S. Patent Application Serial No. 61/182,550, issued May 29, 2009, entitled "Gradient Ternary or Quaternary Multiple-Gate transistor", at j : 匕 cited as a reference. The fin structure 60 may comprise a III-V compound semiconductor material. • Next, as shown in Fig. 13, the structure in which the fin structure 60 is exposed is removed. The portion of the fin structure 60 covered by the gate electrode 34 and the gate spacer 36 can be protected from being etched into a recess. In Fig. 14, the source/gt; and the pole region 42' are grown in a staggered manner and are formed of substantially the same material as discussed in the previous paragraph. The same 'source/nomogram region 42 may comprise a buffer layer 44 between the group IV semiconductor regions 46, or only a ιν semiconductor region. Fig. 15-17 is a schematic cross-sectional view showing an alternative embodiment, wherein the cross-sectional views are derived from the straight cut surface of the slanting 0503-A34280TWF/jamngwo 11 201117342 along the cutting line 第-Α in Fig. 14. In the U-picture, the gate dielectric layer is not formed. Gate electrode imaginary top crucible structure 6G. In this example, a Schottky barrier is shown between the layers 28 of the impurity electrode 34: the spent region (not shown) functions as a gate dielectric layer. Jude 16's quantum well is formed by a fin structure 6G (hereinafter referred to as I core) and a semiconductor layer 64 on the side top surface of the fin structure 60. The semiconductor layer 64 has a band gap greater than that of the structure of the tomb, for example, greater than about ο.1 eV. Furthermore, the fin structure 60 and the material of the semiconductor layer 64 have been disclosed in the co-pending application of the present application. U.S. Patent Application Serial No. 61/182,550, filed on May 29, 2009, entitled Ternary 〇r Quat_ry has just started (4) 攸transistor". The figure shows a similar structure as shown in Fig. 15, in which the gate dielectric layer is not formed. Again, in pictures 15 to 17, although the source The pole/drain regions 42 are not shown in the cross-sectional schematic view and may be formed of substantially the same structure as described in Figure 14. Embodiments of the present invention have the technical advantages of multiple advantages. The source/drain region 42 can be used to reduce the source/drain resistance and improve the drive current of the final transistor. The buffer layer 44 has the channel and source between the transistors. The effect of the lattice constant conversion between the drain regions, thus resulting in the effect of reducing the defect density and reducing the junction leakage current. The present invention has been disclosed above in various embodiments, but is not intended to limit the scope of the present invention. Any technical field Those skilled in the art, while departing from the spirit and scope of the present invention, may be able to do more of the 0503-A34280TWF/5amngw〇\2 201117342 movement and retouching. Therefore, the scope of protection of the present invention is attached to the scope of the patent application. The definition is final.

0503-A34280TWF/jamngwo 13 201117342 [Simplified Schematic] FIG. 1 is a schematic view showing a conventional transistor including π; [a group III-V compound semiconductor material composed of a group element and a group V element; 4A, 4B, 5, 6, 7A, 7B, 8A, 8B, 9 to 11 are schematic cross-sectional views showing stages of each process in the process of fabricating a transistor according to an embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS Embodiments of the invention are schematic views of various process stages in the fabrication of a fin field effect transistor (FinFET); FIGS. U-17 show cross-sectional views of a fin field effect transistor (FinFET) in accordance with an embodiment of the present invention. [Main component symbol description] 1~矽 substrate; 2~buffer layer; 3~gradient buffer layer; 4~bottom barrier layer; 5~channel; 6~top barrier layer; 7~etch stop layer; 8~contact layer ; 9 ~ source / drain; 1 〇 ~ gate structure; 20 ~ substrate; 22 ~ concave; 24 ~ bottom barrier layer; 0503-A34280TWF / jamngwo 14 201117342 2 6 ~ channel layer; 28 ~ top barrier Layer; 30~ shallow trench isolation (STI) region; 32~ gate dielectric layer; 3 4~ gate electrode; 36~ gate spacer; 38~ recessed; 4 2~source/> Region, _ 44 ~ buffer layer; 46 to IV semiconductor region; 50 ~ lithium region; 52 ~ transistor; 5 4 ~ channel layer; 60 ~, if structure, 64 ~ semiconductor layer.

0503-A34280TWF/jamngwo 15

Claims (1)

201117342 VII. Patent application scope: L An integrated circuit structure, comprising: a substrate; the channel is located above the substrate, wherein the channel comprises a first III-V compound composed of a group III private steroid A semiconductor material is disposed on the channel; and a source/drain region is adjacent to the channel, wherein the source/no-polar region includes an IV private region selected from a group substantially comprising the combination. 2. The integrated circuit structure described in the first item of Shen Qing Patent Model 11, the bottom surface of the source/secret region in JL is lower than the recording surface of the channel. 8. The integrated circuit structure of claim 3, further comprising: a gate spacer located on a sidewall of the gate structure, and wherein the outer (four) of the gate spacer is directly aligned with the source Extremely polar region; #1 辟. 4. If you apply for a patent scope! The integrated f-channel structure, wherein the iv-group region is composed of a group IV semiconductor material doped with an impurity, wherein the source/drain region further comprises a buffer layer located in the channel and the iv region Between and adjacent to the channel and the group IV region, and the buffer layer includes - the second m_v compound semiconductor material has a lattice constant between the lattice constant of the channel and the crystal region of the 1¥ family region A number between. Japanese Renewal 5· As set forth in the patent circuit structure described in item i of the patent scope, the pole structure of the pot includes: an open electrode, and a _^〇3~A34280TWF/jamngwo \β 201117342 of the _ pole electrode Located above the channel. 6. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode 'and wherein the gate electrode ' includes a portion directly above the channel, and an additional portion is located The opposite side of the channel. 7. The integrated circuit structure of claim 1, wherein the gate structure comprises a gate electrode and a semiconductor contact.曰 8. An integrated circuit structure comprising: a semiconductor substrate; a channel on the semiconductor substrate, wherein the channel comprises a first m_v group compound conductor material composed of a lanthanum element and a group V element; a gate structure Provided on the channel; a gate spacer is located on a sidewall of the gate structure; a recess adjacent to the channel, the recess having a bottom lower than a bottom of the channel; and a source/drain region located In the recess, wherein the source/drain region comprises a group IV region selected from a group substantially comprising lanthanum, cerium, and combinations thereof, and wherein the source/drain region is doped with a η- Type dopant or a p-type dopant. 9. The circuit structure of claim 4, wherein the buffer layer comprises a second m_v compound semiconductor material in the recess, wherein the buffer layer comprises a vertical portion located in the channel disk. Between the group IV regions, and wherein the buffer layer comprises - the second mv group 0503-A34280TWF/jamngwo 17 201117342 body material has a - crystal 袼 constant between the channel - the first 曰曰 grid number and the 1¥ family Between a second lattice constant of the region. The product as described in claim 9: the buffer layer has a gradient composition, which is closer to the channel: the lattice constant of the second knife is closer to the a first-lattice constant, and a lattice constant of the second portion of the plurality of regions is closer to the second lattice · η. An integrated circuit structure includes: a substrate; wherein the fin structure includes a first a III-V compound fin structure is a semiconductor material composed of a lanthanum element and a group V element on the substrate; a gate structure is partially disposed directly on the fin structure, and an additional portion is disposed on the fin structure Another structure And the source/drain region is adjacent to the fin structure, wherein the source/no-polar region comprises a -IV region selected from the group substantially comprising the bite and the combination thereof. The dragon circuit structure described in the above paragraph (4), wherein the fin structure comprises: - a central, fin structure formed of the first first - ΠΙ Μ compound semiconductor material; and - a semiconductor layer including - a - portion directly located at the center The second part of the rotary structure is located on the opposite side wall of the middle wire structure, wherein the energy gap of the semiconductor layer is larger than the energy gap of the central Korean structure. 〇503-A34280TWF/jamngwo 18