CN220776394U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Download PDF

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Publication number
CN220776394U
CN220776394U CN202321763924.8U CN202321763924U CN220776394U CN 220776394 U CN220776394 U CN 220776394U CN 202321763924 U CN202321763924 U CN 202321763924U CN 220776394 U CN220776394 U CN 220776394U
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semiconductor device
pmos
transistor
carrier substrate
nmos
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O·韦伯
K·J·多里
P·库玛
S·J·阿梅德
C·勒科克
P·乌拉尔
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STMicroelectronics Crolles 2 SAS
STMicroelectronics France SAS
STMicroelectronics International NV
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STMICROELECTRONICS INTERNATIONAL NV
STMicroelectronics SA
STMicroelectronics Crolles 2 SAS
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Priority claimed from US18/347,435 external-priority patent/US20240015945A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material

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Abstract

The present disclosure relates to a semiconductor device. A semiconductor device according to the present disclosure includes: a carrier substrate; a buried dielectric region overlying the carrier substrate; a semiconductor film separated from the carrier substrate by a buried dielectric region; and an NMOS transistor and a PMOS transistor disposed at a surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, the NMOS transistor and the PMOS transistor each including a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. Utilizing embodiments of the present disclosure advantageously allows for independent application of reverse bias on NMOS and PMOS transistors.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
Technical Field
Implementations and embodiments relate to silicon-on-insulator type semiconductor devices, such as implementing static RAM circuitry.
Background
Semiconductor devices of the silicon-on-insulator type, which are typically fabricated inside integrated circuits, typically include a semiconductor film separated from a carrier substrate by a buried dielectric region. For example, in a technique called FDSOI (meaning fully depleted silicon on insulator Fully Depleted Silicon On Insulator), the semiconductor film advantageously has a thickness that is fine enough to fully deplete a few charges.
Conventionally, a static RAM (SRAM, which is commonly used for a static random access memory) includes a memory cell provided with two PMOS transistors and two NMOS transistors (commonly known by those skilled in the art as "p-type/n-type metal oxide semiconductors") connected between a power supply terminal and a ground terminal to form two top-to-tail (top-to-tail) inverters, and typically two access transistors, commonly NMOS transistors, coupled between a bit line and a data node (i.e., an input-output node of the inverter) and controlled by a signal transmitted on a word line.
Writing and reading of a data fragment in an SRAM cell is performed via the access transistor and the bit line by applying at the time of writing or measuring the voltage level on the data node at the time of reading. The retention of the data segment in the memory cell is obtained by the steady state of the signal generated on the data node of the component that is topped up to the tail inverter.
In the "write-read" mode, the supply voltage is generated at a nominal level, i.e. the normal operating level of the transistor, for example between 0.8 volts and 1.2 volts for a semiconductor device of the silicon-on-insulator type, in order to have a well-defined and discernable steady state in the memory cell.
In the "hold" mode of the SRAM cell, it is advantageous to reduce the power consumption of the device as much as possible. The supply voltage can be minimized but still remain greater than the threshold voltage of the transistors of the cell so as not to lose the steady state of the SRAM cell and the data segments retained thereby. It is therefore desirable to propose SRAM memory cell technology with minimal possible current leakage. FDSOI technology (ULL commonly referred to as "ultra low leakage") with the highest performance in terms of current leakage has the result of approximately 1 picoamp (or 1000 nanoamps) in hold mode.
Disclosure of Invention
It is an object of the present disclosure to provide a semiconductor device to at least partially solve the above-mentioned problems occurring in the prior art.
An aspect of the present disclosure provides a semiconductor device including: a carrier substrate; a buried dielectric region overlying the carrier substrate; a semiconductor film separated from the carrier substrate by the buried dielectric region; and an NMOS transistor and a PMOS transistor disposed at a surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, the NMOS transistor and the PMOS transistor each including a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film.
According to one or more embodiments, wherein the gate dielectric layer of the NMOS transistor and the PMOS transistor has a thickness between 3.5 nanometers and 6 nanometers between the active region and the gate conductive region.
In accordance with one or more embodiments, the semiconductor device further comprises a plurality of further PMOS transistors, wherein the active regions of a plurality of the PMOS transistors extend along a first direction.
According to one or more embodiments, wherein the further PMOS transistor is coupled to a further NMOS transistor to form a further SRAM cell, wherein the active region of the further PMOS transistor and the active region of the NMOS transistor extend in the first direction so as to incorporate other SRAM cells.
In accordance with one or more embodiments, the active regions of the plurality of PMOS transistors extend along the first direction so as not to relax compressive stress in the first direction.
In accordance with one or more embodiments, wherein the NMOS transistor and the PMOS transistor are each located in a doped well of the carrier substrate, the device further comprises a bias circuit coupled to the doped well of the carrier substrate.
In accordance with one or more embodiments, the bias circuit is configured to generate voltages in the respective doped wells of the carrier substrate suitable for reverse bias of the PMOS and NMOS transistors.
In accordance with one or more embodiments, wherein the NMOS transistor is located in a p-type doped well in the carrier substrate and the PMOS transistor is located in an n-type doped well in the carrier substrate.
In accordance with one or more embodiments, the bias circuit is configured to generate a reverse bias voltage in the p-doped well of between 0 volts and-2 volts.
In accordance with one or more embodiments, the bias circuit is configured to generate a reverse bias voltage in the n-doped well of between 0 volts and +2 volts.
In accordance with one or more embodiments, the bias circuit is configured to generate voltages suitable for reverse bias of the PMOS and NMOS transistors in a mode for holding a data segment of the memory cell, but not in a read-write mode of the memory cell.
In accordance with one or more embodiments, the bias circuit is configured to generate a supply voltage for the memory cells, the supply voltage having a nominal level in a read-write mode and a voltage of 50% to 85% of the nominal level in a mode for holding a data segment.
Utilizing embodiments of the present disclosure advantageously allows for independent application of reverse bias on NMOS and PMOS transistors.
Drawings
Other advantages and features of the utility model will appear upon examination of the detailed description of the embodiments and examples, which is in no way limiting, and of the accompanying drawings, in which:
fig. 1 schematically shows a semiconductor device DSM of the silicon-on-insulator type;
FIG. 2 shows a circuit diagram of an SRAM memory cell;
FIG. 3 shows an example of a layout in a top view of a circuit of a memory cell as described above with respect to FIGS. 1 and 2;
FIG. 4 shows the result of the intensity of current leakage for a memory cell; and
fig. 5 shows a simplified example of a method for manufacturing a semiconductor device.
Detailed Description
The embodiments are first described in the text and examples are subsequently described with respect to the drawings.
According to one aspect, in this regard, a semiconductor device of the silicon-on-insulator type is proposed, comprising a semiconductor film separated from a carrier substrate by a buried dielectric region. The device includes a static RAM circuit having at least one cell memory including NMOS transistors and PMOS transistors, each transistor including a gate dielectric layer having a thickness greater than 3 nanometers and an active region in a respective semiconductor film. The active region of the PMOS transistor is made of a silicon germanium alloy.
The gate dielectric layer of the transistor is greater than 3 nanometers thick relative to a typical SRAM memory architecture using FDSOI technology. In practice, the gate dielectric layer is typically 1nm to 1.5nm thick. Thus, memory cells defined in accordance with this aspect have minimal gate current leakage. However, the memory cell according to this aspect may have a volume greater than that in conventional architectures (thickness from 1nm to 1.5 nm), and furthermore, the threshold voltages of NMOS and PMOS transistors are greater than those in conventional architectures (thickness from 1nm to 1.5 nm). The active region of a PMOS transistor made of a silicon germanium alloy, which has a compressive stress particularly in the channel (source-drain) direction of the transistor, allows lowering the threshold voltage of the PMOS transistor and thus has proper performance, particularly in terms of stability in read-write mode, without increasing the supply voltage. The increase in threshold voltage of the NMOS transistor advantageously allows reducing current leakage of the conductive region of the NMOS transistor to ground.
The term "active region" denotes a designated region of the semiconductor film that is not covered by a lateral isolation region, such as a shallow isolation trench (typically shallow trench isolation), in a manner that is usual and well known to those skilled in the art, such that an interface between a gate region and a channel region and an interface between source and drain regions of a transistor is formed in the active region.
According to one embodiment, the gate dielectric layers of the NMOS transistor and the PMOS transistor have a thickness between 3.5 nanometers and 6 nanometers between the active region and the gate conductive region.
For example, the gate dielectric layers of NMOS and PMOS transistors include portions made of silicon oxide, such as silicon oxide nitride (or SiO x N y Typically Si 2 O 2 N) having a thickness of between 1nm and 3.5nm and optionally comprising a portion made of a "high dielectric constant" (typically "high-k") dielectric, for example hafnium oxide, having a thickness of substantially 2.5 nm, located above a portion made of silicon oxide, in particular in a technique called "high-k/metal gate", that is to say, the technique comprises a "high dielectric constant" dielectricElectrical and a portion made of metal in the gate conductive region.
The total thickness of the gate dielectric layer between 3.5nm and 6nm may correspond, for example, to the gate dielectric of a "medium voltage" transistor intended to operate at voltages up to 1.8 volts, as opposed to the conventional architecture (from 1nm to 1.5 nm) corresponding to the gate dielectric of a "low voltage" transistor intended to operate at voltages below 1.2 volts.
Circuits other than static RAM circuits belonging to semiconductor devices may incorporate "medium voltage" transistors, that is to say transistors having a gate dielectric layer with a thickness between 3.5nm and 6nm and for operation at voltages between 1.2 volts and 1.8 volts, and optionally "low voltage" transistors, that is to say transistors having a gate dielectric layer with a thickness between 1nm and 1.5nm and for operation at voltages between 0.5 volts and 1.2 volts.
According to one implementation, the active region extends in a first direction in the memory circuit so as to incorporate other cell memories and so as not to relax compressive stress in the first direction of the silicon germanium alloy.
This corresponds to a "continuous active region" architecture for PMOS transistors that allows exploiting the compressive stress in the channel length of the PMOS transistor, but which by construction causes the presence of an additional transistor, called "gate connect", which is advantageously connected to be always inactive (always deactivated).
Furthermore, the first direction corresponds to the length of the channel of the transistor, i.e. the direction between the source and the drain of the transistor.
According to one implementation, the NMOS transistor and the PMOS transistor are located in doped wells of the carrier substrate, respectively, the device comprising a bias circuit configured to generate voltages suitable for reverse biasing of the PMOS and NMOS transistors in respective semiconductor wells of the carrier substrate.
The reverse bias voltage generates a field effect in the active region, which is caused by the bias voltage of the carrier substrate under the buried dielectric region. Reverse bias allows the operation of the transistor to be "slowed down" by increasing the threshold voltage of the transistor and reduces current leakage in the channel of the transistor.
According to one embodiment, the NMOS transistor is located in a p-type doped well in the carrier substrate, the PMOS transistor is located in an n-type doped well in the carrier substrate, and the bias circuit is configured to generate a reverse bias voltage between 0 volts and-2 volts in the p-type doped well, and a reverse bias voltage between 0 volts and +2 volts in the n-type doped well.
According to one implementation, the bias circuit is configured to generate the voltages suitable for reverse bias of the PMOS and NMOS transistors in a mode for holding a data segment of the cell memory, instead of in a read-write mode of the cell memory, the bias circuit is configured to generate a supply voltage for the cell memory having a nominal level in the read-write mode, and the supply voltage has 50% to 85% of the nominal level in the mode for holding the data segment.
According to a further aspect, a method for manufacturing a semiconductor device of the silicon-on-insulator type is proposed, the semiconductor device comprising a semiconductor film separated from a carrier substrate by said buried dielectric region. At least one cell memory of a static RAM circuit including NMOS transistors and PMOS transistors is manufactured. The method includes forming an active region in a corresponding semiconductor film and forming a gate dielectric layer having a thickness greater than 3 nanometers. The active region of the PMOS transistor is made of a silicon germanium alloy.
According to one embodiment, the gate dielectric layers of the NMOS transistor and the PMOS transistor have a thickness between 3.5 nanometers and 6 nanometers between the active region and the gate conductive region.
According to one embodiment, the active region is made by extending in a first direction in the memory circuit so as to incorporate other cell memories and not relax compressive stress in the first direction of the silicon germanium alloy.
According to one embodiment, the fabrication of the NMOS transistor and the PMOS transistor comprises forming separately doped semiconductor wells in the carrier substrate, the PMOS and NMOS transistors being located in the wells having respective types of doping, the method further comprising fabricating bias circuitry capable of generating voltages in the respective semiconductor wells of the carrier substrate suitable for reverse biasing of the PMOS and NMOS transistors.
According to one embodiment, the well in which the NMOS transistor is located has p-type doping, the well in which the PMOS transistor is located has n-type doping, and the bias circuit is fabricated to generate a reverse bias voltage in the p-type doped well of between 0 volts and-2 volts, and a reverse bias voltage in the n-type doped well of between 0 volts and +2 volts.
According to one embodiment, the bias circuit is manufactured to generate said voltages suitable for reverse bias of the PMOS and NMOS transistors in a mode for holding a data segment of said cell memory, instead of in a read-write mode of said cell memory, the bias circuit is manufactured to generate a supply voltage for said cell memory having a nominal level in the read-write mode, and the supply voltage has 50% to 85% of the nominal level in the mode for holding a data segment.
Reference is now made to the drawings.
Fig. 1 schematically shows a semiconductor device DSM of the silicon-on-insulator type comprising a transistor NM of the NMOS type and a transistor PM of the PMOS type, which will be denoted below by the terms "NMOS transistor" and "PMOS transistor".
In the silicon-on-insulator technology, the NMOS transistor and the PMOS transistor are made of a substrate structure including semiconductor films ACTn, ACTp, which are separated from a carrier substrate SUB by buried dielectric regions BOX.
The NMOS and PMOS transistors are particularly suited for cell memory CLL integrated with ultra low leakage "SRAM" static RAM circuits.
In this regard, the NMOS transistor and the PMOS transistor each include, in particular, a gate dielectric layer or "region" EG having a thickness tEG greater than 3 nanometers, and also in particular, the PMOS transistor includes an active region ACTp in a corresponding semiconductor film made of a silicon germanium alloy. In practice, the entire semiconductor film ACTp for the PMOS transistor is made of a silicon germanium alloy.
For example, the gate dielectric layer EG of the NMOS transistor and the PMOS transistor has a thickness tEG, taken in the vertical direction Z, between the active regions ACTn, ACTp and the gate conductive region RG (see below) of between 3.5nm and 6nm, or even 7 nm.
Advantageously, the gate dielectric layer EG has an equivalent electrical thickness of substantially 4 nanometers or less. The equivalent electrical thickness corresponds to the thickness t of a dielectric (e.g. SiO2 silicon dioxide) having a reference dielectric constant epsilon, so as to be generated at the same capacitance value C according to the formula c=epsilon (S/t) at equal surfaces S.
Thus, the reduction of the electrical thickness allows to increase the capacitance value of the dielectric layer, which is advantageous in terms of performance, without reducing the physical thickness of the dielectric layer, which is advantageous in terms of gate current leakage.
For example, in this regard, the gate dielectric layer EG may comprise silicon oxynitride (or SiO) of "SiON" having a thickness between 1nm and 4.5nm x N y Typically Si 2 O 2 N), and a portion made of a "high dielectric constant" (typically "high k") dielectric (e.g., hafnium oxide) having a thickness of substantially 2.5 nanometers over the portion made of silicon oxide. The physical thickness of these materials, for example, approximately 6 nanometers (3.5+2.5), corresponds to an equivalent electrical thickness of approximately 4 nanometers.
In addition, NMOS and PMOS transistors typically include a gate conductive region RG on a gate dielectric layer EG, and include a layer made of, for example, metal and a volume of polysilicon, and source S and drain D regions implanted into the respective active regions ACTn, ACTp.
The active regions ACTn, ACTp are located in the semiconductor film of the silicon-on-insulator substrate and are defined by lateral isolation structures STI (typically shallow isolation trenches). The active region ACTn of the NMOS transistor is made of, for example, intrinsic silicon.
Finally, the NMOS transistor is positioned facing the p-doped well PW implanted in the carrier substrate SUB, and the PMOS transistor is positioned facing the n-doped well NW implanted in the carrier substrate SUB, that is to say in a configuration corresponding to the "normal" structure of the well (as opposed to the "inverted" structure of the well in which the NMOS transistor faces the n-well of the carrier substrate SUB and the PMOS transistor faces the p-well of the carrier substrate SUB).
The "conventional" structure of the wells advantageously allows for the implementation of reverse bias of the NMOS and PMOS transistors, since the junction PN between the wells is blocked under such bias conditions (negative bias in the p-doped well and positive bias in the n-doped well). In this respect, the semiconductor wells PW, NW comprise respective contacts p+, n+, typically in the opening of the buried dielectric region BOX formed between the two shallow isolation trenches STI, and return, for example, from the circuit comprising the transistors NM, PM.
The reverse bias condition BBn, BBp corresponds to the field effect in the active regions ACTn, ACTp generated by the bias of the carrier substrate SUB (wells PW, NW) through the buried dielectric region BOX. Reverse bias includes a negative bias for NMOS transistors and a positive bias for PMOS transistors, which allows for "slowing down" the operation of the transistors and reducing current leakage to the carrier substrate SUB.
The semiconductor device DSM comprises a bias circuit ALM, for example inside the power supply circuit of the device, which is configured to generate voltages BBn, BBp suitable for reverse bias of the PMOS and NMOS transistors in the respective semiconductor wells PW, NW of the carrier substrate SUB.
For example, the reverse bias voltage BBn applied to the NMOS transistor and in the p-type doped well PW is between 0 volts and-2 volts, and the reverse bias voltage BBp applied to the PMOS transistor and in the n-type doped well NW is between 0 volts and +2 volts.
Advantageously, the bias circuit ALM is configured to generate said voltages BBn, BBp of reverse bias of PMOS and NMOS transistors in a mode for holding a data fragment of said cell memory CLL, and to not generate a reverse bias in a read-write mode of said cell memory CLL.
Further, the bias circuit ALM may be configured to generate a power supply voltage VDD for the cell memory CLL, which has a nominal level in the read-write mode and 50% to 85% of the nominal level in the mode of holding the data segment.
Reference is made in this respect to fig. 2.
Fig. 2 shows a circuit diagram of a memory cell CLL of an SRAM static RAM comprising NMOS transistors and PMOS transistors as described in fig. 1.
The memory cell comprises two "pull-up" PMOS transistors PU1, PU2 and two "pull-down" NMOS transistors PD1, PD2 connected between the power supply terminal VDD and the ground terminal GND, so as to form two top-to-tail inverters. The output node N1 (or "first data segment node N1") of the first inverter PU1, PD1 is coupled to the input of the second inverter PU2, PD2, and the output node N2 (or "second data segment node N2") of the second inverter PU2, PD2 is coupled to the input of the first inverter PU1, PD 1.
In addition, the cell CLL conventionally includes two access NMOS transistors PG1, PG2, allowing selection of cells for reading and writing. The first access transistor PG1 is coupled between the bit line BL1 and the first data node N1 and is controlled by a signal transmitted on the word line WL. The second access transistor PG2 is coupled between the further bit line BL2 and the second data node N2 and is controlled by a signal transmitted on the word line WL.
The writing and reading of the data fragment in the cell CLL is performed via the access transistors PG1, PG2 by measuring the voltage level of at least one of the data fragment nodes N1, N2 via the respective bit lines BL1, BL2 at the time of reading and by applying the voltage level on at least one of the data fragment nodes N1, N2 via the respective bit lines BL1, BL2 at the time of writing.
The retention of the data segments in the memory cell is obtained by the steady state of the signals generated on the data nodes N1, N2 of the components of the two top-to-tail inverters PU1-PD1, PU2-PD 2.
In read-write mode, the supply voltage VDD is generated by the bias circuit ALM at a nominal level, i.e. the normal operating level of the transistors PU1, PD1, PU2, PD2, e.g. between 0.8 volts and 1.2 volts, preferably 0.8 volts.
In the hold mode of the SRAM cell, the supply voltage VDD is generated by the bias circuit ALM at an economical level, e.g. 50% to 85% of the nominal level, that is to say between 0.4 volts and 1.0 volts, preferably substantially 0.6 volts.
Fig. 3 shows an example of a layout in a top view of the circuit of the memory cell CLL as described above with respect to fig. 1 and 2.
The same elements have the same reference numerals as in fig. 1 and 2, and will not be described in detail here.
It is particularly noted that the active region ACTn (Si), ACTp (SiGe), extends in the memory circuitry along the first direction L on either side of the outline of the memory cell CLL, thereby incorporating adjacent cell memories (extending to the left and right of the cell CLL in the direction of fig. 3).
This corresponds to a "continuous active region" structure of active regions made of silicon germanium alloy ACTp (SiGe) of PMOS transistors.
This allows not to relax the compressive stress in the first direction L of the silicon germanium alloy ACTP (SiGe) and thus to exploit the improvement of the performance of the PMOS transistor, in particular the reduction of the threshold voltage of the PMOS transistor and the low variability of the threshold voltage of the PMOS transistor.
However, this results in the generation of "parasitic" transistors GT1, GT2 in each active region ACTp of the functional pull-up PMOS transistors PU1, PU2 for the cell CLL. The two parasitic PMOS transistors GT1, GT2 are deactivated by connecting their gates and their sources to the supply voltage terminal VDD and are in this respect commonly referred to as "gate connected transistors". In fig. 2, the parasitic PMOS transistors GT1, GT2 are shown in dashed lines as they are present but they are in a deactivated state.
The gate-connected transistors GT1, GT2 may introduce additional leakage current to the leakage current of the memory cell CLL in an off-mode or a hold-mode (typically an "off-state mode"), but with respect to the consumption of the memory cell in a read/write mode is negligible. That is, even in the off mode or the hold mode, the leakage of the "gate connected" transistor is low due to its gate dielectric layer thickness being greater than 3 nanometers, and a large gate length (in the first direction L), e.g., greater than 100 nm.
The first direction L corresponds to the length of the transistor, i.e. the source-drain direction of the transistor. The width W of the transistor is defined by the extension of the active region in a second direction W perpendicular to the first direction L and the vertical direction Z.
For example, the NMOS and PMOS transistors of the cell CLL may have a channel length between 100nm and 200nm in the first direction L and a channel width between 100nm and 200nm in the second direction W. The length (L) and width (W) of the transistor of the cell CLL are relatively large, but allow ensuring a good electrostatic control of carriers in the channel (and thus less leakage between the source and drain regions), respectively, with respect to the thickness of the gate dielectric layer EG, and a conduction current sufficient for the operation of the SRAM memory cell.
That is, the current leakage in the memory cell CLL as described with respect to fig. 1-3 is extremely low, e.g., substantially 50 factors (times) less than the current leakage of an "ultra low leakage" memory cell.
Reference is made in this respect to fig. 4.
Fig. 4 shows the results of the strength of current leakage ISB in picoamps (10-12A) of the memory cell CLL as described above with respect to fig. 1-3, in volts, and for various reverse biases BBn/BBp, depending on the level of the supply voltage VDD, in the hold mode.
It should be noted that at a supply voltage VDD of 0.6 volts in the retention mode, the magnitude of the current leakage ISB in the memory cell CLL is substantially 24 nanoamps (24 x 10-15A) at a reverse bias voltage of BBn =2 volts and BBp = +2 volts (BBn/BBp: 2/2).
For comparison, cells of conventional ultra low leakage SRAM memories using FDSOI technology have a leakage of about 1 to 1.5 picoamps in hold mode. In other words, the memory cell CLL as described above with respect to fig. 1 to 3 has a current leakage that is less than the conventional art by a factor of 50.
It is also noted that other supply voltage VDD and/or reverse bias BBn/BBp conditions give satisfactory results. For example: at a supply voltage VDD of 0.8 volts and reverse bias of BBn/BBp:2/2, the magnitude of the current leakage ISB in the memory cell CLL is less than 100 nanoamperes; at a supply voltage VDD of 0.6 volts and reverse bias of BBn/BBp: with 1/1, the strength of the current leakage ISB in the memory cell CLL is less than 1 picoampere.
Fig. 5 shows a simplified example of a method for manufacturing the semiconductor device DSM as described above with respect to fig. 1 to 4, in particular the manufacture of the NMOS and PMOS transistors of the memory cell CLL.
In step 101, a silicon-on-insulator type substrate including a semiconductor film made of intrinsic silicon (ACT) is prepared, the semiconductor film being separated from a carrier substrate SUB by a buried dielectric region BOX.
In step 103, the material (initial intrinsic silicon) in the active region ACTp of the future PMOS transistor is modified, for example via a technique commonly referred to as "condensation". The condensation technique first involves the selective growth of silicon germanium by epitaxy on a semiconductor film made of intrinsic silicon that receives the region of the PMOS transistor. Then, germanium is deeply (downwardly) diffused in the semiconductor film. Diffusion is performed by oxidizing the epitaxial region, and then the oxide thus generated is removed, and an active region ACTp made of a silicon germanium alloy is locally formed. The active region ACTn of the future NMOS transistor remains in the intrinsic silicon.
In step 103, shallow isolation trenches STI are also formed to define contacts in the future wells of the carrier substrate SUB and the active regions ACTn, ACTp of the future NMOS and PMOS transistors.
In step 105, wells NW, PW are formed in the carrier substrate SUB by implanting dopants of the respective type.
In step 107, the gate dielectric layer EG of the future NMOS and PMOS transistors is formed, for example, by depositing a dielectric layer EG or a superposition of dielectric layers with a total thickness of more than 3nm (e.g. between 3.5nm and 4.5 nm) over the entire front side of the substrate.
In step 109, the gate conductive regions RG of the NMOS and PMOS transistors are formed, for example, by depositing a conductive structure RG over the entire dielectric layer EG, which may include a metal layer and a polysilicon volume on top.
The various structures of the gates EG, RG of the NMOS and PMOS transistors are then defined by etching, typically by photolithography, to remove the gate conductive region RG and the gate dielectric layer EG in the portions located outside the mask pattern. In fig. 3, the region filled by the most tightly rising diagonal hatching ("RG" in fig. 1) represents the etching result of the gate structures EG, RG and corresponds substantially to the pattern of the mask.
After defining the structure of the gates EG, RG of the NMOS and PMOS transistors, the source and drain regions S/D are implanted in a self-aligned manner into the active regions ACTn, ACTp on the gate structures EG, RG, that is to say into the portions of the active regions ACTn, ACTp not masked by the gate structures EG, RG.
In one aspect, the NMOS and PMOS transistors of the memory cell are electrically connected via vertical metal vias and metal tracks, for example as shown in fig. 3, wherein squares filled with crosses in both diagonals correspond to the locations of the vias, and wherein the regions filled by the least tight rising diagonal hatching (VDD, N1, N2, WL, BL1, BL 2) correspond to the metal tracks.
Thus, in step 111, the memory cell CLL is active and may be powered, for example, with a supply voltage VDD of between 0.8 volts and 1.2 volts (0.8 v+.vdd+.1.2V) without reverse bias (BBn = BBp =0v) in read and write modes of operation, and with a supply voltage VDD of substantially 0.6 volts (vdd=0.6V) in retention mode of operation, and with a reverse bias BBn of substantially 2 volts in the p-well PW, BBp, and with a reverse bias BBn of substantially +2 volts in the n-well NW (BBn =2v; bbp= +2v).
Furthermore, the method for producing the memory cell advantageously uses production steps which can also be planned in conventional production methods and can therefore be carried out in a completely co-integrated manner and without additional costs. In practice, the circuitry of the semiconductor device DSM, in addition to the static RAM circuitry, may comprise "medium voltage" transistors, that is to say transistors having a gate dielectric layer with a thickness of between 3.5nm and 4.5nm, and for voltage operation between 1.2 volts and 1.8 volts, for which the manufacturing steps essentially correspond to the manufacturing steps 101-111 of NMOS and PMOS transistors. Furthermore, other circuits of the semiconductor device DSM may comprise "low voltage" transistors, that is to say transistors with gate dielectric layers having a thickness between 1nm and 1.5nm, and for operation at voltages between 0.5 volts and 1.2 volts.
An aspect of the present disclosure provides a method of operating a static random access memory formed of an NMOS transistor and a PMOS transistor disposed on a surface of a semiconductor film separated from a carrier substrate by a buried dielectric region, wherein the NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film, and wherein the active region of the PMOS transistor includes a silicon germanium alloy, the method comprising: operating the memory in a read-write mode, wherein the NMOS transistor and the PMOS transistor are reverse biased to a nominal voltage in the read-write mode; and operating the memory in a hold mode, wherein the NMOS transistor and the PMOS transistor are reverse biased in the hold mode to a voltage that is 50% to 85% of the nominal voltage.
According to one or more embodiments, the method further comprises applying a reverse bias voltage between 0 volts and-2 volts to a p-type doped well of the NMOS transistor.
According to one or more embodiments, the method further comprises applying a reverse bias voltage between 0 volts and +2 volts to an n-type doped well of the PMOS transistor.
According to one or more embodiments, the semiconductor film is separated from the carrier substrate by a buried dielectric region, the method comprising: forming an NMOS transistor and a PMOS transistor on a surface of the semiconductor film; and coupling the NMOS transistor and the PMOS transistor together to form a plurality of static random access memory SRAM cells; wherein the NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers; wherein the NMOS transistor includes an active region of silicon in the semiconductor film; and wherein the PMOS transistor includes an active region of a silicon germanium alloy in the semiconductor film.
In accordance with one or more embodiments, wherein forming the NMOS transistor and the PMOS transistor comprises: modifying a silicon film in a region of the active region of the PMOS transistor to form the silicon germanium alloy; forming a shallow isolation trench to define the active region; forming an n-type doped well of the PMOS transistor in the carrier substrate; forming a p-type doped well of the NMOS transistor in the carrier substrate; forming the gate dielectric layer; forming a gate conductive layer on the gate dielectric layer; patterning the gate conductive layer to form a gate conductive region; forming source and drain regions for the NMOS transistor and the PMOS transistor; and interconnecting the NMOS transistor and the PMOS transistor to form the SRAM cell.
According to one or more embodiments, wherein modifying the silicon film comprises implementing a condensation technique.
In accordance with one or more embodiments, wherein the gate dielectric layer is formed to a thickness between 3.5nm and 6 nm.
In accordance with one or more embodiments, the active region is formed to extend along a first direction, thereby incorporating a plurality of the SRAM cells.
In accordance with one or more embodiments, wherein the active region is formed to extend along the first direction so as not to relax compressive stress in the first direction of the silicon germanium alloy.
In accordance with one or more embodiments, the method further includes fabricating a bias circuit electrically coupled to the n-type doped well of the PMOS transistor and the p-type doped well of the NMOS transistor.
Embodiments propose SRAM memory technology with even lower power consumption, for example in data retention mode.
In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. The NMOS transistor and the PMOS transistor are disposed on a surface of the semiconductor film and coupled together to form a Static Random Access Memory (SRAM) cell. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. The active region of the PMOS transistor is formed of a silicon germanium alloy.
Further embodiments provide a method of operating a static random access memory formed of an NMOS transistor and a PMOS transistor disposed on a surface of a semiconductor film separated from a carrier substrate by a buried dielectric region. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film. The active region of the PMOS transistor comprises a silicon germanium alloy. The method includes operating the memory in a read-write mode and operating the memory in a hold mode. The NMOS transistor and the PMOS transistor are reverse biased to a nominal voltage in the read-write mode, and the NMOS transistor and the PMOS transistor are reverse biased to a voltage of 50% to 85% of the nominal voltage in the hold mode.
Further embodiments provide methods of forming semiconductor devices in semiconductor films that are separated from a carrier substrate by buried dielectric regions. The method includes forming an NMOS transistor and a PMOS transistor on a surface of a semiconductor film, and coupling the NMOS transistor and the PMOS transistor together to form a plurality of Static Random Access Memory (SRAM) cells. The NMOS transistor and the PMOS transistor each include a gate dielectric layer having a thickness greater than 3 nanometers. The NMOS transistor includes a silicon active region in the semiconductor film, and the PMOS transistor includes a silicon germanium alloy active region in the semiconductor film.
In summary, the implementation of a static RAM cell of a semiconductor device DSM of the FDSOI type has been described, comprising an NMOS transistor and a PMOS transistor in a configuration with regular wells, allowing to apply a reverse bias on the NMOS and PMOS transistors independently. The thickness of the gate dielectric layer EG greater than 3 nanometers allows for the elimination of gate current leakage. The active region ACTp of the PMOS transistor made of a silicon germanium alloy under compressive stress in the channel direction L allows lowering the threshold voltage of the PMOS transistor and thus ensures sufficient stability in reading and writing. The continuous active region ACTp structure of the PMOS transistor allows avoiding relaxation of the compressive stress of the silicon germanium alloy, which thus avoids variability and increase of the threshold voltage of the PMOS transistor. Furthermore, the method for manufacturing the memory cell may use conventional manufacturing steps and thus be implemented in a fully co-integrated manner without additional dedicated costs.

Claims (12)

1. A semiconductor device, comprising:
a carrier substrate;
a buried dielectric region overlying the carrier substrate;
a semiconductor film separated from the carrier substrate by the buried dielectric region; and
an NMOS transistor and a PMOS transistor disposed at a surface of the semiconductor film and coupled together to form a static random access memory SRAM cell, the NMOS transistor and the PMOS transistor each including a gate dielectric layer having a thickness greater than 3 nanometers and an active region in the semiconductor film.
2. The semiconductor device of claim 1, wherein the gate dielectric layer of the NMOS transistor and the PMOS transistor has a thickness between 3.5 nanometers and 6 nanometers between the active region and a gate conductive region.
3. The semiconductor device of claim 1, further comprising a plurality of additional PMOS transistors, wherein the active regions of a plurality of the PMOS transistors extend in a first direction.
4. The semiconductor device of claim 3, wherein the further PMOS transistor is coupled to a further NMOS transistor to form a further SRAM cell, wherein the active region of the further PMOS transistor and the active region of the NMOS transistor extend in the first direction to incorporate other SRAM cells.
5. The semiconductor device of claim 3, wherein the active regions of the plurality of PMOS transistors extend in the first direction so as not to relax compressive stress in the first direction.
6. The semiconductor device of claim 1, wherein the NMOS transistor and the PMOS transistor are each located in a doped well of the carrier substrate, the device further comprising a bias circuit coupled to the doped well of the carrier substrate.
7. The semiconductor device of claim 6, wherein the bias circuit is configured to generate voltages in the respective doped wells of the carrier substrate suitable for reverse bias of the PMOS and NMOS transistors.
8. The semiconductor device of claim 6, wherein the NMOS transistor is located in a p-type doped well in the carrier substrate and the PMOS transistor is located in an n-type doped well in the carrier substrate.
9. The semiconductor device of claim 8, wherein the bias circuit is configured to generate a reverse bias voltage in the p-type doped well between 0 volts and-2 volts.
10. The semiconductor device of claim 8, wherein the bias circuit is configured to generate a reverse bias voltage in the n-doped well of between 0 volts and +2 volts.
11. The semiconductor device of claim 6, wherein the bias circuit is configured to generate voltages suitable for reverse bias of the PMOS and NMOS transistors in a mode for holding a data segment of the memory cell, but not in a read-write mode of the memory cell.
12. The semiconductor device of claim 6, wherein the bias circuit is configured to generate a supply voltage for the memory cell, the supply voltage having a nominal level in a read-write mode and a voltage of 50% to 85% of the nominal level in a mode for holding a data segment.
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