CN102856357A - Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof - Google Patents
Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof Download PDFInfo
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Abstract
The invention provides a heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on a buried layer N-type trap and a preparation method thereof. According to the invention, hole potential barriers between a bulk and the buried layer N-type trap and between the bulk and a source region are effectively increased, thus the bulk potential variation range of a 1T-DRAM unit is effectively increased, and further the threshold voltage variation range is effectively increased, so that the read signal current increases, that is, the signal margin is increased. At the same time, as the hole potential barriers between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively increased, the drain currents between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively decreased, and the retention time of the 1T-DRAM is increased. In addition, as narrow bandgap SiGe is adopted as a bulk layer and a drain region, impact ionization effect is effectively increased, so as to improve bulk hole production rate and increase the read-write velocity of the 1T-DRAM unit.
Description
Technical field
The present invention relates to a kind of 1T-DRAM structure and preparation method thereof, relate in particular to a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap and preparation method thereof.
Background technology
Along with constantly dwindling of semiconductor device characteristic size, tradition 1T/1C embedded DRAM unit is in order to obtain enough amount of storage capacity (General Requirements 30fF/cell), its electric capacity preparation technology (stack capacitor or deep-trench capacitor) will become increasingly complex, and with the logical device processing compatibility worse and worse.Therefore, compatible good in electric capacity DRAM(Capacitorless DRAM with logical device) will in VLSI, have good development prospect in high-performance embedded DRAM field.1T-DRAM(one transistor dynamic random access memory wherein) only has 4F because of its cell size
2And become present study hotspot without electric capacity DRAM.
1T-DRAM is generally a SOI buoyancy aid (floating body) NMOSFET transistor or with the NMOSFET transistor of buried regions N-type trap, when being charged in its tagma, one writing is finished in the accumulation that is the hole, tagma, at this moment owing to the accumulation of hole, tagma causes substrate bias effect, cause transistorized threshold voltage to reduce.When being discharged in its tagma, the hole that namely accumulates by its tagma of the positive assistant general of body drain PN junction bleeds off to finish writes " 0 ", and at this moment body effect disappears, and threshold voltage recovering is normal.And read operation is the source-drain current when reading this transistor opening, because " 1 " different with the threshold voltage of " 0 " state, both source-drain currents are also different, and what represent to read when larger is " 1 ", and is " 0 " than what hour namely represent to read.
The operating characteristic of 1T-DRAM has a detailed description in following paper:
Ohsawa, T.; Et al. Memory design using a one-transistor gain cell on SOI, Solid-State Circuits, IEEE Journal, Nov 2002, Volume:37 Issue:11, page:1510 – 1522
According to the difference of one writing method of operation, 1T-DRAM can be divided into two classes, accumulates the hole in the tagma by ionization by collision (impact-ionization) when a class adopts transistor to work in the saturation region, and a class adopts the GIDL effect to make accumulation hole, tagma.Adopting the 1T-DRAM of impact ionization is the study hotspot of present 1T-DRAM.
But the conventional NMOSFET transistor 1T-DRAM structure with buried regions N-type trap also need to be done further improvement to improve performance in following several respects at present:
1, the hole potential barrier restriction in hole potential barrier, tagma and the source of body potential receptor area and buried regions N-type trap, because conventional Si semiconductor energy gap is limited, the variation of bulk potential is restricted, the variation of threshold voltage less (generally only having about 0.3V), and this is so that the signal code of reading is less;
2, when this 1T-DRAM work, buried regions N-type trap need to connect positive voltage, so that P type tagma and the formed PN junction of buried regions N-type trap are anti-inclined to one side, but it must have a PN junction pull-down current, thereby cause the hole of tagma accumulation to run off, therefore, need reduce this pull-down current as far as possible.In like manner, also need reduce the leakage current in tagma and source, to improve the retention time (retention time) of 1T-DRAM as far as possible.
3, increase impact ionization, produce speed to increase the hole, tagma, increase the read-write speed of 1T-DRAM unit.
Summary of the invention
Three aspects with the required further improvement of NMOSFET transistor 1T-DRAM structure of buried regions N-type trap for above-described present routine, from energy band engineering, propose a kind of buried regions N-type trap and source region and adopt the semi-conducting material of broad stopband, and the semi-conducting material of low energy gap is adopted in tagma and drain region, namely adopt the method for heterojunction to improve the performance of conventional 1T-DRAM, and propose its preparation method:
Wherein, the germanium silicon (SiGe) narrower than the energy gap of Si is adopted in tagma and drain region, to increase impact ionization, produces speed thereby increase the hole, tagma, increases the read-write speed of 1T-DRAM unit.For body trap, body source PN junction, in order to increase the hole potential barrier, theoretically, if use the energy band engineering material wider than the forbidden band of SiGe just can realize.Simultaneously, in order not affect the threshold voltage of NMOS, the conduction band of this wide-band gap material needs and silicon identical or close, namely only needs valence band lower than SiGe, and carborundum (SiC) just has this characteristic.
First purpose of the present invention provides a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap, comprises bottom silicon, is positioned at the buried regions N-type trap layer of described bottom silicon top and is positioned at the top layer silicon of described buried regions N-type trap layer top; Also include grid and the shallow trench that is positioned at the grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Be respectively source region and drain region in the tagma layer between described grid and the shallow trench.
Wherein, described top layer silicon comprises P type SiGe layer, and described source region material is N
+Type SiC, described drain region material is N
+Type SiGe, described buried regions N-type trap layer material is N-type SiC.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, in described buried regions N-type trap layer and/or the source region, the molar content of carbon is preferably 0.01% ~ 10%.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described buried regions N-type trap layer thickness is preferably 〉=10nm.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described top layer silicon top can also comprise the P type silicon thin layer that is positioned at described grid below, or also comprises the gate oxide between described grid and described P shape silicon thin layer.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, in described P type SiGe layer and the described drain region, the molar content of Ge is preferably 0.1 ~ 100%.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described P type SiGe layer thickness 〉=30nm.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described source region thickness are 1/5 ~ 4/5 of described P type SiGe layer thickness.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described grid both sides also comprise side wall, described source region can extend to the side wall below from described shallow trench, or extends to the side wall outward flange.Described outer referring to centered by the grid central shaft pointed to the direction of shallow trench.
Described drain region can be comprised of shallow doped region and heavily doped region, but also can not comprise shallow doped region.
Similarly, also can have shallow doped region between described source region and the grid, this shallow doped region material also can be N
+Type SiGe.
Second purpose of the present invention provides a kind of method for preparing such as above-mentioned heterojunction 1T-DRAM structure based on buried regions N-type trap, and step comprises:
Photoresist cover gate, shallow trench and described P type SiGe layer form the second opening at the grid opposite side, and the P type SiGe layer between the shallow trench of grid and described grid opposite side is come out, and by the second opening the P type SiGe layer that exposes are carried out N
+The type Implantation forms the drain region; Remove the residue photoresist.
In the said method of the present invention, preferably, described N-type SiC layer thickness 〉=10nm, the molar content of C is 0.01% ~ 10%; Described P type SiGe layer thickness 〉=30nm, the molar content of Ge is 0.1% ~ 100%.
The method that the present invention is above-mentioned also comprises the technique for preparing grid curb wall, and the preparation of described side wall can be to carry out before preparation drain region and source region, perhaps after the preparation source region or carry out before the drain region.
Drain region of the present invention can be successively to be prepared by light dope (and injecting low energy Ge ion) and heavy doping (and injecting high energy Ge ion), and at this moment, side wall should be prepared before heavy doping.
In the said method of the present invention, light dope also can be carried out first in described source region before carrying out etching formation source region groove, and injected low energy Ge ion.
In the step 6, in the described etching P type SiGe layer process, the P type SiGe layer thickness that etches away preferably accounts for 1/5 ~ 4/5 of described P type SiGe layer gross thickness.
The present invention above-mentioned based in heterojunction 1T-DRAM structure of buried regions N-type trap and preparation method thereof, described bottom silicon can be P type silicon.
The present invention adopts SiGe as top layer silicon (comprising the tagma) and drain region, adopt N-type SiC as buried regions N-type trap, adopt N+ type SiC as the source region, effectively increased between tagma and the buried regions N-type trap, the hole potential barrier between tagma and the source region, thereby effectively increase the excursion of the bulk potential of 1T-DRAM unit, and then effectively increase the excursion of its threshold voltage, so that the signal code of reading becomes large, namely increased signal margin (margin).Simultaneously because increased between tagma and the buried regions N-type trap, the hole potential barrier between tagma and the source region, effectively reduced between tagma and the buried regions N-type trap, the leakage current between tagma and the source region, increased the retention time of 1T-DRAM.In addition, because the SiGe that adopts low energy gap effectively increases impact ionization as tagma layer and drain region, produce speed to increase the hole, tagma, increase the read-write speed of 1T-DRAM unit.
Description of drawings
Fig. 1 is the method flow diagram that the embodiment of the invention 1 prepares based on the heterojunction 1T-DRAM structure of buried regions N-type trap, wherein:
Figure 1A is preparation bottom silicon, N-type SiC layer, P type SiGe layer and P type silicon thin layer;
Figure 1B is for forming shallow trench;
Fig. 1 C is for forming grid;
Fig. 1 D is that etching forms the source region groove;
Fig. 1 E is for filling the source region groove;
Fig. 1 F is that light dope forms the shallow doped region in drain region;
Fig. 1 G is the preparation grid curb wall;
Fig. 1 H is to carrying out heavy doping in the drain region;
Fig. 1 I is the heterojunction 1T-DRAM structural representation based on buried regions N-type trap;
Fig. 1 J is the 1T-DRAM cellular construction schematic diagram that forms after the wiring;
Fig. 2 is the method flow diagram that the embodiment of the invention 2 prepares based on the heterojunction 1T-DRAM structure of buried regions N-type trap, wherein:
Fig. 2 A is that light dope is carried out in the grid both sides;
Fig. 2 B is that etching forms the source region groove;
Fig. 2 C is for filling the source region groove;
Fig. 2 D is to carrying out heavy doping in the drain region;
Fig. 2 E is the heterojunction 1T-DRAM structural representation based on buried regions N-type trap;
Fig. 3 is that the embodiment of the invention 3 is based on the heterojunction 1T-DRAM structural representation of buried regions N-type trap;
Fig. 4 is that the embodiment of the invention 4 is based on the heterojunction 1T-DRAM structural representation of buried regions N-type trap.
Embodiment
The invention provides a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap, comprise bottom silicon, be positioned at the buried regions N-type trap layer of described silicon base top and be positioned at the top layer silicon of described buried regions N-type trap layer top; Also include grid and the shallow trench that is positioned at the grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Be respectively equipped with source region and drain region in the top layer silicon between described grid and the shallow trench.
The present invention also provides a kind of method for preparing described heterojunction 1T-DRAM structure based on buried regions N-type trap, and step comprises:
Photoresist cover gate, shallow trench and described P type SiGe layer form the second opening at the grid opposite side, and the P type SiGe layer between the shallow trench of grid and described grid opposite side is come out, and by the second opening the P type SiGe layer that exposes are carried out N
+The type injection technology forms the drain region; Remove the residue photoresist.
With reference to the accompanying drawings, by specific embodiment heterojunction 1T-DRAM structure of the present invention is based on buried regions N-type trap and preparation method thereof is described in detail and describes, so that better understand content of the present invention, but following embodiment does not limit the scope of the invention.
With reference to Fig. 1, the preparation method of the described heterojunction 1T-DRAM structure based on buried regions N-type trap of preparation is as follows in the present embodiment:
Shown in Figure 1A, provide P type bottom silicon 1; Extension one deck N-type SiC layer 2 on P type silicon base 1, and make N-type SiC layer 2 thickness 〉=10nm, the molar content of C is between 0.01% ~ 10%; Above N-type SiC layer 2, extension one deck P type SiGe layer 3, and make P type SiGe layer 3 thickness 〉=30nm, the molar content of Ge (when the molar content of Ge is 100%, is being pure Ge layer) between 0.1% ~ 100%; At last, because GeO
2Unsteadiness, can also extension skim P type silicon layer 4 above P type SiGe layer, this layer thickness is far smaller than aforementioned three layers.
With reference to Figure 1B, preparation shallow trench 5, form shallow trench isolation from, and make the lower bottom part of shallow trench 5 be arranged in N-type SiC layer 2, namely the lower bottom part of shallow trench 5 is lower than the upper surface of N-type SiC layer 2 and is higher than the lower surface of N-type SiC layer 2; The upper bottom surface of shallow trench 5 is concordant with P type silicon layer 4 upper surfaces, namely is in the same level.
The concrete preparation technology of shallow trench 5 can implement with reference to prior art.
With reference to Fig. 1 C, between two adjacent shallow trenchs 5, form grid 6, the concrete preparation technology of grid 6 implements with reference to prior art.
After forming grid, can keep gate oxide 60 as follow-up selective epitaxial barrier layer in etch areas.
With reference to Fig. 1 D, photoresist 10 cover gate 6, shallow trench 5 and P type silicon layer 4, form the first opening (arrow locations among Fig. 1 D) by photoetching in a side of grid 6, P type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 one sides is come out, remove the P type silicon layer 4 that exposes in the first opening, expose P type SiGe layer 3, adopt Plasma Etch technique by the first opening the P type SiGe layer 3 that exposes to be carried out the selectivity Self-aligned etching, make the P type SiGe layer thickness that etches away account for P type SiGe layer gross thickness 1/5 to 4/5 between, form source region groove 70.
Remove residue photoresist 10.
With reference to Fig. 1 E, in the source region groove 70 that forms, carry out selective epitaxial growth N
+Type SiC forms source region 7 to filling up source region groove 70, and the molar content that makes C is between 0.01% to 10%.
With reference to Fig. 1 F, photoresist 10 cover gate 6, shallow trench 5 and P type silicon layer 4 and source region 7, form the second opening (arrow locations among Fig. 1 F) by photoetching at the opposite side of grid 6, P type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 opposite sides is come out, the P type silicon layer that exposes and following SiGe layer 3 are carried out drain region LDD injection technology, form the shallow doped region 81 in drain region, this technique can be implemented with reference to prior art.Remove the light residue and carve glue 10.
With reference to Fig. 1 G, in the outside of grid 6, form side wall 62, the concrete formation technique of side wall 62 can be implemented with reference to prior art.
With reference to Fig. 1 H and figure I, photoresist 10 cover gate 6, shallow trench 5 and P type SiGe layer 3(comprise P type silicon layer 4) and source region 7, again form opening (arrow locations among Fig. 1 F) by photoetching at the opposite side of grid 6, the shallow doped region in drain region comes out, and exposed region is carried out drain region N
+The type ion implantation technology forms drain region heavily doped region 82, and this technique can be implemented with reference to prior art.Remove the light residue and carve glue 10.
Those skilled in the art can be understood that, the formation in source region and drain region order can be changed in this step.
Carry out at last annealing process, activate the foreign ion that injects, form N
+Type SiGe drain region 8.
Adopt conventional NMOS technique, with source ground (GND), drain electrode connects bit line (Bit Line, BL), grid connects word line (Word Line, WL), form the 1T-DRAM unit.
With reference to Fig. 1 I and Fig. 1 J, the heterojunction 1T-DRAM structure based on buried regions N-type trap that the present embodiment above-mentioned steps forms, comprise that silicon base 1, N-type SiC layer 2(also can be called " buried regions N-type trap layer "), the tagma layer that forms of P type SiGe layer 3 and thin layer P type silicon layer 4, layer top, tagma is grid 6, the both sides of grid 6 are side wall 62, centered by grid, side wall 62 outsides of grid 6 both sides are respectively source region 7, drain region 8, and source region 7 is N
+Type SiC material, drain region 8 is N
+Type SiGe material, and drain region 8 is comprised of shallow doped region 81 and heavily doped region 82.
The grid below prepares the gate oxide that forms in the gate process in addition.
Source region and the drain region again outside are shallow trench 5, and the bottom surface of shallow trench 5 is positioned at N-type SiC layer 2.
With reference to Fig. 2, the present embodiment preparation is as follows based on the method for the heterojunction 1T-DRAM structure of buried regions N-type trap:
With reference to the described method of embodiment 1 step 1, provide P type silicon base 1, N-type SiC layer 2, P type SiGe layer 3 and thin layer P type silicon layer 4.
With reference to the method described in embodiment 1 step 2, form shallow trench 5.
With reference to Fig. 2 A, between adjacent two shallow trenchs 5, form grid 6.With reference to the described method of embodiment 1 step 3, similarly, also can keep gate oxide as follow-up selective epitaxial barrier layer.
Then carry out respectively LDD technique in the both sides of grid 6, and carry out low energy Ge Implantation, form the shallow doped region 71 in source region and the shallow doped region 81 in drain region.
With reference to the method described in Fig. 2 B and embodiment 1 step 4, photoresist 10 cover gate 6, shallow trench 5 and P type silicon layer 4, form the first opening (arrow locations among Fig. 2 B) by photoetching in a side of grid 6, P type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 one sides is come out, remove the P type silicon layer 4 that exposes in P the first opening, P type SiGe layer 3 is come out, adopt Plasma Etch technique by the first opening the P type SiGe layer 3 that exposes to be carried out the selectivity Self-aligned etching, make the P type SiGe layer thickness that etches away account for P type SiGe layer gross thickness 1/5 to 4/5 between, form source region groove 70.Remove residue photoresist 10.
With reference to Fig. 2 C, in the source region groove 70 that forms, carry out selective epitaxial growth N
+Type SiC forms source region 7 to filling up source region groove 70, and the molar content that makes C is between 0.01% to 10%.
With reference to Fig. 1 F, photoresist 10 cover gate 6, shallow trench 5 and P type SiGe layer 3(comprise P type silicon layer 4) and source region 7, form the second opening (arrow locations among Fig. 1 F) by photoetching at the opposite side of grid 6, the shallow doped region 81 in source region is come out, carry out drain region N to exposing the zone
+Ion implantation technology is injected high energy Ge ion and is formed drain region heavily doped region 81, and this technique can be implemented with reference to prior art.Remove the light residue and carve glue 10.
Annealing activates implanting impurity ion, forms N
+Type SiGe drain region.
Adopt conventional NMOS technique, with source ground (GND), drain electrode connects bit line (Bit Line, BL), grid connects word line (Word Line, WL), form the 1T-DRAM unit.
With reference to Fig. 2 E, the heterojunction 1T-DRAM structure based on buried regions N-type trap of the present embodiment preparation and is compared among the embodiment 1, and difference is:
Between source region 7 and grid 6, have the shallow doped region in source region, and described shallow doped region is N
+Type SiGe; N
+Type SiC source region 7 exists only in the zone between grid curb wall 62 and the shallow trench 5, and there is not N in the below of grid curb wall 62
+Type SiC source region.
Also can not implement LDD technique in the above embodiment of the present invention 1, but form the grid curb wall 62 rear N that directly carry out
+Implantation, in the case, as shown in Figure 3, the heterojunction 1T-DRAM structure based on buried regions N-type trap of the present embodiment preparation is compared with the heterojunction 1T-DRAM structure of preparation among the embodiment 1, and difference is, does not have the shallow doped region 81 in drain region.
Similarly, also can not implement LDD technique in the embodiment of the invention 2, but form the grid curb wall 62 rear N that directly carry out
+Implantation, in the case, as shown in Figure 4, the heterojunction 1T-DRAM structure based on buried regions N-type trap of the present embodiment preparation, compare with the heterojunction 1T-DRAM structure of preparation among the embodiment 2, difference is, does not have the shallow doped region 71 of the shallow doped region 81 in drain region and source region.
In the foregoing of the present invention, symbol SiGe refers to SiGe (Silicon-germanium) alloy, and not representing Si and Ge mol ratio is 1:1, also can be other mol ratios; Similarly, it is 1:1 that symbol SiC does not represent carbon and silicon mol ratio yet, also can be other mol ratios.
Above specific embodiments of the invention are described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of doing under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (10)
1. the heterojunction 1T-DRAM structure based on buried regions N-type trap is characterized in that, comprises bottom silicon, is positioned at the buried regions N-type trap layer of described silicon base top and is positioned at the top layer silicon of described buried regions N-type trap layer top; Also include grid and the shallow trench that is positioned at the grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Be respectively source region and drain region in the tagma layer between described grid and the shallow trench;
Wherein, described top layer silicon material is P type germanium silicon (SiGe), and described source region material is N
+Type carborundum (SiC), described drain region material is N
+Type SiGe, described buried regions N-type trap layer material is N-type SiC.
2. heterojunction 1T-DRAM structure according to claim 1 is characterized in that, described bottom silicon material is P type silicon.
3. heterojunction 1T-DRAM structure according to claim 1 is characterized in that, in described buried regions N-type trap layer and/or the source region, the molar content of C is 0.01% ~ 10%.
4. according to claim 1 or 3 described heterojunction 1T-DRAM structures, it is characterized in that described buried regions N-type trap layer thickness 〉=10nm.
5. heterojunction 1T-DRAM structure according to claim 1 is characterized in that, described top layer silicon top also comprises the P type silicon thin layer that is positioned at described grid below.
6. heterojunction 1T-DRAM structure according to claim 1 is characterized in that, in described P type SiGe layer and the described drain region, the molar content of Ge is 0.1 ~ 100%.
7. according to claim 5 or 6 described heterojunction 1T-DRAM structures, it is characterized in that described P type SiGe layer thickness 〉=30nm.
8. heterojunction 1T-DRAM structure according to claim 1 is characterized in that, described source region thickness is 1/5 ~ 4/5 of described P type SiGe layer thickness.
9. a method for preparing heterojunction 1T-DRAM structure as claimed in claim 1 is characterized in that, step comprises: bottom silicon silicon base; Generate N-type SiC layer in described silicon base; Above described N-type SiC layer, generate P type SiGe layer;
Step 2, the preparation shallow trench, and make described shallow trench bottom surface be arranged in described N-type SiC layer;
Step 3 prepares grid between adjacent two shallow trenchs;
Step 4, photoresist cover gate, shallow trench and described P type SiGe layer, form the first opening in grid one side, P type SiGe layer between the shallow trench of grid and described grid one side is come out, by the first opening the P type SiGe layer that exposes is carried out etching, but be not etched to described N-type SiC layer, form the source region groove, remove the residue photoresist; Selective growth N in the source region groove that forms
+Type SiC forms the source region to filling up described source region groove;
Photoresist cover gate, shallow trench and described P type SiGe layer form the second opening at the grid opposite side, and the P type SiGe layer between the shallow trench of grid and described grid opposite side is come out, and by the second opening the P type SiGe layer that exposes are carried out N
+The type Implantation forms the drain region; Remove the residue photoresist;
Step 5, annealing activates the foreign ion that injects and forms N
+Type SiGe drain region.
10. method according to claim 9 is characterized in that, described N-type SiC layer thickness 〉=10nm, and the C molar content is 0.01% ~ 10%; Described P type SiGe layer thickness 〉=30nm, the Ge molar content is 0.1% ~ 100%; Described N
+In the type SiGe drain region, the Ge molar content is 0.1% ~ 100%.
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| CN113054031A (en) * | 2021-03-12 | 2021-06-29 | 深圳方正微电子有限公司 | Metal oxide semiconductor field effect transistor and preparation method and application thereof |
| CN113054029A (en) * | 2021-03-12 | 2021-06-29 | 深圳方正微电子有限公司 | Metal oxide semiconductor field effect transistor and preparation method and application thereof |
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