CN103489914A - Static random access memory with non-symmetric transistor and control method thereof - Google Patents

Static random access memory with non-symmetric transistor and control method thereof Download PDF

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CN103489914A
CN103489914A CN201310076418.6A CN201310076418A CN103489914A CN 103489914 A CN103489914 A CN 103489914A CN 201310076418 A CN201310076418 A CN 201310076418A CN 103489914 A CN103489914 A CN 103489914A
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transistor
bit line
doped region
grid
static random
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CN103489914B (en
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沃尔堪·库尔散
沙伊尔弗·穆罕默德·萨拉赫丁
焦海龙
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Hong Kong University of Science and Technology HKUST
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Hong Kong University of Science and Technology HKUST
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET

Abstract

The invention discloses a non-symmetric transistor, a static random access memory with the non-symmetric transistor, and a control method of the static random access memory. The non-symmetric transistor comprises a first doped region at a first end of a transistor and a second doped region at a second end of the transistor, with the second end being opposite to the first end in a first direction, and further comprises a channel region between the first doped region and the second doped region, and a grid electrode disposed on the channel region. The first doped region and the second doped region are doped with impurities of first type. The magnitude of the conducting current from the first end to the second end of the transistor is different from that from the second end to the first end. According to the invention, the data reading stability is improved, the data writing ability is improved and the electric leakage power consumption is reduced in the data access process.

Description

Static random-access memory and control method thereof with non-symmetric transistor
Technical field
The application relates to non-symmetric transistor, adopts the static random-access memory of described non-symmetric transistor as bit line access device, and the control method of described static random-access memory.
Background technology
Static random-access memory (SRAM; Static Random Access Memory) be widely used in high-performance microprocessor and SOC (system on a chip).Constantly increase requirement performance improved constantly to meet Modern microprocessor and SOC (system on a chip) in the quantity of the on-chip memory technology node new at each.Along with the propelling of semiconductor technology node, supply voltage constantly reduces, and device size constantly dwindles, and read data stability and the write operation ability of static random-access memory (SRAM) are weakened.Simultaneously, a large amount of transistors is for the static random-access memory array of Modern microprocessor, and therefore memory array is the important sources of electricity leakage power dissipation.Therefore sram cell novel compactness, stable, low energy consumption urgently proposes.
Fig. 1 shows 6 layer transistor SRAM units of a standard.6 layer transistor SRAM units shown in Fig. 1 comprise two bit lines (BL and BLB), a word line (WL), two bit line access transistor (N3 and N4), and two cross-linked inverters (being comprised of P1, P2, N1 and N2).When read-write operation, two data memory nodes (node _ 1 and node _ 2) all pass through the bit line access transistor and directly are connected with bit line.In the sram cell shown in Fig. 1, in the read operation process, due to the dividing potential drop when the read cycle between pull-down transistor in bit line access transistor and cross-linked inverter, in 6 layer transistor SRAM units, the node of storage " 0 " is elevated to a magnitude of voltage higher than ground voltage.Therefore the intensity of the bit line access transistor in 6 layer transistor SRAM units should be than a little less than pull-down transistor, to keep enough read data stability.Contrary, in the write operation process, in order to write " 0 ", the back end of storage " 1 " is by the electric discharge of bit line access transistor.The intensity of the bit line access transistor in standard 6 layer transistor SRAM units should be stronger than pulling up transistor, in order to writing rate and wider write operation tolerance limit faster are provided in the write operation process.As can be seen here, in order to reach sufficiently high read data stability and write operation tolerance limit, for the bit line access transistor in standard 6 layer transistor SRAM units, there is mutual afoul dimensional requirement.Fig. 2 and Fig. 3 show respectively be typically used as the neutrality line of sram cell shown in Fig. 1 access transistor, symmetrical under lap (underlap) the interconnected type bigrid FinFET of N-shaped and the discrete type bigrid of the symmetrical under lap of N-shaped FinFET.Transistor shown in Fig. 2 and Fig. 3 has symmetrical grid under lap, and its On current from right to left is identical with On current size from left to right.Obviously, above-mentioned transistor can not meet in sram cell the mutual afoul dimensional requirement for the bit line access transistor.Therefore, need to provide and can alleviate above-mentioned dimensions and require, improve read data stability and write operation ability simultaneously and there is the more new device of low-leakage current.
Summary of the invention
The aspect according to the application, provide a kind of non-symmetric transistor, comprising: be positioned at first doped region and the second doped region that is positioned at described transistor the second end of described transistor first end, described the second end is relative with described first end along first direction; Channel region between described the first doped region and described the second doped region; And be arranged at the grid on described channel region, wherein, described the first doped region and described the second doped region are doped with first kind impurity, and the On current of described transistor from described first end to described the second end varies in size with the On current from described the second end to described first end.
According to an embodiment, described grid and described channel region are set to form asymmetrical grid under lap in described channel region both sides, and wherein the grid under lap length near described first end is less than the grid under lap length near described the second end.
According to an embodiment, described grid comprises along described first direction first and the second portion that work function is different, described first is near described first end, described second portion is near described the second end, and the gate work-function of described second portion is higher than the gate work-function of described first.
According to an embodiment, described the second doped region is also doped with Second Type impurity, thereby formation is doped with the extra doped region of Second Type impurity between described channel region and described the second doped region.
According to an embodiment, the doping content of described Second Type impurity is less than the doping content of described first kind impurity.
According to an embodiment, the doping gradient of described Second Type impurity is less than the doping gradient of described first kind impurity.
According to an embodiment, described first kind impurity is that N-shaped, described Second Type impurity are p-type.
According to an embodiment, described first kind impurity is that p-type, described Second Type impurity are N-shaped.
According to an embodiment, described the second doped region comprises along described first direction the first sub-doped region and the second sub-doped region that doping content is different, and the wherein said first sub-doped region is near described grid, and the described second sub-doped region is away from described grid.
According to an embodiment, the described first sub-doped region doping content of described the second doped region is lower than the described second sub-doped region doping content of described the second doped region.
According to an embodiment, described the first doped region comprises along described first direction the first sub-doped region and the second sub-doped region that doping content is different, the described first sub-doped region of wherein said the first doped region is near described grid, and the described second sub-doped region of described the first doped region is away from described grid.
According to an embodiment, the described first sub-doped region doping content of described the first doped region is lower than the described second sub-doped region doping content of described the first doped region, and the described first sub-doped region doping content of described the second doped region is lower than the described second sub-doped region doping content of described the second doped region.
According to an embodiment, the doped region length of the described first sub-doped region of described the second doped region is greater than the doped region length of the described first sub-doped region of described the first doped region.
According to an embodiment, described transistor is the FinFET transistor.
According to an embodiment, described transistor is single gridistor, interconnected type double gate transistor, discrete type double gate transistor, tri-gate transistor or all around gate transistor.
According to another aspect of the application, a kind of static random-access memory is provided, comprise the first bit line and the second bit line for reading and writing data, and at least one static random-access memory unit, described static random-access memory unit comprises: inverter group is connected between supply network and ground wire; The first bit line access device, be connected between the first port of described the first bit line and described inverter group, for controlling disconnection between described the first bit line and described the first port and being connected, and the second bit line accessor part, be connected between the second port of described the second bit line and described inverter group, for controlling disconnection between described the second bit line and described the second port and being connected, wherein said the first bit line accesses device and/or described the second bit line accessor part adopts foregoing non-symmetric transistor.
According to another aspect of the application, a kind of static random-access memory is provided, comprise the first bit line and the second bit line for reading and writing data, and at least one static random-access memory unit, described static random-access memory unit comprises: inverter group is connected between supply network and ground wire, the first bit line access device, be connected between the first port of described the first bit line and described inverter group, for controlling disconnection between described the first bit line and described the first port and being connected, and the second bit line accessor part, be connected between the second port of described the second bit line and described inverter group, for controlling disconnection between described the second bit line and described the second port and being connected, wherein said the first bit line access device and/or described the second bit line accessor part adopt foregoing non-symmetric transistor, and described the first bit line access device and/or described the second bit line accessor part are discrete type double gate transistor, a grid of described discrete type double gate transistor is controlled by write signal, another grid is by the Writing/Reading signal controlling simultaneously.
According to an embodiment, described inverter group comprises the first and second pull-up device and the first and second pull-down, and described pull-up device and pull-down form two cross-linked inverters.
According to an embodiment, described pull-up device and/or pull-down can adopt single gridistor, interconnected type double gate transistor, discrete type double gate transistor, tri-gate transistor or all around gate transistor.
According to an embodiment, as described the first bit line access device the time, the described first end of described non-symmetric transistor is connected to described the first bit line, described the second end is connected to described the first port; As described the second bit line accessor part the time, the described first end of described non-symmetric transistor is connected to described the second bit line, described the second end is connected to described the second port.
According to another aspect of the application, a kind of method of the above-mentioned static random-access memory according to another aspect of the application being carried out to read and write access is provided, comprise: when read operation, described write signal with described Writing/Reading signal in contrary logic state, so that gate turn-on of described the first bit line access device and/or described the second bit line accessor part and another grid remain off; And when write operation, described write signal with described Writing/Reading signal in identical logic state, so that a described grid and the equal conducting of another grid of described the first bit line access device and/or described the second bit line accessor part.
According to the application's apparatus and method, in the data access process, the data read stability strengthens, data writing capability improves and electricity leakage power dissipation reduces.
The accompanying drawing explanation
Fig. 1 is a kind of circuit diagram of 6 transistor static random-access memory unit.
Fig. 2 is the symmetrical under lap interconnected type of a kind of N-shaped bigrid FinFET(FinFET-UL-TG) schematic diagram.
Fig. 3 is the discrete type bigrid of the symmetrical under lap of a kind of N-shaped FinFET(FinFET-UL-IG) schematic diagram.
Fig. 4 is according to embodiment of the application, the asymmetric under lap interconnected type of N-shaped bigrid FinFET(FinFET-AU-TG) schematic diagram.
Fig. 5 is according to another embodiment of the application, the discrete type bigrid of the asymmetric under lap of N-shaped FinFET(FinFET-AL-IG) schematic diagram.
Fig. 6 is according to the two material interconnected type bigrid FinFET(FinFET-DM-TG of another embodiment of the application, N-shaped) schematic diagram.
Fig. 7 is according to the two discrete type bigrid of the material FinFET(FinFET-DM-IG of another embodiment of the application, N-shaped) schematic diagram.
Fig. 8 is according to another embodiment of the application, N-shaped codope diffusion interconnected type bigrid FinFET(FinFET-DD-TG) schematic diagram.
Fig. 9 spreads discrete type bigrid FinFET(FinFET-DD-IG according to another embodiment of the application, N-shaped codope) schematic diagram.
Figure 10 is the doping content schematic diagram of the diffusion of N-shaped codope shown in Fig. 8 and 9 FinFET.
Figure 11 is according to another embodiment of the application, N-shaped classification diffusion interconnected type bigrid FinFET(FinFET-GD-TG) schematic diagram.
Figure 12 spreads discrete type bigrid FinFET(FinFET-GD-IG according to another embodiment of the application, N-shaped classification) schematic diagram.
Figure 13 is the doping content schematic diagram of the diffusion of N-shaped classification shown in Figure 11 and 12 FinFET.
Figure 14 is according to the asymmetric classification diffusion of another embodiment of the application, N-shaped interconnected type bigrid FinFET(FinFET-AGD-IG) schematic diagram.
Figure 15 spreads discrete type bigrid FinFET(FinFET-AGD-IG according to another embodiment of the application, the asymmetric classification of N-shaped) schematic diagram.
Figure 16 is the doping content schematic diagram of the asymmetric classification diffusion of N-shaped shown in Figure 14 and 15 FinFET.
Figure 17 according to another embodiment of the application, there is the circuit diagram of the static random-access memory unit of asymmetric bit line access transistor.
Figure 18 is the circuit diagram according to the static random-access memory unit (SRAM-AU-TG) of another embodiment of the application.
Figure 19 is the circuit diagram according to the static random-access memory unit (SRAM-DD-TG) of another embodiment of the application.
Figure 20 is the circuit diagram according to the static random-access memory unit (SRAM-DM-TG) of another embodiment of the application.
Figure 21 is the circuit diagram according to the static random-access memory unit (SRAM-GD-TG) of another embodiment of the application.
Figure 22 is the circuit diagram according to the static random-access memory unit (SRAM-AGD-TG) of another embodiment of the application.
Figure 23 is the circuit diagram according to the static random-access memory unit (SRAM-AU-TG-I) of another embodiment of the application.
Figure 24 is the circuit diagram according to the static random-access memory unit (SRAM-DD-TG-I) of another embodiment of the application.
Figure 25 is the circuit diagram according to the static random-access memory unit (SRAM-DM-TG-I) of another embodiment of the application.
Figure 26 is the circuit diagram according to the static random-access memory unit (SRAM-GD-TG-I) of another embodiment of the application.
Figure 27 is the circuit diagram according to the static random-access memory unit (SRAM-AGD-TG-I) of another embodiment of the application.
Figure 28 according to another embodiment of the application, there is the circuit diagram of the static random-access memory unit of asymmetric bit line access transistor.
Figure 29 is the circuit diagram according to the static random-access memory unit (SRAM-AU-IG) of another embodiment of the application.
Figure 30 is the circuit diagram according to the static random-access memory unit (SRAM-DD-IG) of another embodiment of the application.
Figure 31 is the circuit diagram according to the static random-access memory unit (SRAM-DM-IG) of another embodiment of the application.
Figure 32 is the circuit diagram according to the static random-access memory unit (SRAM-GD-IG) of another embodiment of the application.
Figure 33 is the circuit diagram according to the static random-access memory unit (SRAM-AGD-IG) of another embodiment of the application.
Figure 34 is the circuit diagram according to the static random-access memory unit (SRAM-AU-IG-I) of another embodiment of the application.
Figure 35 is the circuit diagram according to the static random-access memory unit (SRAM-DD-IG-I) of another embodiment of the application.
Figure 36 is the circuit diagram according to the static random-access memory unit (SRAM-DM-IG-I) of another embodiment of the application.
Figure 37 is the circuit diagram according to the static random-access memory unit (SRAM-GD-IG-I) of another embodiment of the application.
Figure 38 is the circuit diagram according to the static random-access memory unit (SRAM-AGD-IG-I) of another embodiment of the application.
Figure 39 shows the experimental result according to the read operation static noise margin of the FinFET static random access memory cell of an example of the application.
Figure 40 shows the experimental result according to the write operation tolerance limit of the FinFET static random access memory cell of an example of the application.
Figure 41 shows the experimental result according to the electricity leakage power dissipation of the FinFET static random access memory cell of an example of the application.
Embodiment
The mode that below will can easily implement with the application those of ordinary skill in the field, a plurality of embodiments with reference to accompanying drawing to the application are elaborated.Below explanation is only illustrative rather than restrictive, and the application should not be construed as the embodiment that only limits to illustrate herein, in the situation that do not break away from the application's thought and technical scope, is understood to include all changes, equivalent and substitute.
The term that the application uses is only with explanation specific implementations and using, and is not used in invention is construed as limiting.For example, in the application, " comprise ", " possessing " or terms such as " having ", being interpreted as only for illustrating, existing described optional network specific digit, step, action, element, parts or its combination, is not to get rid of in advance the existence of one or more further feature, numeral, step, action, element, parts or its combination or additional possibility.
Adopted the terms such as " left side ", " right side " to describe multiple element with reference to the accompanying drawings herein, but these key elements should not be limited to above term and position relation shown in the drawings.Above term is only for the relative position between key element is described, and in the situation that do not break away from the application's thought and technical scope " left side ", " right side " can exchange.
In addition, adopt in this article first, second term such as grade that multiple element is described, use the purpose of described term to be to distinguish an element and another element, and not be construed as limiting.For example, in the situation that do not break away from the application's scope, the first element can called after the second element, and similarly, the second element also can called after the first element.
Except as otherwise noted, all terms, comprise technology or scientific terminology as used herein, has the identical implication of usually understanding with the application those of ordinary skill in the field.The defined identical term of normally used dictionary, be interpreted as the implication that has with the correlation technique context consistent, except the application clearly defines, should not be construed to the desirable or implication of form too.
Below in conjunction with accompanying drawing, the application's specific embodiment is elaborated.In accompanying drawing, similar element is used similar Reference numeral, and omits the repeat specification to same element.
Fig. 4 is according to embodiment of the application, the transistorized schematic diagram of a kind of Novel asymmetric.In Fig. 4, adopted the asymmetric under lap interconnected type of N-shaped bigrid FinFET(FinFET-AU-TG) structure be that example describes Novel asymmetric transistor of the present invention.Be understandable that, the concrete device architecture adopted in illustrations and embodiment and circuit structure are all exemplary and nonrestrictive, and those skilled in the art can, based on the disclosed content of the application, select other different designs.For example, non-symmetric transistor of the present invention can be p-type but not N-shaped, can adopt single gridistor, double gate transistor (interconnected type or discrete type), tri-gate transistor or all around gate transistor according to the difference of grid structure, and can adopt the transistor of the other types except FinFET, as long as can realize the application's scheme.
Transistor shown in Fig. 4 comprise by the N-shaped diffusion region, formed lay respectively at left side and the source/drain on right side, the unadulterated channel region between source electrode and drain electrode, the grid of the other both sides of channel region and be formed on grid and channel region between gate insulation layer.Figure 4 shows that the interconnected type double-grid structure.As shown in Figure 4, according to the under lap of asymmetric gate under lap FET in the raceway groove left and right sides of the present embodiment, have different length, wherein grid left side under lap length is less than grid right side under lap length.With the symmetrical grid under lap FinFET shown in Fig. 2, compare, the under lap of asymmetric gate shown in Fig. 4 FinFET grid left side under lap length is less than the under lap length of symmetrical grid under lap FinFET in Fig. 2, and grid right side under lap length is greater than the under lap length of symmetrical grid under lap FinFET in Fig. 2 simultaneously.In the transistor shown in Fig. 4, can be according to the different On currents that produce different sizes of the sense of current.And, when producing similar On current, with symmetrical under lap grid FinFET, compare, the leakage current that asymmetric under lap grid FinFET produces is less.
Specifically, when the left end voltage of device, during higher than right-hand member, left end is drain electrode, and right-hand member is source electrode.Because the under lap on right side is longer, the gate edge field can not excite on the transistor right side charge carrier of enough concentration, and therefore the right side channel resistance also increases.On current from left to right reduces because of the channel resistance that right side increases.Otherwise during higher than left end, right-hand member is drain electrode when right-hand member voltage, left end is source electrode.Because the under lap zone in left side is less, the under lap zone is modulated effectively to excite the charge carrier of enough concentration in the gate edge field, and therefore the left side channel resistance reduces.Thereby reduced the channel resistance on drain electrode depletion region the right.Effective channel resistance of FinFET also thereby reduce.The On current that therefore transistor On current from right to left compares from left to right increases.Therefore in asymmetric gate under lap FinFETs device from right to left and On current from left to right be dynamically to adjust.In addition, owing to having increased channel length, asymmetric under lap grid FinFET reduces to some extent than the leakage current of symmetrical under lap grid FinFET.Determine that by the sense of current characteristic that different On currents and asymmetric under lap grid FinFET reduce leakage current also can realize in the single gridistor of asymmetric under lap, asymmetric under lap tri-gate transistor and asymmetric under lap all around gate transistor.
Fig. 5 shows according to the discrete type bigrid of the asymmetric under lap of N-shaped another embodiment of the application, a kind of FinFET.In Fig. 5, two of FinFET independent gates can be controlled separately separately, in Fig. 5, the device architecture of FinFET is identical with the FinFET in Fig. 4.In the accompanying drawings, grid _ F means normal-gate.Grid _ B means rear grid.Similar to asymmetric under lap interconnected type bigrid FinFET in Fig. 4, the transistor in Fig. 5 can produce the On current of different sizes and reduce leakage current according to the sense of current.
Fig. 6 is according to the schematic diagram of another embodiment of the application, a kind of pair of material gate transistor.In Fig. 6, adopted the two material interconnected type bigrid FinFET(FinFET-DM-TG of N-shaped) structure be example describes.Similar with Fig. 4, the transistor shown in Fig. 6 also comprises source/drain, channel region, grid and gate insulation layer.Transistor shown in Fig. 6 has identical length in the grid under lap of the raceway groove left and right sides, but its grid is divided into two parts.Two parts work function of this grid is adjusted into device the right work function higher than the left side.
When the left end voltage of device, during higher than right-hand member, left end is source electrode for the drain electrode right-hand member.Because the right work function is higher than the left side, the grid electric field can not be modulated raceway groove the right with in source electrode one side (device the right) the higher carrier concentration in the rate of induced polarization left side, so effective raceway groove series resistance on device the right increases to some extent than the left side.When left end is drain electrode, therefore the On current from the device left side to the right reduces.
Another kind of situation is, when the right-hand member voltage of device, during higher than left end, right-hand member is source electrode for the drain electrode left end.The under lap zone is modulated effectively to excite a high carrier concentration in gate edge field, the left side.When left end is source electrode and right-hand member during for drain electrode, therefore the raceway groove series resistance on the device left side can reduce.And then the depletion region on raceway groove the right that drain electrode excites can reduce the channel resistance below grid.When right-hand member is drain electrode, therefore whole raceway groove series resistance can reduce.In device, electric conduction from right to left fails to be convened for lack of a quorum so than increase to some extent from left to right.And then the work function of increase makes leakage current the reducing to some extent than single material grid FinFET of two material grid FinFET.Therefore, have in two material grid FinFET devices from right to left and electric current from left to right is dynamically to adjust.This transistor produces the On current of different sizes and reduces leakage current according to the sense of current.Determining by the sense of current that different On currents and codope diffusion FinFET reduces the characteristic of leakage current also can be at two bill of materials gridistor, and two material tri-gate transistors and two rings of material realize in gridistor.
Fig. 7 shows according to the two discrete type bigrid of the material FinFET of N-shaped another embodiment of the application, a kind of.In Fig. 7, two independent gates can be controlled separately separately, identical with in Fig. 6 of device architecture in Fig. 7.Similar to two material interconnected type bigrid FinFET in Fig. 6, in Fig. 7, transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.
Fig. 8 is according to the schematic diagram of another embodiment of the application, a kind of codope diffusion transistor.In Fig. 8, adopted N-shaped codope diffusion interconnected type bigrid FinFET(FinFET-DD-TG) structure be example describes.Similar with Fig. 4, the transistor shown in Fig. 8 also comprises channel region, grid, gate insulation layer and the source/drain that lays respectively at left side and right side formed by the N-shaped diffusion region.Transistor shown in Fig. 8 has identical length in the grid under lap of the raceway groove left and right sides, but additionally increased p-type diffusing, doping near the channel region place along N-shaped diffusing, doping district on device the right, thereby formed the extra doped region doped with p-type impurity between channel region and N-shaped diffusing, doping district, right side.Figure 10 shows the doping content of the codope of N-shaped shown in Fig. 8 diffusion FinFET.As shown in figure 10, the p-type doping content is lower than N-shaped doping content.And the doping gradient of p-type doping is higher than N-shaped.Therefore the p-type doping on device the right expands to the grid below towards the device left side.
When the left end voltage of device, during higher than right-hand member, left end is source electrode for the drain electrode right-hand member.Due to the right channel doping, higher than the left side, the grid electric field can not be modulated raceway groove the right in source terminal (device the right), to produce a high carrier concentration.Effective raceway groove series resistance on device the right increases to some extent than the left side.When therefore left end also reduces for On current from left to right in when drain electrode device.
Another kind of situation is, when the right-hand member voltage of device, during higher than left end, right-hand member is source electrode for the drain electrode left end.The device left side does not adopt extra p-type doping.Left side grid electric field fringing field is modulated the under lap zone effectively to excite a high carrier concentration.While with right-hand member, being source electrode, compare, when left end is source electrode, device left side raceway groove series resistance reduces.And then the depletion region that the drain electrode of raceway groove the right excites has reduced the channel resistance of grid below p-type doped region.When right-hand member is drain electrode end, therefore whole raceway groove series resistance can reduce.Device On current ratio increase to some extent from left to right from right to left.Therefore have in the FinFET device of codope diffusion region from right to left and electric current from left to right is dynamically to adjust.In addition, with single doped F inFET, compare, owing to having raised potential barrier, the leakage current of codope diffusion FinFET is reduced to some extent.Therefore this transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.Determine that by the sense of current characteristic that different On currents and codope diffusion FinFET reduces leakage current also can spread single gridistor in codope, codope diffusion tri-gate transistor and codope diffuser ring are realized in gridistor.
Fig. 9 shows according to codope another embodiment of the application, a kind of and spreads discrete type FinFET.In Fig. 9, two independent gates can be controlled separately separately, in Fig. 9, device architecture is identical with device in Fig. 8.Similar to two material interconnected type bigrid FinFET in Fig. 8, in Fig. 9, transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.
Figure 11 is according to the schematic diagram of another embodiment of the application, a kind of classification diffusion transistor.In Figure 11, adopted N-shaped classification diffusion interconnected type bigrid FinFET(FinFET-GD-TG) structure be example describes.Similar with Fig. 4, the transistor shown in Figure 11 also comprises channel region, grid, gate insulation layer and the source/drain that lays respectively at left side and right side formed by the N-shaped diffusion region.Transistor shown in Figure 11 has identical length in the grid under lap of the raceway groove left and right sides, but its right diffusion region doping content is divided into two different doping grades.Figure 13 is the doping content schematic diagram of N-shaped classification diffusion FinFET in Figure 11.As shown in figure 13, the nearly grid in right diffusion region place diffusion concentration is low and high in right-hand other zones.
When the left end voltage of device, during higher than right-hand member, left end is source electrode for the drain electrode right-hand member.Due to grid the right diffusing, doping, lower than the left side, the grid electric field can not be modulated raceway groove the right at source electrode (device the right), to excite enough large carrier concentration.Device the right effectively raceway groove series resistance increases to some extent than the left side.Therefore when left end when draining in device On current from left to right because of the higher channel resistance in the right, reduce.
Another kind of situation is, when the right-hand member voltage of device, during higher than left end, right-hand member is source electrode for the drain electrode left end.Diffusion region, grid left side doping content is higher than grid the right.The under lap zone is modulated effectively to excite enough carrier concentrations in gate edge field, the left side.While with right-hand member, being source electrode, compare, when left end is source electrode, therefore device left side raceway groove series resistance reduces.And then the depletion region that on the right of raceway groove, drain electrode excites has reduced the channel resistance of grid the right doped regions.When right-hand member is drain electrode, therefore whole raceway groove series resistance reduces.In device, On current from right to left is therefore than increase to some extent from left to right.Therefore have in classification diffusion FinFET device from right to left and electric current from left to right is dynamically to adjust.In addition, owing to having raised potential barrier, the leakage current of classification diffusion FinFET reduces to some extent than symmetrical FinFET.Therefore this transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.Determine that by the sense of current characteristic that different On currents and classification diffusion FinFET reduces leakage current also can spread single gridistor in classification, classification diffusion tri-gate transistor and classification diffuser ring are realized in gridistor.
Figure 12 shows according to N-shaped classification another embodiment of the application, a kind of and spreads discrete type bigrid FinFET.In Figure 12, two independent gates can be controlled separately separately, in Figure 12, device architecture is identical with device in Figure 11.Similar to classification diffusion interconnected type bigrid FinFET in Figure 11, in Figure 12, transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.
Figure 14 is according to the schematic diagram of another embodiment of the application, a kind of asymmetric classification diffusion transistor.In Figure 14, adopted the asymmetric classification of N-shaped diffusion interconnected type bigrid FinFET(FinFET-AGD-IG) structure be that example describes.Similar with Fig. 4, the transistor shown in Figure 14 also comprises channel region, grid, gate insulation layer and the source/drain that lays respectively at left side and right side formed by the N-shaped diffusion region.Transistor shown in Figure 14 has identical length in the grid under lap of the raceway groove left and right sides, but the doping content of each diffusion region is divided into two different doping grades.Figure 16 is the doping content schematic diagram of the asymmetric classification diffusion of N-shaped shown in Figure 14 FinFET.As shown in figure 16, the nearly grid place doping content of each diffusion region is low, and the rightmost side doping content of the leftmost side of left part diffusion region and right part diffusion region is high, while high diffusing, doping zone, device right side is from grid than away from left side, and the low diffusing, doping zone length in grid the right is longer than the left side.
When the left end voltage of device, during higher than right-hand member, left end is source electrode for the drain electrode right-hand member.Owing to comparing with left side, device right side high concentration diffusing, doping region distance grid is far away, and the grid electric field can not be modulated raceway groove the right in source electrode one side (the right of device), to excite enough carrier concentrations.Device the right effectively raceway groove series resistance increases to some extent than the left side.When left end is when drain electrode, in device, On current from left to right reduces because of the higher channel resistance in the right.
Another kind of situation is, when the right-hand member voltage of device, during higher than left end, right-hand member is source electrode for the drain electrode left end.With right side, compare, grid left side high concentration diffusing, doping region distance grid is nearer.Low doped region is modulated effectively to excite enough carrier concentrations in gate edge field, the left side.While with right-hand member, being source electrode, compare, when left end is source electrode, therefore device left side raceway groove series resistance reduces.And then the depletion region that on the right of raceway groove, drain electrode excites has reduced the channel resistance of grid the right low doped region.When right-hand member for when drain electrode whole raceway groove series resistance therefore reduce.In device, On current from right to left is also therefore than from left to right increase to some extent.Therefore have in asymmetric classification diffusion FinFET device from right to left and electric current from left to right is dynamically to adjust.In addition, because the leakage current of having raised the asymmetric classification diffusion of potential barrier FinFET reduces to some extent than symmetrical FinFET.Therefore this transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.Determine that by the sense of current characteristic that different On currents and asymmetric classification diffusion FinFET reduces leakage current also can spread single gridistor in asymmetric classification, asymmetric classification diffusion tri-gate transistor and asymmetric classification diffuser ring are realized in gridistor.
Figure 15 shows the asymmetric classification according to N-shaped another embodiment of the application, a kind of and spreads discrete type bigrid FinFET.In Figure 15, two independent gates can be controlled separately separately, in Figure 15, device architecture is with identical in Figure 14.Similar to asymmetric classification diffusion interconnected type bigrid FinFET in Figure 14, in Figure 15, transistor can produce the On current of different sizes and reduce leakage current according to the sense of current.
Above in conjunction with exemplary, asymmetric under lap transistor (as shown in Figures 4 and 5), two material gate transistor (as shown in Figures 6 and 7), codope diffusion transistor (as shown in FIG. 8 and 9), classification diffusion transistor (as shown in FIG. 11 and 12) and the asymmetric classification diffusion transistor (as shown in FIG. 14 and 15) to the application is illustrated respectively.According to the application, the structure of above-mentioned each embodiment can be carried out combination each other, and the structure that its various combinations obtain is all in the application in claimed scope.
For instance, according to another embodiment of the application, transistor of the present invention can have the two material gate structures shown in the asymmetric under lap structure shown in Fig. 4 and Fig. 6 simultaneously.; transistorized grid and channel region are set to form in the channel region both sides asymmetrical grid under lap; wherein under lap length in grid left side is less than grid right side under lap length, and grid is divided into two parts, and the right half gate work-function is higher than the left half gate work-function.According to another embodiment of the application, transistor of the present invention can have the two material gate structures shown in the asymmetric under lap structure shown in Fig. 4, Fig. 6 and the codope diffusion structure shown in Fig. 8 simultaneously.; transistorized grid left side under lap length is less than grid right side under lap length; and grid right half gate work-function is higher than the left half gate work-function; transistor the right has additionally increased the p-type diffusing, doping near the channel region place along N-shaped diffusing, doping district simultaneously, thereby forms the extra doped region doped with p-type impurity between channel region and N-shaped diffusing, doping district, right side.According to another embodiment of the application, transistor of the present invention can have the classification diffusion structure shown in the two material gate structures shown in the asymmetric under lap structure shown in Fig. 4, Fig. 6, the codope diffusion structure shown in Fig. 8 and Figure 11 simultaneously.; transistorized grid left side under lap length is less than grid right side under lap length; grid right half gate work-function is higher than the left half gate work-function; form the extra doped region doped with p-type impurity between transistor channel region and N-shaped diffusing, doping district, right side simultaneously; and N-shaped diffusing, doping district, right side doping content is divided into two different doping grades, and nearly grid place diffusion concentration is low and high in right-hand other zones.According to another embodiment of the application, transistor of the present invention can have the asymmetric classification diffusion structure shown in the two material gate structures shown in the asymmetric under lap structure shown in Fig. 4, Fig. 6, the codope diffusion structure shown in Fig. 8 and Figure 14 simultaneously., transistorized grid left side under lap length is less than grid right side under lap length, grid right half gate work-function is higher than the left half gate work-function, form the extra doped region doped with p-type impurity between transistor channel region and N-shaped diffusing, doping district, right side simultaneously, and the doping content in N-shaped diffusing, doping district, the left and right sides is divided into two different doping grades, the nearly grid place doping content of each diffusion region is low, and the rightmost side doping content of the leftmost side of left part diffusion region and right part diffusion region is high, simultaneously high diffusing, doping zone, device right side from grid than away from left side, be that the low diffusing, doping zone length in grid the right is longer than the left side.
Below only several possible combining structures have been carried out to exemplary illustration, the content that those skilled in the art put down in writing based on the application, can learn other various possible combining structures, therefore at this, will not enumerate.Above-mentioned various possible structure all within the spirit and scope of the present invention.
Abovely take in non-symmetric transistor On current from right to left and be illustrated as example than structure that from left to right On current is large; but as mentioned before; " left side " herein, " right side " are only for illustrating the relative position between key element; it will be appreciated by persons skilled in the art that will be above " left side ", " right side " in transistor arrangement exchanged so that in transistor, On current is less too in the application in claimed scope than On current from left to right from right to left.No longer it is enumerated herein.
Figure 17 shows according to another embodiment of the application, static random-access memory unit that have asymmetric bit line access transistor.As shown in figure 17, static random-access memory unit 1000 comprises two bit lines BL for reading and writing data and BLB, word line WL, two bit line access devices 100 and 300 and the inverter group 200 that is comprised of two cross-linked inverters.Inverter group 200 is connected between supply network and ground wire, and is connected to respectively bit line access quartz crystal device 100 and 300 by two data memory nodes (node _ 1 and node _ 2), thereby with bit line BL, with BLB, is connected respectively.Inverter group 200 comprises pull-up device 210 and 230 and pull-down 220 and 240, and described pull-up device and pull-down form two cross-linked inverters.
According to the present embodiment, the static random-access memory unit in Figure 17 has adopted non-symmetric transistor of the present invention as the bit line access transistor.The embodiment according to the application, the left side of non-symmetric transistor is connected in bit line, right side is connected in data memory node, thereby, when memory cell is worked, the electric current that flows to data memory node from bit line is less than the electric current that flows to bit line from data memory node.Obviously, when adopting with the heterochiral non-symmetric transistor of structure shown in accompanying drawing (be in transistor On current than from left to right On current is little) from right to left, the right side that adopts non-symmetric transistor is connected in to the connected mode that bit line, left side are connected in data memory node, thereby, when memory cell is worked, still make the electric current that flows to data memory node from bit line be less than the electric current that flows to bit line from data memory node.The bit line access transistor can be realized by the asymmetric under lap transistor as introduced above, two material gate transistor, codope diffusion transistor, classification diffusion transistor, asymmetric classification diffusion transistor or the above-mentioned non-symmetric transistor with combining structure.Above-mentioned bit line access transistor also can be single gridistor, double gate transistor, tri-gate transistor or all around gate transistor.In addition, single gridistor, double gate transistor (interconnected type or discrete type), tri-gate transistor or all around gate transistor all can be used for drawing and pull-down transistor.When pulling up transistor by double gate transistor (discrete type) while realizing, the grid that this discrete type pulls up transistor is connected with supply network and another grid is controlled by data memory node.When the pulldown transistor by double gate transistor (discrete type) while realizing, a grounded-grid of this discrete type pull-down transistor and another grid is controlled by data memory node.
Figure 18 to Figure 27 has showed adopted respectively 10 the concrete examples of non-symmetric transistor of the present invention as described above as the bit line access transistor in the unit of static random-access memory shown in Figure 17.
Wherein, Figure 18 to Figure 22 has showed 5 static random-access memory unit (SRAM-AU-TG that typically have the asymmetric bit line access transistor of interconnected type bigrid FinFET, SRAM-DD-TG, SRAM-DM-TG, SRAM-GD-TG and SRAM-AGD-TG) example.As shown in the figure, two bit line access devices 100 and 300 adopt respectively non-symmetric transistor N3 and N4, and pull-up device 210 and 230 adopts respectively transistor P1 and P2, and pull-down 220 and 240 adopts respectively transistor N1 and N2.
Be understandable that, the physical circuit illustrated herein is all exemplary and nonrestrictive, and those skilled in the art can, based on the disclosed content of the application, select other different physical circuits designs according to different design expectations.For example, write bit line access device, pull-up device and pull-down can be individual devices (as single transistor) or device network (as the network of a plurality of transistors formations).Inverter group can adopt other different circuit structures.The content that those skilled in the art put down in writing based on the application, can learn and the concrete structure of above-mentioned various possible memory cell therefore will not enumerate herein.
In Figure 18, the bit line access transistor is realized by asymmetric under lap grid FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.For show clear for the purpose of, in accompanying drawing, asymmetric under lap gridistor means with two asymmetric thick lines at channel region.Symmetrical under lap gridistor means with two symmetrical thick lines at channel region.In Figure 19, the bit line access transistor is realized by codope diffusion FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In accompanying drawing, the codope diffusion transistor means with real triangle at channel region.In Figure 20, the bit line access transistor is realized by two material grid FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In accompanying drawing, two material gridistors mean by space rectangles at channel region.In Figure 21, the bit line access transistor is realized by classification diffusion FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In accompanying drawing, the classification diffusion transistor means with L shaped thick line at channel region.In Figure 22, the bit line access transistor is realized by asymmetric classification diffusion FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In accompanying drawing, asymmetric classification diffusion transistor means with asymmetric T shape thick line at channel region.SRAM-AU-TG(Figure 18), SRAM-DD-TG(Figure 19), SRAM-DM-TG(Figure 20), SRAM-GD-TG(Figure 21) and SRAM-AGD-TG(Figure 22) be used as strengthening the data read stability of static random-access memory unit, improve data writing capability and reduce electricity leakage power dissipation.
Similar with Figure 18 to Figure 22, Figure 23 to 29 has showed other 5 examples that typically have the static random-access memory unit (SRAM-AU-TG-I, SRAM-DD-TG-I, SRAM-DM-TG-I, SRAM-GD-TG-I and SRAM-AGD-TG-I) of the asymmetric bit line access transistor of interconnected type bigrid FinFET.In Figure 23, the bit line access transistor is realized by the asymmetric under lap grid of interconnected type bigrid FinFET.On draw with pull-down transistor and realized by the discrete type bigrid of symmetry and symmetrical interconnected type bigrid FinFET respectively.In Figure 24, the bit line access transistor is realized by codope diffusion interconnected type bigrid FinFET.On draw with pull-down transistor and realized by the discrete type bigrid of symmetry and discrete type bigrid FinFET respectively.In Figure 25, the bit line access transistor is realized by two material gate interconnection type bigrid FinFET.On draw with pull-down transistor and realized by the discrete type bigrid of symmetry and symmetrical interconnected type bigrid FinFET respectively.In Figure 26, the bit line access transistor is realized by classification diffusion interconnected type bigrid FinFET.On draw with pull-down transistor and realized by the discrete type bigrid of symmetry and symmetrical interconnected type bigrid FinFET respectively.In Figure 27, the bit line access transistor is realized by asymmetric classification diffusion interconnected type bigrid FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid and discrete type bigrid FinFET respectively.SRAM-AU-TG-I(Figure 23), SRAM-DD-TG-I(Figure 24), SRAM-DM-TG-I(Figure 25), SRAM-GD-TG-I(Figure 26) and SRAM-AGD-TG-I(Figure 27) be used as strengthening the data read stability of static random-access memory unit, improve data writing capability and reduce electricity leakage power dissipation.
In this article, about the control method of memory, the course of work in connection with memory describes.Below take in Figure 18 to Figure 27 10 static random-access memory unit showing and be described as the course of work of example to memory cell of the present invention.According to control method of the present invention, in not accessed unit, word line (WL) signal keeps 0V.The bit line access transistor is cut-off state.Cell data is kept by cross coupling inverter.Bit line periodically preliminary filling is Vdd.When becoming Vdd, word-line signal can initiate a read operation.The conducting of bit line access transistor.If one " 0 " has been stored in node _ 1, bit line is by N3 and N1 electric discharge.Because read current flows to the grid memory node of unit from bit line, the end points of the N3 be connected with bit line is (as FinFET-AU-TG in Fig. 4, FinFET-DM-TG in Fig. 6, FinFET-DD-TG in Fig. 8, the left end of FinFET-AGD-TG in FinFET-GD-TG or Figure 14 in Figure 11) be drain electrode.Due to the higher raceway groove series resistance of asymmetric bit line access transistor, the weakened of N3 in read operation.Therefore intrinsic data disturb (being caused by the dividing potential drop between N3 and N1) to be reduced significantly by asymmetric bit line access transistor.The new asymmetric bit line access transistor proposed can strengthen the data read stability.
Before a write operation, by the data of importing into, determine that a bit line discharges of the accessed row of memory array is to 0V.Word-line signal becomes Vdd and initiates a write operation process.The conducting of bit line access transistor.If " 0 " on bit line is write to the node that originally is stored as " 1 " _ 1, and bit line access transistor (N3) is 0V by node _ 1 from the Vdd electric discharge with (P1) competition that pulls up transistor.Because write current flows to bit line from the cell data memory node, the end points of the N3 be connected with bit line is (as FinFET-AU-TG in Fig. 4, FinFET-DM-TG in Fig. 6, FinFET-DD-TG in Fig. 8, the left end of FinFET-AGD-TG in FinFET-GD-TG or Figure 14 in Figure 11) be source electrode.Due to the raceway groove series resistance that asymmetric bit line access transistor reduces, the intensity of N3 is enhanced in the write operation process.The asymmetric bit line access transistor that therefore write capability of the new static random-access memory unit proposed is suggested improves.Thereby the data read stability of static random-access memory and write capability require to be solved by the new asymmetric bit line access transistor in this new static random-access memory monotechnics for the contradiction of transistor size.
Figure 28 shows according to another embodiment of the application, static random-access memory unit that have asymmetric bit line access transistor.The difference of scheme shown in scheme shown in Figure 28 and Figure 17 is, the memory cell shown in Figure 17 only adopts a word line WL, and the memory cell neutrality line access transistor shown in Figure 28 is controlled and Writing/Reading signal WR co-controlling by write signal W.In the embodiment shown in Figure 28, the bit line access transistor is realized by discrete type double gate transistor.A grid of this bit line access transistor is controlled by write signal W, and another grid is controlled by Writing/Reading signal WR simultaneously.When read operation, write signal in contrary logic state, so that a gate turn-on of bit line access transistor and another grid remain off, thereby makes the intensity of bit line access transistor die down in the read operation process with the Writing/Reading signal.When write operation, write signal in identical logic state, so that grid of bit line access transistor and the equal conducting of another grid, thereby makes the intensity of bit line access transistor be enhanced in the write operation process with the Writing/Reading signal.The bit line access transistor of take is that the N-shaped transistor is example, and in the process of a read operation, Writing/Reading signal WR becomes Vdd and write signal W maintenance 0V.In the process of a write operation, write signal W and Writing/Reading signal WR become Vdd.On draw or pull-down transistor can adopt single gridistor, double gate transistor (interconnected type or discrete type), tri-gate transistor or all around gate transistor.When pulling up transistor by double gate transistor (discrete type) while realizing, the grid that this discrete type pulls up transistor is connected with supply network and another grid is controlled by data memory node.When the pulldown transistor by double gate transistor (discrete type) while realizing, a grounded-grid of this discrete type pull-down transistor, another grid is controlled by data memory node.
Similar with Figure 18 to Figure 27, Figure 29 to Figure 38 has showed adopted respectively 10 the concrete examples of asymmetric discrete type double gate transistor of the present invention as described above as the bit line access transistor in the unit of static random-access memory shown in Figure 28.
Wherein, Figure 29 to 33 has showed 5 examples that typically have the static random-access memory unit (SRAM-AU-IG, SRAM-DD-IG, SRAM-DM-IG, SRAM-GD-IG and SRAM-AGD-IG) of asymmetric discrete type bigrid bit line access transistor.As shown in the figure, two bit line access devices 100 and 300 adopt respectively non-symmetric transistor N3 and N4, and pull-up device 210 and 230 adopts respectively transistor P1 and P2, and pull-down 220 and 240 adopts respectively transistor N1 and N2.
In Figure 29, the bit line access transistor is realized by the asymmetric under lap grid of discrete type bigrid FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In Figure 30, the bit line access transistor spreads discrete type bigrid FinFET by codope and realizes.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In Figure 31, the bit line access transistor is realized by the discrete type bigrid of two materials FinFET.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In Figure 32, the bit line access transistor spreads discrete type bigrid FinFET by classification and realizes.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.In Figure 33, the bit line access transistor spreads discrete type bigrid FinFET by asymmetric classification and realizes.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid FinFET.SRAM-AU-IG(Figure 29), SRAM-DD-IG(Figure 30), SRAM-DM-IG(Figure 31), SRAM-GD-IG(Figure 32) and SRAM-AGD-IG(Figure 33) be used as strengthening the data read stability of static random-access memory unit, improve data writing capability and reduce electricity leakage power dissipation.
Figure 34 to 38 has showed other 5 examples that typically have the static random-access memory unit (SRAM-AU-IG-I, SRAM-DD-IG-I, SRAM-DM-IG-I, SRAM-GD-IG-I and SRAM-AGD-IG-I) of the asymmetric bit line access transistor of discrete type bigrid FinFET.In Figure 34, the bit line access transistor is realized by the discrete type bigrid of asymmetric under lap FinFET.On draw with pull-down transistor and realized by symmetry discrete type bigrid FinFET and symmetrical interconnected type bigrid FinFET respectively.In Figure 35, the bit line access transistor spreads discrete type bigrid FinFET by codope and realizes.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid and discrete type bigrid FinFET respectively.In Figure 36, the bit line access transistor is realized by the discrete type bigrid of two materials FinFET.On draw with pull-down transistor and realized by symmetry discrete type bigrid FinFET and symmetrical interconnected type bigrid FinFET respectively.In Figure 37, the bit line access transistor spreads discrete type bigrid FinFET by classification and realizes.On draw with pull-down transistor and realized by the discrete type bigrid of symmetry and symmetrical interconnected type bigrid FinFET respectively.In Figure 38, the bit line access transistor spreads discrete type bigrid FinFET by asymmetric classification and realizes.On draw with pull-down transistor and realized by symmetrical interconnected type bigrid and discrete type bigrid FinFET respectively.SRAM-AU-IG-I(Figure 34), SRAM-DD-IG-I(Figure 35), SRAM-DM-IG-I(Figure 36), SRAM-GD-IG-I(Figure 37) and SRAM-DM-IG-I(Figure 38) be used as strengthening the data read stability of static random-access memory unit, improve data writing capability and reduce electricity leakage power dissipation.
Below take in Figure 29 to Figure 38 10 static random-access memory unit showing and be described as the course of work of example to the present embodiment memory cell.According to control method of the present invention, in not accessed unit, write signal W and Writing/Reading signal WR keep 0V.The bit line access transistor is cut-off state.Bit line periodically preliminary filling is Vdd.Writing/Reading signal WR can initiate a read operation while becoming Vdd.In the read operation process, discrete type bigrid bit line access transistor only has a gate turn-on.Therefore the intensity of bit line access transistor dies down in the read operation process.If one " 0 " has been stored in node _ 1, bit line is by N3 and N1 electric discharge.Because read current flows to the cell data memory node from bit line, the end points of the N3 be connected with bit line is (as FinFET-AU-IG in Fig. 5, FinFET-DM-TG in Fig. 7, FinFET-DD-IG in Fig. 9, the left end of FinFET-AGD-IG in FinFET-GD-IG or Figure 15 in Figure 12) be drain electrode.Due to the higher raceway groove series resistance of asymmetric bit line access transistor, the weakened of N3 in the read operation process.Therefore intrinsic data disturb (being caused by the dividing potential drop between N3 and N1) to be reduced significantly by asymmetric bit line access transistor.The new asymmetric bit line access transistor proposed can strengthen the data read stability.
Before a write operation, by the data of importing into, determine that a bit line discharges of the accessed row of memory array is to 0V.Write signal W and Writing/Reading signal WR just initiate a write operation process while becoming Vdd.The interconnected gates pattern is connected and be operated in to the bit line access transistor.Therefore bit line access transistor intensity be enhanced in write operation.If " 0 " on bit line is write to the node that originally is stored as " 1 " _ 1, and bit line access transistor (N3) is 0V by node _ 1 from the Vdd electric discharge with (P1) competition that pulls up transistor.Because write current flows to bit line from the cell data memory node, the end points of the N3 be connected with bit line is (as FinFET-AU-IG in Fig. 5, FinFET-DM-IG in Fig. 7, FinFET-DD-IG in Fig. 9, the left end of FinFET-AGD-IG in FinFET-GD-IG or Figure 15 in Figure 12) be source electrode.Due to the raceway groove series resistance that asymmetric bit line access transistor reduces, the intensity of N3 is enhanced in the write operation process.The asymmetric bit line access transistor that therefore write capability of the new static random-access memory unit proposed is suggested improves.The data read stability of raising standard 6 transistor static random-access memories and write capability require to be solved by this new static random-access memory monotechnics for the contradiction of transistor size.
experimental result
I. read operation data stability
Figure 39 shows the experimental result according to the read operation static noise margin of the FinFET static random access memory cell of an example of the application.Experiment condition is Vdd=0.8V.T=90°C。The left end of FinFET-AU-TG as shown in Figure 4 is connected with the bit line of SRAM-AU-TG as shown in figure 18.The read current that FinFET-AU-TG produces is less than the symmetrical transistor FinFET-UL-TG shown in Fig. 2.The interference of data memory node also reduces because of the bit line access transistor by asymmetric under lap gate design.Therefore strengthened the read operation static noise margin than Standard Symmetric Multivariate SRAM-UL-TG reaches the β ratio that 75%(depends on the static random-access memory unit to SRAM-AU-TG in Figure 18).
II. write operation tolerance limit
Figure 40 shows the experimental result according to the write operation tolerance limit of the FinFET static random access memory cell of an example of the application.Experiment condition is Vdd=0.8V.T=90°C。As shown in figure 40, when remarkable enhancing data read stability, the SRAM-AU-TG in Figure 18 provides the write operation tolerance limit similar to Standard Symmetric Multivariate SRAM-UL-TG.
III. electricity leakage power dissipation
Figure 41 shows the experimental result according to the electricity leakage power dissipation of the FinFET static random access memory cell of an example of the application.Experiment condition is T=90 ° of C.FinFET-AU-TG as shown in Figure 4 produces the leakage current from the device left side to the right lower than the symmetrical transistor FinFET-UL-TG shown in Fig. 2.Therefore SRAM-AU-TG as shown in figure 18 consumes lower electricity leakage power dissipation than Standard Symmetric Multivariate SRAM-UL-TG.As shown in figure 41, the electricity leakage power dissipation of the SRAM-AU-TG in Figure 18 reduces and reaches the β ratio that 5.9%(depends on the static random-access memory unit than Standard Symmetric Multivariate SRAM-UL-TG).
It is above that with reference to accompanying drawing, the exemplary embodiment to the application is described.It should be appreciated by those skilled in the art that above-mentioned embodiment is only the example of lifting for illustrative purposes, rather than be used for being limited.Any modification of doing under all instructions in the application and claim protection range, be equal to replacement etc., all should be included in the claimed scope of the application.

Claims (24)

1. a non-symmetric transistor comprises:
Be positioned at first doped region and the second doped region that is positioned at described transistor the second end of described transistor first end, described the second end is relative with described first end along first direction;
Channel region between described the first doped region and described the second doped region; And
Be arranged at the grid on described channel region,
Wherein, described the first doped region and described the second doped region are doped with first kind impurity, and the On current of described transistor from described first end to described the second end varies in size with the On current from described the second end to described first end.
2. non-symmetric transistor as claimed in claim 1, wherein said grid and described channel region are set to form asymmetrical grid under lap in described channel region both sides, and wherein the grid under lap length near described first end is less than the grid under lap length near described the second end.
3. as the described non-symmetric transistor of aforementioned any one claim, wherein said grid comprises along described first direction first and the second portion that work function is different, described first is near described first end, described second portion is near described the second end, and the gate work-function of described second portion is higher than the gate work-function of described first.
4. as the described non-symmetric transistor of aforementioned any one claim, wherein said the second doped region is also doped with Second Type impurity, thereby formation is doped with the extra doped region of Second Type impurity between described channel region and described the second doped region.
5. non-symmetric transistor as claimed in claim 4, the doping content of wherein said Second Type impurity is less than the doping content of described first kind impurity.
6. non-symmetric transistor as claimed in claim 4, the doping gradient of wherein said Second Type impurity is less than the doping gradient of described first kind impurity.
7. non-symmetric transistor as claimed in claim 4, wherein said first kind impurity is that N-shaped, described Second Type impurity are p-type.
8. non-symmetric transistor as claimed in claim 4, wherein said first kind impurity is that p-type, described Second Type impurity are N-shaped.
9. as the described non-symmetric transistor of aforementioned any one claim, wherein said the second doped region comprises along described first direction the first sub-doped region and the second sub-doped region that doping content is different, the wherein said first sub-doped region is near described grid, and the described second sub-doped region is away from described grid.
10. non-symmetric transistor as claimed in claim 9, the described first sub-doped region doping content of wherein said the second doped region is lower than the described second sub-doped region doping content of described the second doped region.
11. non-symmetric transistor as claimed in claim 9, wherein said the first doped region comprises along described first direction the first sub-doped region and the second sub-doped region that doping content is different, the described first sub-doped region of wherein said the first doped region is near described grid, and the described second sub-doped region of described the first doped region is away from described grid.
12. non-symmetric transistor as claimed in claim 11, the described first sub-doped region doping content of wherein said the first doped region is lower than the described second sub-doped region doping content of described the first doped region, and the described first sub-doped region doping content of described the second doped region is lower than the described second sub-doped region doping content of described the second doped region.
13. non-symmetric transistor as claimed in claim 11, the doped region length of the described first sub-doped region of wherein said the second doped region is greater than the doped region length of the described first sub-doped region of described the first doped region.
14. non-symmetric transistor as described as any one in claim 1-13, wherein said transistor is the FinFET transistor.
15. non-symmetric transistor as described as any one in claim 1-13, wherein said transistor is single gridistor, interconnected type double gate transistor, discrete type double gate transistor, tri-gate transistor or all around gate transistor.
16. a static random-access memory, comprise the first bit line and the second bit line for reading and writing data, and at least one static random-access memory unit, described static random-access memory unit comprises:
Inverter group, be connected between supply network and ground wire;
The first bit line access device, be connected between the first port of described the first bit line and described inverter group, for controlling disconnection between described the first bit line and described the first port and being connected, and
The second bit line accessor part, be connected between the second port of described the second bit line and described inverter group, for controlling disconnection between described the second bit line and described the second port and being connected,
Wherein said the first bit line access device and/or described the second bit line accessor part adopt the described non-symmetric transistor of any one in claim 1-15.
17. static random-access memory as claimed in claim 16, wherein said inverter group comprises the first and second pull-up device and the first and second pull-down, and described pull-up device and pull-down form two cross-linked inverters.
18. static random-access memory as claimed in claim 17, wherein said pull-up device and/or pull-down can adopt single gridistor, interconnected type double gate transistor, discrete type double gate transistor, tri-gate transistor or all around gate transistor.
19. static random-access memory as described as any one in claim 16 to 18, wherein, as described the first bit line access device the time, the described first end of described non-symmetric transistor is connected to described the first bit line, described the second end is connected to described the first port; As described the second bit line accessor part the time, the described first end of described non-symmetric transistor is connected to described the second bit line, described the second end is connected to described the second port.
20. a static random-access memory, comprise the first bit line and the second bit line for reading and writing data, and at least one static random-access memory unit, described static random-access memory unit comprises:
Inverter group, be connected between supply network and ground wire;
The first bit line access device, be connected between the first port of described the first bit line and described inverter group, for controlling disconnection between described the first bit line and described the first port and being connected, and
The second bit line accessor part, be connected between the second port of described the second bit line and described inverter group, for controlling disconnection between described the second bit line and described the second port and being connected,
Wherein said the first bit line access device and/or described the second bit line accessor part adopt the described non-symmetric transistor of any one in claim 1-14, and described the first bit line access device and/or described the second bit line accessor part are discrete type double gate transistor, a grid of described discrete type double gate transistor is controlled by write signal, and another grid is by the Writing/Reading signal controlling simultaneously.
21. static random-access memory as claimed in claim 20, wherein said inverter group comprises the first and second pull-up device and the first and second pull-down, and described pull-up device and pull-down form two cross-linked inverters.
22. static random-access memory as claimed in claim 21, wherein said pull-up device and/or pull-down can adopt single gridistor, interconnected type double gate transistor, discrete type double gate transistor, tri-gate transistor or all around gate transistor.
23. static random-access memory as described as any one in claim 20 to 22, wherein, as described the first bit line access device the time, the described first end of described non-symmetric transistor is connected to described the first bit line, described the second end is connected to described the first port; As described the second bit line accessor part the time, the described first end of described non-symmetric transistor is connected to described the second bit line, described the second end is connected to described the second port.
24. a method of static random-access memory as described as any one in claim 20 to 23 being carried out to read and write access comprises:
When read operation, described write signal with described Writing/Reading signal in contrary logic state, so that gate turn-on of described the first bit line access device and/or described the second bit line accessor part and another grid remain off; And
When write operation, described write signal with described Writing/Reading signal in identical logic state, so that a described grid and the equal conducting of another grid of described the first bit line access device and/or described the second bit line accessor part.
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