CN103000221B - Semiconductor device - Google Patents
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- CN103000221B CN103000221B CN201110274870.4A CN201110274870A CN103000221B CN 103000221 B CN103000221 B CN 103000221B CN 201110274870 A CN201110274870 A CN 201110274870A CN 103000221 B CN103000221 B CN 103000221B
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Abstract
Semiconductor device of the present invention (100) comprising: the N-type transistor (Tn) supplying the power suppling part (110) of the first operation voltage or second operation voltage less than the first operation voltage, receive the P-type crystal pipe (Tp) of the Low threshold of the first operation voltage or the second operation voltage and be connected between transistor (Tp) and reference potential from power suppling part (110), and transistor (Tp, Tn) forms the logical circuit producing output signal (Dout) corresponding to the signal (Din) inputing to grid.First operation voltage, when usual action, is supplied to the source electrode of transistor (Tp) by power suppling part (110), when standby action, the second operation voltage is supplied to the source electrode of transistor (Tp).Second operation voltage is set, makes the amplitude of the voltage between the respective grid of transistor (Tp, Tn) and source electrode be greater than the threshold value of transistor (Tp, Tn).
Description
Technical field
The present invention relates to a kind of semiconductor device comprising logical circuit or logic gate, and in particular to the semiconductor device that power consumption when making standby action reduces.
Background technology
For the semiconductor memory of flash memory (flashmemory), dynamic storage (dynamicmemory) etc., according to the requirement of Large Copacity, low price and low consumption electric power, except realizing except miniaturization, also process will be cut down.Result, such as in the operation of the polysilicon (polysilicon) of individual layer, P channel (channel) metal-oxide semiconductor (MOS) (MetalOxideSemiconductor, MOS) threshold value of transistor (transistor) rises, be difficult to realize high speed motion, therefore, improve, such as the transistor of newly-increased Low threshold.But if reduce threshold value, even if the voltage Vgs then between grid (gate) and source electrode (source) is 0V, so-called leakage current (leakagecurrent) still can flow, and causes electric power to be consumed.Threshold value is less, then described leakage current more can increase.
Patent documentation 1 is between the logic gate and power circuit (line) of the thin Low threshold of grid oxidation film, power switch (switching) transistor of the thin Low threshold of grid oxidation film is set, when standby (standby) state, power switch transistor applies reverse biased consumingly, thus the leakage current of power switch transistor is reduced.
[prior art document]
[patent documentation]
[patent documentation 1] Japanese Patent Laid-Open 2004-147175 publication
Fig. 1 is an example of the existing circuit that leakage current is reduced, and this circuit represents for synchronous data transmission circuit such as the clock (clock) of inputoutput data impact damper (databuffer) etc.Data transmission circuit comprises: clock generation circuit C1, produces internal clock signal InCLK according to external timing signal ExCLK; And output circuit C2, synchronously export data with internal clock signal InCLK.Clock generation circuit C1 comprises: the one CMOS phase inverter (inverter) (P1, the N1) inputted by external timing signal ExCLK; 2nd CMOS phase inverter (P2, N2), is inputted the output of a CMOS phase inverter and is exported by internal clock signal InCLK; Be connected to the P channel MOS transistor Qp between power Vcc and transistor P1; And the N channel transistor Qn be connected between the output of a CMOS phase inverter and GND.Power interruption (powerdown) signal P/D puts on the grid of transistor Qp, Qn, and power failure signal P/D is in L level (level) when usual action, when standby, be in H level.Form the first phase inverter, P channel transistor P1, P2 of the second phase inverter be made up of the transistor of Low threshold.
Output circuit C2 comprises: the 3rd CMOS phase inverter (P3, N3) internal data inputted; 4th CMOS phase inverter (P4, N4), is inputted the output of the 3rd CMOS phase inverter and data is exported; P channel transistor P5, N channel transistor N5, be connected in series in the 3rd CMOS phase inverter respectively; Be connected to the P channel transistor Qp between transistor P5 and power Vcc; And the N channel transistor Qn be connected between the output of the 3rd CMOS phase inverter and GND.The internal clock signal InCLK reversed puts on the grid of transistor P5, and internal clock signal InCLK puts on the grid of transistor N5.Power failure signal P/D puts on the grid of transistor Qp, Qn.Form the 3rd CMOS phase inverter, P channel transistor P3, P4 of the 4th CMOS phase inverter and the transistor P5 of clock synchronous to be made up of the transistor of Low threshold.
When usual action, power failure signal P/D is L level, and therefore, transistor Qp connects, and power Vcc is connected to a CMOS phase inverter and the 3rd CMOS phase inverter, and transistor Qn disconnects.Therefore, synchronous with external timing signal ExCLK internal clock signal InCLK exports from clock generation circuit C1.In addition, in output circuit C2, when the internal clock signal InCLK of transistor P5, N5 is L level, internal data is obtained by the 3rd CMOS phase inverter, and the data of the logical value corresponding with the logical value of input data are exported by the 4th CMOS phase inverter.
If when being transferred to standby, then power failure signal P/D is H level.Therefore, in clock generation circuit C1, transistor Qp disconnects, and operation voltage Vcc is not supplied to the transistor P1 of Low threshold, and in addition, transistor Qn connects, and whereby, the internal clock signal InCLK exported from clock generation circuit C1 is fixed on H level.In addition, in output circuit C2, operation voltage Vcc is not supplied to transistor P3, and transistor Qn connects, and whereby, the data of output export and are fixed on H level.
As mentioned above, in order to cut down the leakage current of transistor P1, the P3 with Low threshold, in series transistor Qp, the Qn with common threshold value must be inserted, and logic setting must be carried out according to power failure signal P/D.Whereby, transistor P1, the P3 with Low threshold can be utilized to realize high speed motion, but then, owing in series transistor Qp, Qn being inserted, therefore, the channel width of transistor P1 and transistor Qp and transistor P3 and transistor Qp increases, and causes to set holding state and logic section is increased.And, when standby, due to export data be fixed on H level, therefore, when from time standby to when shifting during usual action, logic section must be given initialization, therefore need the time.
Summary of the invention
The object of the invention is to the problems referred to above solved in the past, and a kind of semiconductor device comprising the logical circuit of leakage current when reducing standby action is provided.
And, the object of the present invention is to provide a kind of can without sluggishness from during standby action to the semiconductor device shifted during usual action.
Semiconductor device of the present invention comprises: the first MOS transistor of P channel type, at least receives the first operation voltage or second operation voltage less than the first operation voltage, and the second MOS transistor of N channel type, at least be connected between the first MOS transistor and reference potential, first MOS transistor and the second MOS transistor are formed corresponding to inputing to the signal of grid to produce the logical circuit of output signal, when usual action, first operation voltage is supplied to the source electrode of the first MOS transistor, when standby action, second operation voltage is supplied to the source electrode of the first MOS transistor, second operation voltage is set, the amplitude of the voltage between the respective grid of the first MOS transistor and the second MOS transistor and source electrode is made to be greater than the threshold value of the first MOS transistor and the second MOS transistor.
Semiconductor device preferably also comprises selection circuit, and this selection circuit selects the first operation voltage when usual action, selects the second operation voltage when standby action.The control signal that selection circuit is preferably based on from outside selects the first operation voltage or the second operation voltage.Semiconductor device also comprises generation circuit, and this generation circuit from external reception first operation voltage, and produces the second operation voltage according to the first operation voltage.Semiconductor device also comprises generation circuit, and this generation circuit from external reception second operation voltage, and produces the first operation voltage according to the second operation voltage.
Logical circuit comprises: comprise the first inverter circuit of described first MOS transistor and the second MOS transistor and be connected to described first inverter circuit and comprise the second inverter circuit of described first MOS transistor and the second MOS transistor.External timing signal inputs to the first inverter circuit, and internal clock signal is exported by the second inverter circuit.Logical circuit also comprises the circuit synchronously data being given input and output with described internal clock signal.Logical circuit also comprises: supply the power suppling part of the first operation voltage or the second operation voltage, be connected in series the 3rd MOS transistor of the P channel type between power suppling part and the first MOS transistor and be connected in series the 4th MOS transistor of the N channel type between transistor seconds and reference potential, first clock signal inputs to the grid of the 3rd MOS transistor, input to the grid of the 4th MOS transistor to the first clock signal carry out reversing second clock signal of gained, data input to the grid of the first MOS transistor and the second MOS transistor.
Semiconductor device also comprises: be formed in order to the memory cell that data are remembered memory array, be connected to the data output circuit of described memory array, described data output circuit comprises described logical circuit.Be during chip enable signal does not input to semiconductor device from outside during standby action.In addition, during standby action be chip enable signal is inputted after the fixing period of not carrying out command action.
[effect of invention]
According to the present invention, when standby action, second operation voltage lower than the first operation voltage is supplied to the first MOS transistor, therefore, compared with during supply the first operation voltage, the leakage current of the first MOS transistor can be made to reduce.And, second operation voltage is set, the amplitude of the voltage between the respective grid of the first MOS transistor and the second MOS transistor and source electrode is made to be greater than the threshold value of the first MOS transistor and the second MOS transistor, therefore, the logic level of the signal inputing to logical circuit can be maintained, result, when from during standby action to during usual action transfer time, without the need to logical circuit is given initialization, can process rapidly.And, without the need to such as in the past as, the transistor in order to carry out logic setting according to power failure signal is inserted in logical circuit, therefore, the highly integrated of logical circuit and miniaturization can be realized.
For the above and other object of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the figure of the formation representing the existing logical circuit that leakage current is reduced.
Fig. 2 is the figure of the formation of the semiconductor device representing the first example of the present invention.
Fig. 3 is the form of the relation of operation voltage and the operating state representing that voltage supplier supplies.
Fig. 4 (a) ~ Fig. 4 (c) is the figure of the configuration example representing power suppling part.
Fig. 5 (a), Fig. 5 (b) are the figure of the formation of the semiconductor device representing the second example of the present invention.
Fig. 6 is the figure of the formation of the semiconductor device representing the 3rd example of the present invention.
Fig. 7 is the figure of the formation of the semiconductor device representing the 4th example of the present invention.
Fig. 8 (a), Fig. 8 (b) are the figure of the formation of the semiconductor device representing the 5th example of the present invention.
Fig. 9 is the figure of the formation of the semiconductor device representing the 6th example of the present invention.
Figure 10 (a) represents in the logical circuit of Fig. 1, and transistor is not time diagram during Low threshold,
Figure 10 (b) represents in the logical circuit of Fig. 1, and transistor has sequential chart during Low threshold.
Figure 11 is the sequential chart that application has the flash memory of the data output circuit of the 6th example of the present invention.
Figure 12 represents that application has the formation calcspar of the flash memory of the data output circuit of the 6th example of the present invention.
Wherein, description of reference numerals is as follows:
100,100A, 100B, 100C, 100D: semiconductor device
100E: flash memory
110,140: power suppling part
112: outside terminal
120,150: selection circuit
130,130A, 130B: voltage generation circuit
160A: the one CMOS phase inverter
160B: the two CMOS phase inverter
170: logical circuit
180: data output circuit
200: memory array
200L, 200R: memory set
210: inputoutput buffer
220: address register
230: data register
240: controller
250: word line selection circuit
260: page buffer/sensing circuit
270: column select circuit
280: internal voltage generating circuit
Ax: row address information
Ay: column address information
BLK (L) 1, BLK (L) 2, BLK (L) m+1, BLK (R) 1, BLK (R) 2, BLK (R) m+1: block
C1: clock generation circuit
C2: output circuit/data output circuit
CE: chip enable signal
CLK, CLK ': clock signal
CTL: control signal
D1, D2, Da, Db: time delay
Din: input data/data/signal
Dout: export data/output signal
ExCLK: external timing signal
InCLK: internal clock signal
A MOS transistor/CMOS phase inverter of N1:N passage
MOS transistor/the 2nd CMOS phase inverter of N2:N passage
MOS transistor/the 3rd CMOS phase inverter of N3:N passage
MOS transistor/the 4th CMOS phase inverter of N4:N passage
MOS transistor/N channel transistor/the transistor of N5:N passage
OE: output enable signal
P/D: power failure signal
P1: the MOS transistor of a transistor/CMOS phase inverter/P channel transistor/P channel
The MOS transistor of the P2: the two CMOS phase inverter/P channel transistor/P channel
The MOS transistor of the P3: the three CMOS phase inverter/P channel transistor/transistor/P channel
The MOS transistor of the P4: the four CMOS phase inverter/P channel transistor/P channel
The MOS transistor of P5:P channel transistor/transistor/P channel
PWR1, PWR2: power rail
Qn:N channel transistor/transistor
Transistor/P channel MOS transistor/transistor/P channel the transistor of Qp:P channel-style
R: resistance
T1: moment
MOS transistor/N-type transistor/the transistor of Tn:N channel-style
MOS transistor/P-type crystal pipe/transistor/P channel the transistor of Tp:P channel-style
TR:N channel MOS transistor/transistor
V1, V1/V2: operation voltage
V2: operation voltage/voltage
Va, Vb: voltage
Vcc: power supply/operation voltage
Vcc (Ext): external power source
Vcc (Int): internal electric source
Embodiment
Then, come to be described embodiments of the present invention in detail with reference to accompanying drawing.
[example]
Fig. 2 is the figure of the basic comprising of the logical circuit of the semiconductor device representing the first example of the present invention.The semiconductor device 100 of the first example preferably includes formation CMOS logical circuit on a silicon substrate or cmos logic gate, represents that a CMOS phase inverter is as typical example herein.Semiconductor device 100 comprises: the MOS transistor Tp of P channel type, the MOS transistor Tn of N channel type and operation voltage is supplied to the power suppling part 110 of transistor Tp.The transistor Tp of P channel is preferably the low transistor of threshold value, therefore, such as, makes the common thickness of the Film Thickness Ratio of gate insulating film thinner.
Power suppling part 110 corresponds to the operating state of semiconductor device and operation voltage is supplied to CMOS phase inverter.In a preferred example, as shown in the form of Fig. 3, power suppling part 110 is when semiconductor device carries out usual action (Active), internal electric source Vcc (Int) is set to the operation voltage V1 identical with external power source Vcc (Ext), when holding state (Idle), internal electric source Vcc (Int) is set to the operation voltage V2 (V1 > V2) lower than the operation voltage V1 of external power source Vcc (Ext).Power suppling part 110 can comprise the circuit being used as internal electric source Vcc (Int) in order to service voltage V2, such as, can comprise: level shifting circuit, direct current (DirectCurrent, DC)-DC converter (converter).
For the CMOS phase inverter shown in Fig. 2, when semiconductor device carries out usual action, the operation voltage V1 of such as 1.8V is supplied to the source electrode of P channel transistor Tp.Because transistor Tp has Low threshold, therefore, the on-state grow when signal of logic L level is transfused to, and also switch motion now accelerates.
On the other hand, when semiconductor device be holding state or standby mode (mode) time, operation voltage V2 such as 1.3V is supplied to the source electrode of P channel transistor Tp.Now, should be noted that part is: operation voltage V2 is set, make the amplitude of the voltage Vgs between the grid of transistor Tp and source electrode be greater than the threshold value of transistor Tp, Tn.That is, set action voltage V2 is carried out in the mode of the logic state of the H or L level that can maintain the signal inputing to CMOS phase inverter.Because this operation voltage V2 is lower than operation voltage V1, therefore, the switching speed of transistor Tp is than slower during usual action, but leakage current when transistor Tp can be made to disconnect reduces.
When standby action, when the data Din inputing to CMOS phase inverter is logic L level, transistor Tp connects, and transistor Tn disconnects, and exporting data Dout is logic H level.On the other hand, when inputted data Din is logic H level, transistor Tp disconnects, and transistor Tn connects, and exporting data Dout is logic L level.Even if when standby action, semiconductor device 100 also can carry out action under the state that maintain logic level, therefore, when from holding state to usual action transfer, without the need to carrying out the initialization must carried out for logical circuit in the past, can shift from holding state to usual action without delay.Moreover holding state can be the state defined based on the external signal putting on semiconductor device, or also can judge that the internal circuit of semiconductor device is whether as holding state based on described external signal.So-called holding state, such as, can comprise: make the action of semiconductor device stop the form of fixing period, make responsiveness be less than the form of common responsiveness or make power consumption be less than the form of common power consumption.In addition, operation voltage V1, V2 can suitably be selected according to the size of MOS transistor, threshold value and other acting characteristics.
Fig. 4 (a) ~ Fig. 4 (c) is the figure of other examples representing power suppling part 110.In the example shown in Fig. 4 (a), semiconductor device comprises the outside terminal 112 inputted by external power source Vcc (Ext).Power suppling part 110 supply from outside terminal 112 input operation voltage V1 as external power source Vcc (Ext).And, semiconductor device comprises the voltage generation circuit 130 in order to produce operation voltage V2 according to the operation voltage V1 of external power source Vcc (Ext), and this voltage generation circuit 130 supplies operation voltage V2 as internal electric source Vcc (Int).
In addition, in the example shown in Fig. 4 (b), operation voltage V2 is inputted as external power source Vcc (Ext) from outside terminal 112 by semiconductor device.And the operation voltage V2 of voltage generation circuit 130A to outside power Vcc (Ext) boosts, produce operation voltage V1 as internal electric source Vcc (Int).In the example shown in Fig. 4 (c), voltage Va is inputted as external power source Vcc (Ext) from outside terminal 112 by semiconductor device.And voltage generation circuit 130B produces operation voltage V1, the V2 as internal electric source Vcc (Int) according to voltage Va.Beyond described content, operation voltage V1, V2 also can be inputted as external power source Vcc (Ext) from outside terminal by semiconductor device respectively.
Then, with reference to Fig. 5 (a), Fig. 5 (b), the second example of the present invention is described.In the second example, semiconductor device 100A comprises the selection circuit 120 in order to switch the operation voltage V1/V2 of CMOS phase inverter.Selection circuit 120 reception control signal CTL, and according to control signal CTL, operation voltage V1 or operation voltage V2 being supplied to the source electrode of transistor Tp, described control signal CTL represents that semiconductor device is usual action (Active) or holding state (Idle or Standby).That is, selection circuit 120 supplies high operation voltage V1 when usual action, supplies low operation voltage V2 when standby action.
Fig. 5 (b) represents the preference of selection circuit 120.Selection circuit 120 comprises: the power rail PWR2 that supply has power rail (rail) PWR1 of the voltage Vb from external power source or internal electric source, supply operation voltage V1 or operation voltage V2, the N channel MOS transistor TR being connected to the resistance R between power rail PWR1 with power rail PWR2 and being connected in parallel with this resistance R.Control signal CTL is connected to the grid of transistor TR.When usual action, transistor TR responds and conducting to control signal CTL, and operation voltage V1 is supplied to power rail PWR2.On the other hand, when standby action, transistor TR responds and not conducting to control signal CTL, and operation voltage V2 (< V1) is supplied to power rail PWR2.Selection circuit 120 can be formed by very simple formation.
Then, with reference to Fig. 6, the 3rd example of the present invention is described.In the 3rd example, semiconductor device 100B comprises: the power suppling part 140 of supply operation voltage V1 and operation voltage V2; And selection circuit 150, receive the operation voltage V1 from power suppling part 140 and operation voltage V2, and come optionally any one operation voltage V1 or operation voltage V2 to be exported according to control signal CTL.In the same manner as when the first example, power suppling part 140 can comprise the voltage generation circuit producing internal electric source Vcc (Int) based on external power source Vcc (Ext) or external power source.Selection circuit 150 selects operation voltage V1 or operation voltage V2 according to control signal CTL, and selected operation voltage is supplied to the source electrode of transistor Tp, when described control signal CTL represents that semiconductor device 100B is still in standby action when being in usual action.In the case of this example, selection circuit 150 only can select operation voltage V1 or operation voltage V2, in addition, also can share by other circuit the operation voltage V1 and operation voltage V2 that supply from power suppling part 140.
Then, with reference to Fig. 7, the 4th example of the present invention is described.The semiconductor device 100C of the 4th example comprises the typical clock generation circuit producing internal clock signal InCLK according to external timing signal ExCLK.Clock generation circuit comprises: the CMOS phase inverter 160A inputted by external timing signal ExCLK; And the 2nd CMOS phase inverter 160B, the output of a CMOS phase inverter 160A is inputted and exported by internal clock signal InCLK.With the first example in the same manner as during the 3rd example, the power suppling part 110 optionally supplying operation voltage V1 or operation voltage V2 is connected to a CMOS phase inverter 160A and the 2nd CMOS phase inverter 160B.
When usual action, operation voltage V1 is supplied to the transistor Tp of the Low threshold of a CMOS phase inverter 160A and the 2nd CMOS phase inverter 160B, and transistor Tp carries out high speed motion.Whereby, according to external timing signal ExCLK, the internal clock signal InCLK short time delay is exported.On the other hand, when standby action, operation voltage V2 is supplied to the transistor Tp with Low threshold, but owing to setting operation voltage V2, the amplitude of the voltage of external timing signal ExCLK is made to be greater than the threshold value of transistor Tp, therefore, the clock signal InCLK ' of the logic state that maintain external timing signal ExCLK is exported by a CMOS phase inverter 160A.Clock signal clk ' input to the 2nd CMOS phase inverter 160B, but even in this case, owing to setting operation voltage V2, make clock signal clk ' amplitude be greater than the threshold value of transistor Tp, therefore, the 2nd CMOS phase inverter 160B by maintain clock signal clk ' the internal clock signal InCLK of logic state exported.On the other hand, because operation voltage V2 is less than operation voltage V1, therefore, the leakage current of the transistor Tp of Low threshold when can suppress standby action.
Then, with reference to Fig. 8 (a), Fig. 8 (b), the 5th example of the present invention is described.The semiconductor device 100D of the 5th example comprises: power suppling part 110, with the logical circuit 170 optionally supplying operation voltage V1 or operation voltage V2 from power suppling part 110.This logical circuit 170 comprises cmos logic gate, and this cmos logic gate has P channel MOS transistor and the N channel MOS transistor of Low threshold.Logical circuit 170 receive external timing signal ExCLK or internal clock signal InCLK, receive input data Din, and by with clock signal synchronization treated output data Dout is exported.When usual action, operation voltage V1 is supplied to logical circuit 170, and the transistor by Low threshold carries out high speed motion.When standby action, operation voltage V2 is supplied to logical circuit 170, this logical circuit 170 to carry out action than speed slower during usual action, but with clock signal synchronization the data of the logic level that maintain cmos logic gate (gate) are exported.
Fig. 8 (b) represents a circuit example of the logical circuit 170 of the 5th example.Logical circuit 170 comprises: phase inverter, have the transistor Tp of the P channel type of Low threshold, with the transistor Tn of N channel type; Be connected in series the transistor Qp of the P channel type of the Low threshold between transistor Tp and power suppling part 110; And be connected in series the transistor Qn of the N channel type between transistor Tn and ground connection (ground).This input data Din is supplied to the grid of transistor Tp and transistor Tn, and the internal clock signal InCLK reversed is supplied to the grid of transistor Qp, and internal clock signal InCLK is supplied to the grid of transistor Qn.When usual action, operation voltage V1 is supplied to transistor Qp, and logical circuit 170 and internal clock signal synchronously obtain and input data Din, are exported by output data Dout.
When standby action, operation voltage V2 is supplied to transistor Qp, therefore, the leakage current of transistor Qp reduces, on the other hand, owing to setting operation voltage V2, the amplitude of the voltage of internal clock signal is made to be greater than the threshold value of transistor Qp, therefore, when transistor Qp conducting, operation voltage V2 is supplied to the source electrode of transistor Tp, and transistor Tp corresponds to the logic state of input data Din and is switched on or switched off.
Then, with reference to Fig. 9 to Figure 12, the 6th example of the present invention is described.Fig. 9 represents the data output circuit 180 of the 6th example, and data output circuit 180 is such as applicable to the flash memory 100E of the NAND shown in Figure 12.As shown in figure 12, flash memory 100E comprises: memory array (array) 200, has and is arranged in rectangular multiple memory cells (cell); Inputoutput buffer 210, is connected to outside input and output terminal I/O and remains inputoutput data; Receive the address register (addressregister) 220 from the address date (addressdata) of inputoutput buffer 210; Controller (controller) 240, receive from " remain data register (dataregister) 230, this inputoutput buffer 210 of the data of input and output " and order data (commanddata), and based on order, each several part to be controlled; Word line selection circuit 250, decodes (decode) to the row address information Ax from address register 220, selects block (block) and select wordline based on this decoded result; Page buffer (pagebuffer)/sensing circuit (sensecircuit) 260, the data that sensing reads from the paging selected by word line selection circuit 250, or remain the write data writing to selected paging; Column select circuit 270, decodes to the column address information Ay from address register 220, selects bit line based on this decoded result; And internal voltage generating circuit 280, produce data are read, necessary voltage when data being programmed (program) and data are deleted.As described in as described in explanation in example, when internal voltage generating circuit 280 corresponds to usual action or standby action time and supply operation voltage V1, V2.Herein although not shown, but flash memory 100E can receive external timing signal, or carrys out clocking by clock generation circuit.
Outside input and output terminal I/O comprises multiple terminal, described multiple terminal can shared address input terminal, DATA IN terminal, data output terminal and command input end, order latch enable signal, address latch enable signal, chip enable signal, reading enable signal, write enable signal, output enable signal are inputted as external control signal, then ready/busy signal is exported.
Memory array 200 comprises two memory set (memorybank) 200L, the 200R that can access (access) simultaneously.Memory set 200L comprise in a column direction m block BLK (L) 1, BLK (L) 2 ..., BLK (L) m+1, memory set 200R comprise in a column direction m block BLK (R) 1, BLK (R) 2 ..., BLK (R) m+1.Each block of memory set is connected to the bit line BL of n bit, and the NAND unit group (cellunit) being connected in series multiple memory cell is connected to each bit line BL.
Data are transmitted at inputoutput buffer 210 and between address register 220, data register 230 and controller 240.Never the order that illustrated Memory Controller sends, data and address information are supplied to controller 240, address register 220 and data register 230 via inputoutput buffer 210.In addition, when reading, the data read from page buffer/sensing circuit 260 transfer to inputoutput buffer 210 via data register 230.
Controller 240 reads based on the order data received from inputoutput buffer 210, controls the sequence (sequence) of programming or deletion etc.Order data such as comprises: enable signal CLE and output enable signal OE etc. are latched in read-out command, program command, delete command, chip enable signal CE, write enable signal WE, reading enable signal RE, address latch enable signal ALE, order.Such as, controller 240 differentiates address information and write data based on order data, the former is transferred to word line selection circuit 250 or column select circuit 270 via address register 220, the latter is transferred to page buffer/sensing circuit 260 via data register 230.
The upper bit of word line selection circuit 250 to the row address information from address register 220 is decoded, select in two memory set 200L, 200R by each paging in a pair block selecting.Page buffer/sensing circuit 260 is connected to data register 230, according to read write command, the data of reading is transferred to data register 230, or receives the write data of transmission from data register 230.Column select circuit 270 is decoded to the column address information Ay from address register 220, selects based on decoded result the data or the bit line that are held in page buffer/sensing circuit 260.
Data output circuit 180 shown in Fig. 9 is such as applicable to inputoutput buffer 210.Data output circuit 180 comprises: clock generation circuit C1, produces internal clock signal InCLK according to external timing signal ExCLK; And data output circuit C2, data are exported the internal clock synchronization produced with clock generation circuit C1.P1, P2, P3, P4 and P5 are the MOS transistor of the P channel of Low threshold, and N1, N2, N3, N4 and N5 are the MOS transistor of N channel.
Figure 10 (a) is the movement oscillogram of the data output circuit that the threshold value Th1 of transistor P1 ~ P5 is higher, and Figure 10 (b) is the movement oscillogram of the data output circuit of the threshold value Th2 lower (Th2 < Th1) of transistor P1 ~ P5 as shown in Figure 9.Do not have in the data output circuit of Low threshold, from external timing signal ExCLK, producing internal clock signal InCLK through time delay after D1, then producing after D2 through time delay from internal clock signal InCLK and export data Dout.On the other hand, in the data output circuit 180 of transistor P1 ~ P5 comprising Low threshold, in Da time delay (Da < D1), produce internal clock signal InCLK, from this internal clock signal InCLK, in Db time delay (Db < D2), produce data export Dout.
Figure 11 represents the action waveforms when data output circuit 180 shown in Fig. 9 being applied to flash memory 100E.When moment t1, if chip enable signal CE, output enable signal OE (being negative logic (lowactive)) are inputed to flash memory 100E as external control signal, then controller 240 responds to this and makes control signal from representing that the L level of holding state (Standby) is changing into the H level representing usual state (Active).Control signal is supplied to each several part in storer, and the control signal of internal voltage generating circuit 280 couples of Active responds and produces operation voltage V1, and this operation voltage V1 is supplied to data output circuit 180.Herein, internal voltage generating circuit 280 couples of operation voltage V2 boost, and produce the operation voltage V1 as internal electric source Vcc (Int).
The control signal of Active state, during carrying out the process corresponding with order (t1-t2), is exported by controller 240, and during this period, operation voltage V1 is supplied to data output circuit 180.Therefore, data output circuit 180 is synchronous with clock signal clk, produces and export data Dout from clock signal clk after fixing time delay.If control signal switches to standby (Standby) state, then internal voltage generating circuit 280 responds to this and operation voltage V2 is supplied to data output circuit 180.Control signal, when carrying out process at a high speed according to the fixed action sequence of regulation, in period t3-t4, period t5-t6, is switched to Active by controller 240, and during this period, operation voltage V1 is supplied to data output circuit 180.When control signal is Standby state (period t2-t3, period t4-t5 and period t6-t7), operation voltage V2 is supplied to data output circuit 180, but because clock generation circuit C1 maintains the logic state of clock signal clk, therefore, even if control signal switches to Active state from Standby state, also without the need to data output circuit is given initialization, thus the delay exporting data Dout can be suppressed.
Logical circuit illustrated in described example is an example, the cmos logic gate beyond described in the present invention is also applicable to or CMOS logical circuit.And, the present invention is except being applicable to flash memory, also be applicable to dynamic RAM (DynamicRandomAccessMemory, DRAM), static RAM (StaticRandomAccessMemory, SRAM), the various semiconductor devices of microcontroller (microcontroller), microprocessor (microprocessor) and application-specific IC (ApplicationSpecificIntegratedCircuit, ASIC) etc.
The preferred embodiment of the present invention is described in detail, but the present invention is not limited to specific embodiment, in the scope of the aim of the present invention disclosed at claims, can various distortion, change be carried out.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention, anyly have the knack of this those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on accompanying those as defined in claim.
Claims (12)
1. a semiconductor device, is characterized in that, comprising:
First MOS transistor of P channel type, at least receives the first operation voltage or second operation voltage less than described first operation voltage; And
Second MOS transistor of N channel type, is at least connected between described first MOS transistor and reference potential,
Described first MOS transistor and described second MOS transistor are formed corresponding to inputing to the signal of grid to produce the logical circuit of output signal,
When usual action, described first operation voltage is supplied to the source electrode of described first MOS transistor,
When standby action, described second operation voltage is supplied to the source electrode of described first MOS transistor, described second operation voltage is set, makes the amplitude of the voltage between the respective grid of described first MOS transistor and described second MOS transistor and source electrode be greater than the threshold value of described first MOS transistor and described second MOS transistor.
2. semiconductor device according to claim 1, is characterized in that, described semiconductor device also comprises selection circuit, and this selection circuit selects described first operation voltage when usual action, selects described second operation voltage when standby action.
3. semiconductor device according to claim 2, is characterized in that, described selection circuit selects described first operation voltage or described second operation voltage based on the control signal from outside.
4. semiconductor device according to any one of claim 1 to 3, it is characterized in that, described semiconductor device also comprises generation circuit, and this generation circuit from the first operation voltage described in external reception, and produces described second operation voltage according to described first operation voltage.
5. semiconductor device according to any one of claim 1 to 3, it is characterized in that, described semiconductor device also comprises generation circuit, and this generation circuit from the second operation voltage described in external reception, and produces described first operation voltage according to described second operation voltage.
6. semiconductor device according to claim 1, it is characterized in that, described logical circuit comprises: comprise the first inverter circuit of described first MOS transistor and the second MOS transistor, be connected to described first inverter circuit and comprise the second inverter circuit of described first MOS transistor and the second MOS transistor, external timing signal inputs to described first inverter circuit, and internal clock signal is exported by described second inverter circuit.
7. semiconductor device according to claim 6, is characterized in that, described logical circuit also comprises the circuit synchronously data being given input and output with described internal clock signal.
8. semiconductor device according to claim 1, it is characterized in that, described logical circuit also comprises: supply the power suppling part of described first operation voltage or the second operation voltage, be connected in series the 3rd MOS transistor of the P channel type between described power suppling part and described first MOS transistor and be connected in series the 4th MOS transistor of the N channel type between described second MOS transistor and reference potential;
First clock signal inputs to the grid of described 3rd MOS transistor, inputs to the grid of described 4th MOS transistor to described first clock signal carry out the reversing second clock signal of gained,
Data input to the grid of described first MOS transistor and the second MOS transistor.
9. semiconductor device according to claim 1, it is characterized in that, described semiconductor device also comprises: be formed in order to the memory cell that data are remembered memory array, be connected to the data output circuit of described memory array, described data output circuit comprises described logical circuit.
10. semiconductor device according to claim 1, is characterized in that, is during chip enable signal does not input to described semiconductor device from outside during described standby action.
11. semiconductor devices according to claim 1, is characterized in that, during described standby action be chip enable signal is inputted after the fixing period of not carrying out command action.
12. semiconductor devices according to claim 11, is characterized in that, described semiconductor device is flash memory.
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| CN104104378B (en) * | 2013-04-10 | 2018-11-13 | 联华电子股份有限公司 | output buffer |
| CN106160728B (en) * | 2015-03-30 | 2019-03-19 | 华邦电子股份有限公司 | Output circuit |
| CN105702280B (en) * | 2016-01-15 | 2018-08-21 | 西安紫光国芯半导体有限公司 | A kind of circuit and method reducing quiescent dissipation under DRAM energy-saving modes |
| JP6796681B2 (en) * | 2019-05-13 | 2020-12-09 | ウィンボンド エレクトロニクス コーポレーション | Semiconductor storage device |
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| EP0739097A2 (en) * | 1995-04-21 | 1996-10-23 | Nippon Telegraph And Telephone Corporation | MOSFET circuit and CMOS logic circuit using the same |
| CN101114526A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| DE102007059547A1 (en) * | 2006-12-15 | 2008-06-19 | Qimonda North America Corp. | A circuit and method for suppressing a gate-induced drain leakage current |
| CN101714402A (en) * | 2008-10-08 | 2010-05-26 | 南亚科技股份有限公司 | Method for reducing leakage current of a memory and related device |
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| EP0739097A2 (en) * | 1995-04-21 | 1996-10-23 | Nippon Telegraph And Telephone Corporation | MOSFET circuit and CMOS logic circuit using the same |
| CN101114526A (en) * | 2006-07-28 | 2008-01-30 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| DE102007059547A1 (en) * | 2006-12-15 | 2008-06-19 | Qimonda North America Corp. | A circuit and method for suppressing a gate-induced drain leakage current |
| CN101714402A (en) * | 2008-10-08 | 2010-05-26 | 南亚科技股份有限公司 | Method for reducing leakage current of a memory and related device |
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