CN109961810B

CN109961810B - Word line driving circuit of ROM memory array and ROM memory

Info

Publication number: CN109961810B
Application number: CN201711407353.3A
Authority: CN
Inventors: 于跃; 郑坚斌
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2017-12-22
Filing date: 2017-12-22
Publication date: 2021-07-23
Anticipated expiration: 2037-12-22
Also published as: CN109961810A

Abstract

The invention provides a word line driving circuit of a ROM memory array and a ROM memory. The drive circuit includes: the word line selection circuit generates a word line selection signal according to an input signal, and the voltage conversion circuit outputs a first voltage or a second voltage according to the word line selection signal, wherein the first voltage is higher than a power supply voltage, and the second voltage is lower than a ground voltage. The invention can improve the array density of the ROM memory without changing the size of each ROM memory cell in the ROM memory array.

Description

Word line driving circuit of ROM memory array and ROM memory

Technical Field

The invention relates to the technical field of ROM memories, in particular to a word line driving circuit of a ROM memory array and a ROM memory.

Background

In the design of ROM memories, it is desirable to reduce the area of the ROM memory as much as possible. The ROM memory array is formed of ROM memory cells, the area of the ROM memory array directly affects the area of the ROM memory, and increasing the array density is an effective method for reducing the area of the ROM memory. With the increase in array density, the number of arrays is reduced for large capacity ROM memories, with a concomitant reduction in the number of peripheral circuits and a reduction in the area of the peripheral circuits.

For a ROM memory array, the maximum number of word lines determines the array density with a certain number of bit lines, and depends on the memory cell switching current ratio and the read margin ratio. The memory cell switching current ratio is a ratio of an on current that can flow when the memory cell is turned on to a leakage current when the memory cell is turned off, and the ratio indicates how many memory cells can have a total leakage current equal to the on current of one memory cell. In consideration of the existence of leakage current, when reading the information of the memory cell, no matter reading '0' or reading '1', the bit line is pulled down by the current. We define the conduction current of a memory cell connected to a bit line as a read "0" current, the memory cell not connected to a bit line, and the leakage current of other un-turned on cells on the same bit line as a read "1" current. To ensure that the reading is correct and there is enough margin, we require that the difference between the read "0" current and the read "1" current must be greater than a certain ratio, which is called the read margin ratio. It is generally required that the read "0" current is more than 10 times the read "1" current, i.e., the read margin ratio is 10 or more.

In general, the read margin ratio is a definite value in terms of read correctness, and thus to change the maximum number of word lines, only the memory cell switch current ratio can be changed. By increasing the channel length of the ROM memory unit, the switching current ratio of the memory unit can be increased, the maximum word line number is increased, and the array density is improved.

However, in practice, increasing the channel length of the ROM memory cell increases the area of the memory cell, which increases the area of the array, and the increase in the area of the array may not only decrease the area of the ROM memory but also increase the area of the ROM memory, compared to the decrease in the area of the peripheral circuit caused by the increase in the density of the array. The existing methods do not guarantee a reduction of the area of the ROM memory.

Disclosure of Invention

The invention provides a word line driving circuit of a ROM memory array and a ROM memory, which can improve the array density of the ROM memory without changing the size of each ROM memory cell in the ROM memory array, thereby reducing the area of the ROM memory.

In a first aspect, the present invention provides a word line driver circuit adapted to drive a word line of a ROM memory array, comprising:

a word line selection circuit for generating a word line selection signal based on an input signal;

and a voltage conversion circuit outputting a first voltage higher than a power supply voltage or a second voltage lower than a ground voltage according to the word line selection signal.

Optionally, when the word line selection signal indicates that the current word line is selected, the voltage conversion circuit outputs the first voltage; when the word line selection signal indicates that the current word line is not selected, the voltage conversion circuit outputs the second voltage.

Optionally, the circuit further comprises:

and the buffer is powered by using the first voltage and the second voltage and buffers the first voltage or the second voltage output by the voltage conversion circuit so as to enhance the driving capability of the word line driving circuit.

In a second aspect, the present invention provides a ROM memory comprising: the circuit comprises a ROM storage array, wherein each word line in the ROM storage array is driven by a respective word line driving circuit, and the word line driving circuit adopts the circuit structure.

Optionally, the ROM memory further comprises: a boost circuit that generates the first voltage from the power supply voltage.

Optionally, the ROM memory further comprises: a voltage reduction circuit that generates the second voltage according to the ground voltage.

The word line driving circuit and the ROM provided by the invention do not change the size of the memory cell any more, but improve the word line driving circuit, improve the voltage of the selected word line, increase the conduction current of the selected memory cell, reduce the voltage of the unselected word line and reduce the leakage current of the unselected memory cell during data reading, thereby increasing the switch current ratio of the memory cell, increasing the maximum word line number of the memory array, finally improving the array density and reducing the area of the ROM, and the invention is particularly suitable for designing a large-capacity ROM. Meanwhile, as the conduction current of the memory cell is increased, the data reading speed is faster under the condition that the loads of the bit lines are the same.

Drawings

FIG. 1 is a schematic diagram of a wordline driver circuit according to an embodiment of the invention;

fig. 2 is a schematic circuit diagram of a voltage converting circuit according to an embodiment of the invention;

FIG. 3 is a block diagram of a ROM according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

An embodiment of the present invention provides a word line driving circuit, which is suitable for driving one word line of a ROM memory array, and as shown in fig. 1, the circuit includes a word line selection circuit 11 and a voltage conversion circuit 12.

The word line selection circuit 11 generates a word line selection signal Select _ net according to an input signal IN _ sinnal, and the word line selection circuit 11 is powered by VDD and VSS, where VDD represents a power supply voltage and VSS represents a ground voltage, which are intrinsic parameters of the ROM memory design.

The voltage converting circuit 12 outputs a first voltage VP or a second voltage VN according to the word line selection signal Select _ net, wherein the first voltage VP is higher than the power supply voltage VDD, and the second voltage VN is lower than the ground voltage VSS. VP and VN can be provided directly from an external power supply or can be obtained from VDD and VSS by designing the associated circuitry inside the ROM.

When the wordline Select signal Select _ net indicates that the current wordline is selected, the voltage conversion circuit 12 outputs the first voltage VP; when the word line selection signal Select _ net indicates that the current word line is not selected, the voltage conversion circuit 12 outputs the second voltage VN.

In order to enhance the driving capability of the circuit, a buffer 13 is added, the buffer 13 is powered by the first voltage VP and the second voltage VN, and the output signal of the voltage conversion circuit 12 is transmitted to the word line through the buffer 13.

Specifically, a specific circuit of the voltage conversion circuit 12 is shown in fig. 2. The voltage conversion circuit 12 includes two stages of sub-circuits, the first stage of sub-circuit inputs the word line selection signal Select _ net, outputs the first voltage VP or the ground voltage VSS, and outputs the first voltage VP or the ground voltage VSS as internal _ net; the second-stage sub-circuit inputs internal _ net and outputs a first voltage VP or a second voltage VN.

The first-stage sub-circuit comprises 4P-type MOS transistors PM 11-PM 14, 2N-type MOS transistors NM15 and NM16 and a first inverter Inv1, Inv1 is powered by VDD and VSS, a Select _ net is connected to a grid of PM13 and a grid of NM15 and is connected to a grid of NM16 and a grid of PM14 after being inverted by the inverter Inv1, a source of PM11 and a source of PM12 are connected with a first voltage VP, a drain of PM11 is connected with a source of PM13, a drain of PM13 is connected with a drain of NM15, and a source of NM15 is grounded to VSS; the drain of PM12 is connected to the source of PM14, the drain of PM14 is connected to the drain of NM16, the source of NM16 is grounded VSS, the gate of PM12 is connected to the drain of PM13, the gate of PM11 is connected to the drain of PM14, and the connection outputs the signal internal _ net. When the input level of Select _ net is VSS, the level of internal _ net is VSS, and when the input level of Select _ net is VDD, the level of internal _ net is the first voltage VP.

The second-stage sub-circuit comprises 2P-type MOS tubes PM21 and PM22, 4N-type MOS tubes NM 23-NM 26 and a second inverter Inv2, Inv2 which are powered by a first voltage VP and a ground voltage VSS, internal _ net is connected to the gate of PM21 and the gate of NM23 and is inverted by an inverter Inv2 and then input to the gate of PM22 and the gate of NM24, the source of PM21 and the source of PM22 are connected to the first voltage VP, the drain of PM21 and the drain of NM23, the source of NM23 and NM25 are connected, the source of NM25 and PM22 are connected to the drain of NM24, the source of NM24 and NM26, the source of NM26 and NM26 and PM21, the gate of NM25 and the drain of NM 22, and the second inverter Inv2 and the output signal. When the level of the internal _ net is VSS, the output out is the second voltage VN, and when the level of the internal _ net is VP, the output out is the first voltage VP.

Because the word line is connected with the grid end of the ROM storage unit, the ROM storage unit is an N-MOSFET, according to the characteristics of the N-MOSFET, when the ROM storage unit is switched off, the grid end voltage is lower, the leakage current is smaller, and when the ROM storage unit is switched on, the grid end voltage is higher, and the conduction current is larger. Therefore, the word line driving circuit provided by the embodiment of the invention reduces the voltage of unselected word lines, reduces the leakage current of unselected memory cells, improves the voltage of the selected word line during reading, and increases the conduction current of the selected memory cell, thereby increasing the on-off current ratio of the memory cells, further increasing the maximum word line number of the ROM memory array, and improving the array density. The present invention does not increase the size of the memory cell, and therefore, the present invention can reduce the area of the final ROM memory compared to the prior art. Meanwhile, as the conduction current of the memory cell is increased, the data reading speed is faster under the condition that the loads of the bit lines are the same.

The embodiment of the present invention further provides a ROM memory, which includes a ROM memory array, wherein each word line in the array is driven by a respective word line driving circuit, and the word line driving circuit adopts the circuit structure shown in fig. 1 in the foregoing embodiment. The first voltage VP and the second voltage VN required by all the word line driving circuits may be supplied from an external power supply, or may be supplied from a voltage boosting circuit and a voltage dropping circuit, respectively, which are designed in the ROM.

As shown in fig. 3, taking 4 word lines as an example, each word line corresponds to a respective word line driving circuit, each word line driving circuit is only marked with the first voltage VP and the second voltage VN, and other signals are not marked, which can be referred to fig. 1 specifically.

A boost circuit 31 and a buck circuit 32 are added in the ROM, first voltage VP required by all the word line driving circuits is provided by the boost circuit 31, and the boost circuit 31 boosts power supply voltage VDD to obtain VP; the second voltage VN required by all the word line driving circuits is provided by the voltage-decreasing circuit 32, and the voltage-decreasing circuit 32 decreases the ground voltage VSS to obtain VN.

According to the ROM provided by the embodiment of the invention, the voltage of unselected word lines is reduced, and the voltage of the selected word line during reading is improved, so that the switching current ratio of the storage unit can be increased, the maximum word line number of the ROM storage array is increased, and the array density is improved.

For example, if the selected word line voltage is VDD and the unselected word line voltage is VSS, the on-current of the memory cell is 200uA, the leakage current is 100nA, and the switching current ratio is 200uA/100nA to 2000, i.e., the leakage current of 2000 memory cells may be equivalent to the on-current of one memory cell. In order to ensure that data can be read correctly, the read margin ratio is 10, and the maximum number of memory cells that can be connected to one bit line, i.e. the maximum word line number, is: 200uA/10/100nA is 200.

In the ROM memory of the present invention, assuming that the voltage of the selected word line is VDD +300mV, which causes the conduction current of the memory cell connected to the selected word line to change from 200uA to 300uA, and the voltage of the unselected word line is VSS-200mV, which causes the leakage current of the memory cell connected to the unselected word line to change from 100nA to 50nA, the maximum number of word lines is: 300uA/10/50nA is 600. Therefore, the invention increases the maximum word line number of the memory array without changing the size of the memory unit, and improves the array density.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A wordline driver circuit adapted to drive a wordline of a ROM memory array, comprising:

a word line selection circuit that is supplied with power using a power supply voltage and a ground voltage, and generates a word line selection signal according to an input signal, the word line selection signal indicating whether a current word line is selected;

a voltage conversion circuit that is powered using a first voltage higher than a power supply voltage and a second voltage lower than a ground voltage, and outputs the first voltage or the second voltage according to the word line selection signal;

wherein the voltage conversion circuit comprises a first-stage sub-circuit and a second-stage sub-circuit, the first-stage sub-circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube and a first phase inverter, the first phase inverter is powered by power supply voltage and ground voltage, the grid electrode of the third PMOS tube, the grid electrode of the first NMOS tube and the input end of the first phase inverter are connected at one point and used as the input end of the first-stage sub-circuit, the grid electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube and the output end of the first phase inverter are connected at one point, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the first voltage, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the ground voltage, the drain electrode of the first PMOS tube is connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the first NMOS tube and the gate electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the source electrode of the fourth PMOS tube, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the second NMOS tube and the grid electrode of the first PMOS tube at one point and is used as the output end of the first-stage sub-circuit;

the second-stage sub-circuit comprises a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a second phase inverter, the second phase inverter is powered by a first voltage and a ground voltage, a grid electrode of the fifth PMOS tube, a grid electrode of the third NMOS tube and an input end of the second phase inverter are connected to one point and used as an input end of the second-stage sub-circuit, a grid electrode of the sixth PMOS tube, a grid electrode of the fourth NMOS tube and an output end of the second phase inverter are connected to one point, a source electrode of the fifth PMOS tube and a source electrode of the sixth PMOS tube are connected to the first voltage, a source electrode of the fifth NMOS tube and a source electrode of the sixth NMOS tube are connected to the second voltage, a source electrode of the third NMOS tube is connected to a drain electrode of the fifth NMOS tube, a drain electrode of the fifth PMOS tube, a drain electrode of the third NMOS tube and a grid electrode of the sixth NMOS tube are connected to one point, a source electrode of the fourth NMOS tube and a drain electrode of the sixth NMOS tube are connected to one point, and serves as an output terminal of the second stage sub-circuit.

2. The word line driver circuit of claim 1, wherein the voltage conversion circuit outputs the first voltage when the word line select signal indicates that a current word line is selected; when the word line selection signal indicates that the current word line is not selected, the voltage conversion circuit outputs the second voltage.

3. The word line driver circuit of claim 1, further comprising:

4. A ROM memory comprising a ROM memory array in which each wordline is driven by a respective wordline driver circuit, the wordline driver circuit comprising:

5. The ROM memory according to claim 4, wherein the voltage conversion circuit outputs the first voltage when the word line selection signal indicates that a current word line is selected; when the word line selection signal indicates that the current word line is not selected, the voltage conversion circuit outputs the second voltage.

6. The ROM memory of claim 4, wherein the wordline driver circuit further comprises:

7. The ROM memory according to any of claims 4 to 6, further comprising: a boost circuit that generates the first voltage from the power supply voltage.

8. The ROM memory according to any of claims 4 to 6, further comprising: a voltage reduction circuit that generates the second voltage according to the ground voltage.