CN109961810A - The word line driving circuit and ROM memory of ROM storage array - Google Patents
The word line driving circuit and ROM memory of ROM storage array Download PDFInfo
- Publication number
- CN109961810A CN109961810A CN201711407353.3A CN201711407353A CN109961810A CN 109961810 A CN109961810 A CN 109961810A CN 201711407353 A CN201711407353 A CN 201711407353A CN 109961810 A CN109961810 A CN 109961810A
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- China
- Prior art keywords
- voltage
- word line
- circuit
- rom
- line selection
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
Abstract
The present invention provides the word line driving circuit and ROM memory of a kind of ROM storage array.The driving circuit includes: the word line selection circuit that word line selection signal is generated according to input signal, the voltage conversion circuit of first voltage or second voltage is exported according to the word line selection signal, wherein first voltage is higher than supply voltage, and second voltage is lower than ground voltage.The present invention can improve the array density of ROM memory in not changing ROM storage array in the case where each ROM bit cell size.
Description
Technical field
The present invention relates to the word line driving circuit of ROM memory technical field more particularly to a kind of ROM storage array and
ROM memory.
Background technique
In the design process of ROM memory, it is desirable to reduce the area of ROM memory as far as possible.ROM storage array by
ROM bit cell is formed, and the area of ROM storage array directly affects the area of ROM memory, and improving array density is to reduce
The effective ways of ROM memory area.With the raising of array density, for large capacity ROM memory, array quantity subtracts
Few, peripheral circuit quantity is reduced therewith, and the area of peripheral circuit is reduced.
For a ROM storage array, in the case where number of bit determines, maximum wordline number determines array
Density, and maximum wordline number depends on storage unit switching current ratio and read margin ratio.Storage unit switching current
Ratio refers to the ratio of the storage unit conducting electric current that can flow through and storage unit leakage current when off when opening, the ratio
Value illustrates that the leakage current summation of how many a storage units can be equivalent to the conducting electric current of a storage unit.In view of electric leakage
The presence of stream, when reading location information, either reading " 0 " or reading " 1 ", bit line can all be pulled down by electric current.We are fixed
Adopted storage unit is connected to the conducting electric current on bit line to read " 0 " electric current, and storage unit is not connected on bit line, same position
The leakage current of other non-opening units is to read " 1 " electric current on line.It is correct in order to guarantee to read, and have enough nargin, Wo Menyao
Reading " 0 " electric current and the gap read between " 1 " electric current is asked to have to be larger than some ratio, this ratio is referred to as read margin ratio
Value.Usually require that reading " 0 " electric current is 10 times or more for reading " 1 " electric current, i.e. read margin ratio is more than or equal to 10.
Under normal conditions, read margin ratio relation is a determining numerical value, therefore to change most to correctness is read
Big wordline number, then can only change storage unit switching current ratio.It, can be with by increasing the channel length of ROM bit cell
Increase storage unit switching current ratio, and then increase maximum wordline number, improves array density.
But in real process, increase the channel length of ROM bit cell, will increase the area of storage unit, to make
At the increase of array area, and the increase of array area improves the reduction phase of generated peripheral circuit area with array density
Than sometimes reducing not only the area of ROM memory, increasing the area of ROM memory instead.Therefore existing method without
Method guarantees to reduce the area of ROM memory.
Summary of the invention
The word line driving circuit and ROM memory of ROM storage array provided by the invention can not change ROM storage
In array in the case where each ROM bit cell size, the array density of ROM memory is improved, to reduce the face of ROM memory
Product.
In a first aspect, the present invention provides a kind of word line driving circuit, suitable for driving a wordline of ROM storage array,
Include:
Word line selection circuit generates word line selection signal according to input signal；
Voltage conversion circuit exports first voltage or second voltage, first electricity according to the word line selection signal
Pressure is higher than supply voltage, and the second voltage is lower than ground voltage.
Optionally, when word line selection signal instruction wordline current is selected, the voltage conversion circuit exports institute
State first voltage；When word line selection signal instruction wordline current is not selected, described in the voltage conversion circuit output
Second voltage.
Optionally, the circuit further include:
Buffer, the buffer are powered using the first voltage and the second voltage, convert electricity to the voltage
The first voltage or second voltage of road output are buffered, to enhance the driving capability of the word line driving circuit.
Second aspect, the present invention provide a kind of ROM memory, comprising: ROM storage array, in the ROM storage array
Every wordline is all driven by respective word line driving circuit, and the word line driving circuit uses above-mentioned circuit structure.
Optionally, the ROM memory further include: booster circuit, the booster circuit are generated according to the supply voltage
The first voltage.
Optionally, the ROM memory further include: reduction voltage circuit, the reduction voltage circuit generate institute according to the ground voltage
State second voltage.
Word line driving circuit and ROM memory provided by the invention no longer go the size for changing storage unit, but go to change
Into word line driving circuit, in reading data, the voltage of selected wordline is improved, the electric conduction for choosing storage unit is increased
Stream, and the voltage of not selected wordline is reduced, the leakage current of unselected storage unit is reduced, to increase storage unit switch
Current ratio, can increase the maximum wordline number of storage array, and finally improve array density, reduce the face of ROM memory
Product is particularly suitable for design large capacity ROM memory.Simultaneously as the conducting electric current of storage unit increases, in bit-line load phase
With in the case where, data reading speed is faster.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the word line driving circuit of one embodiment of the invention；
Fig. 2 is the electrical block diagram of the voltage conversion circuit of one embodiment of the invention；
Fig. 3 is the structural schematic diagram of the ROM memory of one embodiment of the invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
It is only a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
The embodiment of the present invention provides a kind of word line driving circuit, suitable for driving a wordline of ROM storage array, such as schemes
Shown in 1, the circuit includes word line selection circuit 11 and voltage conversion circuit 12.
Wherein, word line selection circuit 11 generates word line selection signal Select_net, word according to input signal IN_sinnal
Line options circuit 11 is powered using VDD, VSS, and it is all that ROM memory is set that wherein VDD, which indicates that supply voltage, VSS indicate ground voltage,
The intrinsic parameter of meter.
Wherein, voltage conversion circuit 12 exports the electricity of first voltage VP or second according to word line selection signal Select_net
VN is pressed, wherein first voltage VP is higher than supply voltage VDD, and second voltage VN is lower than ground voltage VSS.VP and VN can be by external electrical
Source directly provides, and can also be obtained in ROM interior design interlock circuit according to VDD and VSS.
When word line selection signal Select_net instruction wordline current is selected, first electricity of the output of voltage conversion circuit 12
Press VP；When word line selection signal Select_net instruction wordline current is not selected, second electricity of the output of voltage conversion circuit 12
Press VN.
In order to enhance the driving capability of circuit, increase buffer 13, buffer 13 passes through first voltage VP and second voltage
VN power supply, the output signal of voltage conversion circuit 12 are transferred in wordline through buffer 13.
Specifically, the physical circuit of voltage conversion circuit 12 is as shown in Figure 2.Voltage conversion circuit 12 includes two-stage son electricity
Road, first order sub-circuit input word line selection signal Select_net, export first voltage VP or ground voltage VSS, output note
For internal_net；Second level sub-circuit inputs internal_net, exports first voltage VP or second voltage VN.
First order sub-circuit includes 4 p-type metal-oxide-semiconductor PM11~PM14,2 N-type metal-oxide-semiconductor NM15 and NM16 and first anti-
Phase device Inv1, Inv1 are powered by VDD and VSS, and Select_net accesses the grid of PM13 and the grid of NM15, and by anti-
The grid of NM16 and the grid of PM14 are accessed after phase device Inv1 reverse phase, the source electrode of PM11 connects first voltage with the source electrode of PM12
The drain electrode of VP, PM11 are connect with the source electrode of PM13, and the drain electrode of PM13 is connect with the drain electrode of NM15, the source electrode ground voltage of NM15
VSS；The drain electrode of PM12 is connect with the source electrode of PM14, and the drain electrode of PM14 is connect with the drain electrode of NM16, the source electrode ground voltage of NM16
The drain electrode of the grid and PM13 of VSS, PM12 connects, and the drain electrode of the grid and PM14 of PM11 connects, the connecting pin output signal
internal_net.When the incoming level of Select_net is VSS, then the level of internal_net is VSS, when
When the incoming level of Select_net is VDD, then the level of internal_net is first voltage VP.
Second level sub-circuit is anti-including 2 p-type metal-oxide-semiconductors PM21 and PM22,4 N-type metal-oxide-semiconductor NM23~NM26 and second
Phase device Inv2, Inv2 are powered by first voltage VP and ground voltage VSS, and internal_net accesses the grid and NM23 of PM21
Grid, and input after phase inverter Inv2 reverse phase the grid of PM22 and the grid of NM24, the source electrode of PM21 and the source of PM22
Pole connects first voltage VP, and the drain electrode of PM21 is connect with the drain electrode of NM23, and the drain electrode of the source electrode and NM25 of NM23 connects, NM25's
Source electrode connects second voltage VN, and the drain electrode of PM22 is connect with the drain electrode of NM24, and the drain electrode of the source electrode and NM26 of NM24 connects, NM26
Source electrode connect second voltage VN, the drain electrode of the grid of NM26 and PM21 connect, and the drain electrode of the grid and PM22 of NM25 connects, should
Connecting pin output signal out.When internal_net level is VSS, output out is second voltage VN, works as internal_net
Level is VP, and output out is first voltage VP.
Since wordline is connected to the grid end of ROM bit cell, ROM bit cell N-MOSFET, according to N-MOSFET's
Characteristic, when shutdown, grid end voltage is lower, and leakage current is smaller, and when opening, grid end voltage is higher, and conducting electric current is bigger.Therefore,
Word line driving circuit provided in an embodiment of the present invention reduces the voltage of unselected word line, and it is single to also reduce unselected storage
The leakage current of member, the voltage of selected word line when improving reading also just increase the conducting electric current for choosing storage unit, therefore increase
Big storage unit switching current ratio, and then the maximum wordline number of ROM storage array is increased, improve array density.
But the present invention not will increase the size of storage unit, therefore, compared with prior art, the present invention can reduce final ROM
The area of memory.Simultaneously as the conducting electric current of storage unit increases, and in the identical situation of bit-line load, reading data
Speed is faster.
The embodiment of the present invention also provides a kind of ROM memory, including ROM storage array, each wordline in array all by
Respective word line driving circuit is driven, and word line driving circuit is using circuit structure as shown in Figure 1 in above-described embodiment.Institute
The first voltage VP and second voltage VN for having word line driving circuit to need can be provided by external power supply, can also be by designing
Booster circuit and reduction voltage circuit in ROM provide respectively.
As shown in figure 3, every wordline corresponds to respective word line driving circuit, each word line driving circuit by taking 4 wordline as an example
First voltage VP and second voltage VN are only denoted, other signals do not indicate, specifically can refer to Fig. 1.
Increase booster circuit 31 and reduction voltage circuit 32 inside ROM memory, the first of all word line driving circuits needs
Voltage VP is provided by booster circuit 31, and booster circuit 31 boosts to supply voltage VDD, obtains VP；All wordline drivings
The second voltage VN that circuit needs is provided by reduction voltage circuit 32, and 32 voltage-to-ground VSS of reduction voltage circuit is depressured, and VN is obtained.
ROM memory provided in an embodiment of the present invention is chosen when by reducing the voltage of unselected word line, and improve reading
The voltage of wordline is capable of increasing storage unit switching current ratio, and then increases the maximum wordline number of ROM storage array,
Improve array density.
For example, it is assumed that selected word line voltage is VDD, when unselected word line voltage is VSS, the conducting electric current of storage unit is
200uA, leakage current 100nA, switching current ratio are 200uA/100nA=2000, i.e., the leakage current of 2000 storage units
The conducting electric current of a storage unit can be equivalent to.In order to guarantee that data can correctly be read, read margin ratio is 10, this
When one bit line on the maximum number of storage unit that can connect, i.e., maximum wordline number are as follows: 200uA/10/100nA=
200。
ROM memory of the invention, it is assumed that the voltage of selected word line is VDD+300mV, causes to connect with selected word line
The conducting electric current of storage unit becomes 300uA from 200uA, and the voltage of unselected word line is VSS-200mV, causes and unselected word
The leakage current of the storage unit of line connection becomes 50nA from 100nA, then maximum wordline number are as follows: 300uA/10/50nA=600.
It can be seen that the size that the present invention is not necessarily to change storage unit just increases the maximum wordline number of storage array, battle array is improved
Column density.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by those familiar with the art, all answers
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (8)
1. a kind of word line driving circuit, suitable for driving a wordline of ROM storage array characterized by comprising
Word line selection circuit generates word line selection signal according to input signal；
Voltage conversion circuit exports first voltage or second voltage according to the word line selection signal, and the first voltage is high
In supply voltage, the second voltage is lower than ground voltage.
2. word line driving circuit according to claim 1, which is characterized in that when the word line selection signal indicates current word
When line is selected, the voltage conversion circuit exports the first voltage；When the word line selection signal indicates wordline current not
When selected, the voltage conversion circuit exports the second voltage.
3. word line driving circuit according to claim 1, which is characterized in that the circuit further include:
Buffer, the buffer is powered using the first voltage and the second voltage, defeated to the voltage conversion circuit
First voltage or second voltage out is buffered, to enhance the driving capability of the word line driving circuit.
4. a kind of ROM memory, including ROM storage array, every wordline in the ROM storage array is all by respective wordline
Driving circuit is driven, which is characterized in that the word line driving circuit includes:
Word line selection circuit generates word line selection signal according to input signal；
Voltage conversion circuit exports first voltage or second voltage according to the word line selection signal, and the first voltage is high
In supply voltage, the second voltage is lower than ground voltage.
5. ROM memory according to claim 4, which is characterized in that when the word line selection signal indicates wordline current
When selected, the voltage conversion circuit exports the first voltage；When the word line selection signal instruction wordline current not by
When choosing, the voltage conversion circuit exports the second voltage.
6. ROM memory according to claim 4, which is characterized in that the word line driving circuit further include:
Buffer, the buffer is powered using the first voltage and the second voltage, defeated to the voltage conversion circuit
First voltage or second voltage out is buffered, to enhance the driving capability of the word line driving circuit.
7. according to the described in any item ROM memories of claim 4 to 6, which is characterized in that the ROM memory further include: rise
Volt circuit, the booster circuit generate the first voltage according to the supply voltage.
8. according to the described in any item ROM memories of claim 4 to 6, which is characterized in that the ROM memory further include: drop
Volt circuit, the reduction voltage circuit generate the second voltage according to the ground voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711407353.3A CN109961810B (en) | 2017-12-22 | 2017-12-22 | Word line driving circuit of ROM memory array and ROM memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711407353.3A CN109961810B (en) | 2017-12-22 | 2017-12-22 | Word line driving circuit of ROM memory array and ROM memory |
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| Publication Number | Publication Date |
|---|---|
| CN109961810A true CN109961810A (en) | 2019-07-02 |
| CN109961810B CN109961810B (en) | 2021-07-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201711407353.3A Active CN109961810B (en) | 2017-12-22 | 2017-12-22 | Word line driving circuit of ROM memory array and ROM memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967741A (en) * | 2021-02-06 | 2021-06-15 | 江南大学 | High-speed high-voltage word line driving circuit facing storage array |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1627444A (en) * | 2003-12-10 | 2005-06-15 | 松下电器产业株式会社 | Semiconductor memory device |
| US20060203553A1 (en) * | 2004-08-04 | 2006-09-14 | Micron Technology, Inc. | NAND string wordline delay reduction |
| CN103794242A (en) * | 2012-10-31 | 2014-05-14 | 台湾积体电路制造股份有限公司 | Wordline tracking for boosted-wordline timing scheme |
-
2017
- 2017-12-22 CN CN201711407353.3A patent/CN109961810B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1627444A (en) * | 2003-12-10 | 2005-06-15 | 松下电器产业株式会社 | Semiconductor memory device |
| US20060203553A1 (en) * | 2004-08-04 | 2006-09-14 | Micron Technology, Inc. | NAND string wordline delay reduction |
| CN103794242A (en) * | 2012-10-31 | 2014-05-14 | 台湾积体电路制造股份有限公司 | Wordline tracking for boosted-wordline timing scheme |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967741A (en) * | 2021-02-06 | 2021-06-15 | 江南大学 | High-speed high-voltage word line driving circuit facing storage array |
| CN112967741B (en) * | 2021-02-06 | 2023-09-08 | 江南大学 | High-speed high-voltage word line driving circuit for memory array |
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| Publication number | Publication date |
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| CN109961810B (en) | 2021-07-23 |
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