CN114446341A - Word line driving circuit of memory and time sequence control method - Google Patents
Word line driving circuit of memory and time sequence control method Download PDFInfo
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- CN114446341A CN114446341A CN202011214855.6A CN202011214855A CN114446341A CN 114446341 A CN114446341 A CN 114446341A CN 202011214855 A CN202011214855 A CN 202011214855A CN 114446341 A CN114446341 A CN 114446341A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1693—Timing circuits or methods
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Abstract
The application provides a word line driving circuit of a memory, which comprises a plurality of pre-decoders and a plurality of row decoding drivers connected with the pre-decoders, wherein each row decoding driver comprises a power supply selection circuit and a plurality of decoding driving circuits, and the word line driving circuits control word lines of the magnetic random access memory; the power selection circuit and each decoding driving circuit are respectively provided with two input ends, wherein one input end is connected to the driving selection signals provided by the plurality of pre-decoders; the other input end of the power supply selection circuit is connected to a read-write selection signal, and the output end of the power supply selection circuit is connected to a common node; the power supply selection circuit selects the write voltage or the read voltage of the word line according to the input row pre-decoding signal and the read-write selection signal, and the word line driving circuit power supply voltage selects the read voltage when the read-write selection signal is in a read state and the row pre-decoding signal is effective. The word line driving circuit has the advantages of simple structure, low manufacturing cost, high reliability and the like.
Description
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a word line driving circuit and a timing control method for a memory.
Background
A Magnetoresistive Random Access Memory (MRAM) needs to apply a current from a bit line to a source line to the MRAM in a write operation, and a Magnetic Tunneling Junction (MTJ) is written in a p-state (low resistance state); or applying a current from the source line to the bit line to the MRAM, the MTJ writes to the ap state (high resistance state). Since the write current is larger, which is related to the size of the switching transistor in the MRAM cell, increasing the size of the switching transistor increases the area of the entire column of the MRAM, and therefore, the drive current is increased by applying an overvoltage to the gate voltage of the transistor. The current required for reading the MRAM is low, and no over-voltage is required. The word line driving circuit of the MRAM chip needs to be able to output a waveform of a dual voltage to supply a different operating voltage VDD at the time of read/write operations. Some manufacturers use a common voltage VCOM for potential switching to form a variation in the operating voltage of the word line driver circuit.
For example, U.S. patent application No. US20130314980a1 switches the power supply VCOM input to the word line driver circuit, using Vwl for write operations and Vcore for read operations. However, the word line driving circuit is generally large in scale, and in this technique, the VCOM parasitic capacitance is relatively large, and VCOM switching requires a long time. This can cause the switching transistor in the MRAM cell to be over-stressed for a relatively long time during the read operation, which can affect the reliability of the transistor. On the other hand, since the parasitic capacitance of VCOM is large, large power consumption is wasted for VCOM switching in the read operation.
Disclosure of Invention
In order to solve the above technical problem, an object of the present invention is to provide a word line driving circuit, which selects and controls a word line through a pre-decoder and a corresponding power switching circuit under a word line driving circuit structure with a reduced device architecture. The word line driving circuit has the advantages of simple structure, low manufacturing cost, high reliability, high reading and writing speed, effective reduction of reading operation power consumption, reduction of the total chip area and the like.
The purpose of the application and the technical problem to be solved are realized by adopting the following technical scheme.
According to the word line driving circuit provided by the application, the word line driving circuit is suitable for a magnetic random access memory chip architecture and comprises a plurality of row decoding drivers comprising a power supply selection circuit and a plurality of row pre-decoders connected with the row decoding drivers. The word line driving circuit controls the word line of the magnetic random access memory; the power selection circuit and each decoding driving circuit are respectively provided with two input ends, wherein one input end is connected to the driving selection signals provided by the plurality of pre-decoders; the other input end of the power supply selection circuit is connected to a read-write selection signal, and the output end of the power supply selection circuit is connected to a common node; the power supply selection circuit selects the write voltage or the read voltage of the word line according to the input row pre-decoding signal and the read-write selection signal, and the word line driving circuit power supply voltage selects the read voltage when the read-write selection signal is in a read state and the row pre-decoding signal is effective, and otherwise selects the write voltage.
The technical problem solved by the application can be further realized by adopting the following technical measures.
Optionally, when a read enable signal external to the chip arrives, the read-write select signal remains in a write state within a set time, so that a write voltage is applied to the selected word line; and after the set time, the read-write selection signal is changed into a read state.
Optionally, the input circuit of each row decoding driver is a nand gate circuit, the output circuit of the row decoding driver is a buffer circuit or an inverter circuit, and the input end of the row decoding driver is connected to the output end of the nand gate circuit.
Optionally, the power selection circuit includes: the input ends of the NAND gates are respectively connected with the read-write selection signals and the driving selection signals; the input end of the NOT gate is connected with the output end of the NAND gate; a gate of the write enable switch is connected with the output end of the NOT gate, a source of the write enable switch is connected with a first potential, and a drain of the write enable switch is connected with the common node; and a grid of the read enable switch is connected with the output end of the NAND gate, a source is connected with a second potential, and a drain is connected with the common node.
Optionally, the write enable switch and the read enable switch are p-type field effect transistors or n-type field effect transistors.
Optionally, the read/write selection signal is generated by a read/write enable circuit, and includes: the input end of the first NOT gate is connected with a write control signal of the memory; one input end of the NAND gate is connected with the output end of the first NAND gate, and the other input end of the NAND gate is connected with a power switch control enabling signal; and the input end of the second NOT gate is connected with the output end of the NAND gate, and the output end of the second NOT gate generates the read-write selection signal.
It is another object of the present invention to provide a memory device including any of the word line driver circuits described above.
Another objective of the present application is to provide a timing control method for a memory, including: the plurality of pre-decoders select the working area decoding circuit according to the address signal; generating a read-write selection signal through a read-write enabling circuit according to a write control signal of the memory and a power switch control enabling signal; the row decoding driver selects a writing voltage or a reading voltage of the word line according to the reading and writing selection signal and the power selection circuit according to the reading and writing selection signal, and the word line driving circuit power voltage selects the reading voltage when the reading and writing selection signal is in a reading state and the row pre-decoding signal is effective, otherwise, the writing voltage is selected.
The technical problem solved by the application can be further realized by adopting the following technical measures.
Optionally, when a read enable signal external to the chip arrives, the read-write select signal remains in a write state within a set time, so that a write voltage is applied to the selected word line; and after the set time, the read-write selection signal is changed into a read state.
Optionally, during a read operation, the time length for adjusting the potential led into the output circuit to the second potential is controlled by controlling the enabling time of the enable signal through controlling the power switch. Therefore, the speed of pulling up the word line can be increased, and the reading speed is improved.
Optionally, the time length is adjusted so that a peak difference between the rising potential introduced into the output circuit and the second potential is close to or equal to 0V.
According to the power supply switching circuit, the circuit change of the region decoding circuit reduces the external power supply switching circuit with large area. Although each group of regional decoding circuits is added with a power supply switching circuit, the partial circuits are generally shared by partial or all decoding driving circuits, the size is relatively small, the area of each group of regional decoding circuits is not greatly influenced, and the total chip area of the word line driving circuit can be reduced. Secondly, the parasitic capacitance of the common node VPP is only 1/n during the reading operation, and n is the number of the regional decoding circuits. During continuous read-write operation, VPP needs to be charged and discharged between VDD1 and VDD2, and power consumption during read operation can be effectively saved due to reduction of VPP parasitic capacitance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of an exemplary word line driver circuit for a memory;
FIG. 2 is a schematic diagram of a word line driver circuit of a memory according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a local decoding circuit according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a read/write enable circuit according to an embodiment of the present disclosure;
FIG. 5 is a timing diagram illustrating a timing control method of a memory according to an embodiment of the present disclosure.
Detailed Description
Refer to the drawings wherein like reference numbers refer to like elements throughout. The following description is based on illustrated embodiments of the application and should not be taken as limiting the application with respect to other embodiments that are not detailed herein.
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. In the present application, directional terms such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", and the like are merely referring to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting.
The terms "first," "second," "third," and the like in the description and claims of this application and in the above-described drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the objects so described are interchangeable under appropriate circumstances. Furthermore, the terms "comprising" and "having," as well as variations thereof, such as, for example, are intended to cover non-exclusive inclusions.
The terminology used in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts of the present application. Unless the context clearly dictates otherwise, expressions used in the singular form encompass expressions in the plural form. In the present specification, it will be understood that terms such as "including," "having," and "containing" are intended to specify the presence of the features, integers, steps, acts, or combinations thereof disclosed in the specification, and are not intended to preclude the presence or addition of one or more other features, integers, steps, acts, or combinations thereof. Like reference symbols in the various drawings indicate like elements.
The drawings and description are to be regarded as illustrative in nature, and not as restrictive. In the drawings, elements having similar structures are denoted by the same reference numerals. In addition, the size and thickness of each component shown in the drawings are arbitrarily illustrated for understanding and ease of description, but the present application is not limited thereto.
In the drawings, the range of configurations of devices, systems, components, circuits is exaggerated for clarity, understanding, and ease of description. It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present.
In addition, in the description, unless explicitly described to the contrary, the word "comprise" will be understood to mean that the recited components are included, but not to exclude any other components. Further, in the specification, "on.
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, the following detailed description of a word line driving circuit of a memory according to the present invention with reference to the accompanying drawings and embodiments will be made in detail as follows.
FIG. 1 is a block diagram of an exemplary wordline driver circuit for a memory. As shown in fig. 1, which is a spin-transfer torque magnetic random access memory disclosed in U.S. patent application No. US20130314980a1, includes a dual voltage row decoder with charge sharing for read operations. The dual voltage row decoder has a charge-shared read operation, reduces read disturb failure rates, and provides a robust macro design that improves yield. During a write operation, a voltage may be applied from one of the power supplies. This patent application discloses switching the power supply VCOM input to the row decoder using Vwl for write operations and Vcore for read operations. The patent can solve the problem that the output voltages of MRAM read-write row decoders are different, but because of design, the row decoder is generally large in scale, the VCOM parasitic capacitance is relatively large, and VCOM switching needs a long time. This can cause the switching transistor in the MRAM cell to be over-stressed for a relatively long time during the read operation, which can affect the reliability of the transistor. On the other hand, since the parasitic capacitance of VCOM is large, large power consumption is wasted for VCOM switching in the read operation.
Fig. 2 is a schematic structural diagram of a word line driving circuit of a memory according to an embodiment of the present disclosure. Fig. 3 is a schematic structural diagram of a local decoding circuit according to an embodiment of the present application.
As shown in fig. 2, the word line driving circuit is suitable for a magnetic random access memory chip architecture, and is generally implemented in two parts, the first part is a pre-decoder (pre-decoder)120, the second part is a row-decoder (local-decoder)140, and the two parts are connected to form a many-to-many decoding circuit.
Optionally, the number of the pre-decoders 120 is two or more, all the pre-decoders 120 have n address input terminals, each pre-decoder 120 has k control output terminals, and the output of each pre-decoder 120 is used as an address selection signal (AIN) and a driving selection signal (BIN) to the column decoding driver 140 according to the function. Wherein n is a positive integer of 1 or more, and k is 2n，k＝2、4、8. 16 …, etc., with a common layout being k 8, 16.
Optionally, the row decoding drivers 140 are connected to the pre-decoder 120, and may be divided into k groups. For example: the output of two 2-4 pre-decoders is connected with 4 regional decoder groups to form a 4-16 word line driving circuit.
As shown in fig. 3, each row decoding driver 140 includes a power selection circuit 141 and a plurality of decoding driving circuits 144. The power selection circuit 141 and each decoding driving circuit 144 have two input terminals, one of which is connected to the driving selection signal (BIN) provided by the pre-decoders 120. The power selection circuit 141 has another input terminal connected to the read/write selection signal VPPSW and an output terminal connected to the common node VPP. The power selection circuit 141 has another input terminal connected to the read/write selection signal VPPSW and an output terminal connected to the common node VPP. The power selection circuit 141 selects a write voltage or a read voltage of a word line according to an input row predecoding signal and a read-write selection signal VPPSW, and the word line driving circuit power voltage selects the read voltage when the read-write selection signal VPPSW is in a read state and the row predecoding signal is valid, or otherwise selects the write voltage.
In an embodiment of the present application, when the read enable signal REN outside the chip arrives, the read/write select signal VPPSW remains in a write state for a set time, so that the selected word line is applied with a write voltage; after the set time, the read/write selection signal VPPSW changes to a read state.
In an embodiment of the present application, as shown in fig. 3, the input circuit of each row decoding driver 144 is a NAND gate (NAND) circuit 145, and the output circuit 146 of the row decoding driver 144 is a buffer circuit or an inverter circuit, and its input terminal is connected to the output terminal of the NAND gate.
In an embodiment of the present application, as shown in fig. 3, the power selection circuit 141 includes: a nand gate 142, a not gate 143, a write enable switch M1 and a read enable switch M2. The input terminals of the nand gate 142 are respectively connected to the read/write selection signal VPPSW and the driving selection signal (BIN). The input end of the not gate 143 is connected to the output end of the nand gate 142. The gate of the write enable switch M1 is connected to the output terminal (WEN) of the not gate 143, the source is connected to the first potential VDD1, and the drain is connected to the common node VPP. The gate of the read enable switch is connected to the output terminal (REN) of the nand gate 142, the source is connected to the second potential VDD2, and the drain is connected to the common node VPP. The first potential VDD1 and the second potential VDD2 are different potentials. The write enable switch M1 and the read enable switch M2 are p-type field effect transistors or n-type field effect transistors.
Fig. 4 is a schematic structural diagram of a read/write enable circuit according to an embodiment of the present disclosure, and as shown in fig. 4, the read/write select signal VPPSW is generated by the read/write enable circuit 150, which includes: a first not gate 151, the input terminal of which is connected to the write control signal WE of the memory; an input end of the nand gate 152 is connected to the output end of the first not gate 151, and the other input end of the nand gate is connected to the power switch control enable signal RE 0V; and a second not gate 153 having an input end connected to the output end of the nand gate 152 and an output end generating the read/write selection signal VPPSW.
In an embodiment of the present application, a memory is provided, which includes any one of the word line driver circuits described above. It should be appreciated that the power switch control enable signal RE0V is generated by the read control signal RE being delayed by certain logic circuitry. The write control signal WE and the read control signal RE are external input signals as a memory.
FIG. 5 is a timing diagram illustrating a timing control method of a memory according to an embodiment of the present disclosure. The write control signal WE of the memory is used for controlling the read-write operation of the memory, and corresponds to the write operation when the WE is at a high potential and corresponds to the read operation when the WE is at a low potential. AIN represents the input memory address and WL one of the decoder output waveforms. The method comprises the following steps: the plurality of pre-decoders 120 select an operating row decoding driver according to an address signal; generating a read-write selection signal VPPSW by the read-write enable circuit 150 according to the write control signal WE of the memory and the power switch control enable signal RE 0V; the row decoding driver 140 selects a write voltage or a read voltage of a word line according to the read-write selection signal VPPSW, the power selection circuit 141 selects a write voltage or a read voltage of a word line according to the input row pre-decoding signal and the read-write selection signal VPPSW, and the word line driving circuit selects the read voltage according to the power supply voltage when the read-write selection signal VPPSW is in a read state and the row pre-decoding signal is valid, or otherwise selects the write voltage.
As described above, when the read enable signal REN outside the chip arrives, the read/write select signal VPPSW remains in a write state for a set time, so that the write voltage is applied to the selected word line; after the set time, the read/write selection signal VPPSW changes to a read state.
In some embodiments, during a read operation, the time length T1 of the potential led to the output circuit 146 being adjusted to the second potential VDD2 is controlled by controlling the enabling timing of the power switch control enable signal RE 0V. Therefore, the speed of pulling up the word line can be increased, and the reading speed is improved. Further, by adjusting the time length T1, the peak difference V1 between the rising potential led to the output circuit and the second potential VDD2 is close to or equal to 0V.
According to the invention, the external power supply switching circuit with a large area is reduced through circuit change of the row decoding driver. Although each group of row decoding drivers is added with a power supply switching circuit, the circuit is generally shared by part or all of the decoding driving circuits, the size is relatively small, the area of each group of row decoding drivers is not greatly influenced, and the total chip area of the word line driving circuit can be reduced. Secondly, the parasitic capacitance of the common node VPP is only 1/n during the read operation, where n is the number of row decoding drivers. During continuous read-write operation, VPP needs to be charged and discharged between VDD1 and VDD2, and the reduction of VPP parasitic capacitance can effectively save power consumption during read operation.
The terms "in one embodiment of the present application" and "in various embodiments" are used repeatedly. This phrase generally does not refer to the same embodiment; it may also refer to the same embodiment. The terms "comprising," "having," and "including" are synonymous, unless the context dictates otherwise.
Although the present application has been described with reference to specific embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the application, and all changes, substitutions and alterations that fall within the spirit and scope of the application are to be understood as being covered by the following claims.
Claims (10)
1. A memory word line driving circuit, suitable for magnetic random memory chip architecture, the said word line driving circuit includes a plurality of row decoding drivers including power selection circuit and a plurality of pre-decoders connected with it, characterized by that:
the word line driving circuit controls the word line of the magnetic random access memory;
the power selection circuit and each row decoding driver are respectively provided with two input ends, wherein one input end is connected to the driving selection signals provided by the plurality of pre-decoders;
the other input end of the power supply selection circuit is connected to a read-write selection signal, and the output end of the power supply selection circuit is connected to a common node;
the power supply selection circuit selects the write voltage or the read voltage of the word line according to the input row pre-decoding signal and the read-write selection signal, and the word line driving circuit power supply voltage selects the read voltage when the read-write selection signal is in a read state and the row pre-decoding signal is effective, and otherwise selects the write voltage.
2. The word line driver circuit of claim 1 in which the read/write select signal remains in a write state for a set time when a read enable signal arrives external to the chip, causing a write voltage to be applied to the selected word line; and after the set time, the read-write selection signal is changed into a read state.
3. The word line driver circuit of claim 1, wherein the input circuit of each of said row decoding drivers is a nand gate circuit, and the output circuit of said row decoding driver is a buffer circuit or an inverter circuit, and the input terminal of said nand gate circuit is connected to the output terminal of said nand gate circuit.
4. The word line driver circuit of claim 1, wherein the power supply selection circuit comprises:
the input ends of the NAND gates are respectively connected with the read-write selection signals and the driving selection signals;
the input end of the NOT gate is connected with the output end of the NAND gate;
a gate of the write enable switch is connected with the output end of the NOT gate, a source of the write enable switch is connected with a first potential, and a drain of the write enable switch is connected with the common node;
and the grid of the read enable switch is connected with the output end of the NAND gate, the source of the read enable switch is connected with the second potential, and the drain of the read enable switch is connected with the common node.
5. The wordline driver circuit of claim 4, wherein the write enable switch and the read enable switch are p-type field effect transistors or n-type field effect transistors.
6. The wordline driver circuit of claim 1, wherein the read and write select signals are generated by a read and write enable circuit comprising:
the input end of the first NOT gate is connected with a write control signal of the memory;
one input end of the NAND gate is connected with the output end of the first NAND gate, and the other input end of the NAND gate is connected with a power switch control enabling signal;
and the input end of the second NOT gate is connected with the output end of the NAND gate, and the output end of the second NOT gate generates the read-write selection signal.
7. A memory comprising the word line driver circuit as claimed in any one of claims 1 to 5.
8. A timing control method of a memory including the word line driver circuit of claim 1, the timing control method comprising:
the plurality of pre-decoders select the working row decoding drivers according to the address signals;
generating a read-write selection signal through a read-write enabling circuit according to a write control signal of the memory and a power switch control enabling signal;
the power supply selection circuit selects the write voltage or the read voltage of the word line according to the input row pre-decoding signal and the read-write selection signal, and the word line driving circuit power supply voltage selects the read voltage when the read-write selection signal is in a read state and the row pre-decoding signal is effective, and otherwise selects the write voltage.
9. The timing control method of the memory according to claim 8, wherein when a read enable signal arrives outside the chip, the read/write select signal remains in a write state for a set time, so that a write voltage is applied to the selected word line; and after the set time, the read-write selection signal is changed into a read state.
10. The timing control method of the memory according to claim 9, wherein the time length of the adjustment of the potential introduced to the output circuit of the row decoding driver to the second potential is controlled by controlling the enable timing of the power switch control enable signal during the read operation; and adjusting the time length so that a peak difference between a rising potential introduced to an output circuit of the row decode driver and the second potential is close to or equal to 0V.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118038949A (en) * | 2024-04-12 | 2024-05-14 | 浙江力积存储科技有限公司 | Device and method for saving energy consumption in memory refreshing process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118038949A (en) * | 2024-04-12 | 2024-05-14 | 浙江力积存储科技有限公司 | Device and method for saving energy consumption in memory refreshing process |
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