CN219778495U - Circuit for reducing standby power consumption - Google Patents
Circuit for reducing standby power consumption Download PDFInfo
- Publication number
- CN219778495U CN219778495U CN202321365185.7U CN202321365185U CN219778495U CN 219778495 U CN219778495 U CN 219778495U CN 202321365185 U CN202321365185 U CN 202321365185U CN 219778495 U CN219778495 U CN 219778495U
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- China
- Prior art keywords
- circuit
- vcc
- switch chip
- level
- power supply
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- 239000003990 capacitor Substances 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000003044 adaptive effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000002618 waking effect Effects 0.000 description 1
Abstract
The utility model relates to an LCD control circuit, in particular to a circuit for reducing standby power consumption, which realizes wake-up and standby switching. The power supply VCC is connected with the switch chip U1 in an adaptive mode, the VCC forms VCC_LCD through the switch chip U1, power is supplied to the LCD screen, the switch chip U1 is connected with an enabling circuit in an adaptive mode, and the enabling circuit sends an enabling signal to the switch chip U1. The power supply is characterized in that the enabling circuit comprises a power supply VDD, a high-level circuit and a low-level circuit are arranged between the power supply VDD and the output end of the enabling circuit, keys are arranged on the high-level circuit and the low-level circuit, the high-level enable EN_high is output by the output end of the enabling circuit when the key of the high-level circuit is pressed, a channel is formed between VCC and VCC_LCD, the LCD screen is in a working state when the key of the low-level circuit is pressed, the low-level enable EN_low is output by the output end of the enabling circuit, the VCC and the VCC_LCD form an open circuit, and the power failure of the LCD screen is in a standby state. The standby power consumption of the circuit is low.
Description
Technical Field
The utility model relates to an LCD control circuit, in particular to a circuit for reducing standby power consumption, which realizes wake-up and standby switching.
Background
At present, a traditional LCD control circuit for waking up and standby switching comprises a power supply VCC and a switch chip U1, wherein the power supply VCC is connected with the switch chip U1 in an adaptive manner, the power supply VCC forms VCC_LCD through the switch chip U1 to supply power for an LCD screen, the switch chip U1 is connected with an MCU in an adaptive manner, and the MCU sends an enabling signal to the switch chip U1 to control whether the power supply VCC and the VCC_LCD form a passage or not. The control circuit utilizes the MCU to control whether the switch chip U1 is on or off, and the MCU consumes electric energy in standby, so that the standby power consumption of the circuit is higher.
Disclosure of Invention
The utility model aims to provide a circuit for reducing standby power consumption, which has lower standby power consumption.
In order to solve the problems, the following technical scheme is provided:
the circuit for reducing standby power consumption comprises a power supply VCC and a switch chip U1, wherein the power supply VCC is connected with the switch chip U1 in an adapting way, the power supply VCC forms VCC_LCD through the switch chip U1 and supplies power to an LCD screen, the switch chip U1 is connected with an enabling circuit in an adapting way, and the enabling circuit sends an enabling signal to the switch chip U1 and is used for controlling whether the power supply VCC and the VCC_LCD form a passage or not. The power supply is characterized in that the enabling circuit comprises a power supply VDD, a high-level circuit and a low-level circuit are arranged between the power supply VDD and the output end of the enabling circuit, keys are arranged on the high-level circuit and the low-level circuit, the high-level enable EN_high is output by the output end of the enabling circuit when the key of the high-level circuit is pressed, a channel is formed between VCC and VCC_LCD, the LCD screen is in a working state when the power is on, the key of the low-level circuit is pressed, the low-level enable EN_low is output by the output end of the enabling circuit, the VCC and the VCC_LCD form an open circuit, and the power failure of the LCD screen is in a standby state.
The high-level circuit comprises a first resistor, a second resistor, a PMOS (P-channel metal oxide semiconductor) tube, a diode and a key, wherein the power supply VDD is connected with one end of the first resistor and the source stage of the PMOS tube, the other end of the first resistor is connected with the grid electrode of the PMOS tube and one end of the second resistor, the other end of the second resistor is connected with the positive electrode of the diode, the negative electrode of the diode is connected with one end of the key, and the other end of the key is grounded. The drain of the PMOS tube is connected with the output end OUT of the enabling circuit.
The front end structure of the low-level circuit is the same as that of the high-level circuit, the drain of the PMOS tube of the low-level circuit is connected with the input end of the inverter INV, and the output end of the inverter is connected with the output end OUT of the enabling circuit.
The model of the switch chip U1 is DIO7553ST6, the 1 pin of the switch chip U1 is connected with the power supply VCC, the 6 pin of the switch chip U1 outputs the VCC_LCD, and the 3 pin of the switch chip U1 is connected with the output end of the enabling circuit.
The 1 pin of the switch chip U1 is grounded through a capacitor C1
And the 3 pin of the switch chip U1 is grounded through a resistor R1.
By adopting the scheme, the method has the following advantages:
because the high-level circuit and the low-level circuit are arranged between the power supply VDD of the circuit for reducing standby power consumption and the output end of the enabling circuit, the high-level circuit and the low-level circuit are provided with keys, the keys of the high-level circuit are pressed, the output end of the enabling circuit outputs high-level enabling EN_high, VCC and VCC_LCD form a passage, the LCD screen is in a working state, the keys of the low-level circuit are pressed, the output end of the enabling circuit outputs low-level enabling EN_low, VCC and VCC_LCD form a cut-off, and the LCD screen is in a standby state when power is lost. The circuit realizes the switching between standby and normal operation by using the keys without MCU control, thereby avoiding the power consumption generated by MCU during standby and leading the standby power consumption of the circuit to be lower.
Drawings
Fig. 1 is a circuit diagram of a circuit for reducing standby power consumption of the present utility model;
fig. 2 is a circuit diagram of an enable circuit in the circuit for reducing standby power consumption of the present utility model.
Detailed Description
The utility model is described in further detail below in connection with figures 1 and 2.
As shown in fig. 1, the circuit for reducing standby power consumption of the present utility model includes a power VCC and a switching chip U1. The model of the switch chip U1 is DIO7553ST6, the 1 pin of the switch chip U1 is a power input pin and is connected with a power VCC, the 1 pin of the switch chip U1 is grounded through a capacitor C1, and filtering shaping is performed by using the capacitor C1, so that the stability of the input power is ensured. And 6 pins of the switch chip U1 are power supply output pins and output VCC_LCD. The 3 pins of the switch chip U1 are enabling receiving pins and are connected with the output end of the enabling circuit, and the 3 pins of the switch chip U1 are grounded through a resistor R1. The switch chip U1 adopts 2 pins as grounding pins and is connected with GND. The 5 pin of the switch chip U1 is a threshold current pin and is grounded through a resistor R2. The 4-pin FAULT feedback signal pin of the switch chip U1 forms a FAULT signal. The power supply VCC forms VCC_LCD through the switch chip U1 to supply power to the LCD screen.
The enabling circuit comprises a power supply VDD, and a high-level circuit 1 and a low-level circuit 2 are arranged between the power supply VDD and the output end of the enabling circuit. The high-level circuit 1 comprises a first resistor R3, a second resistor R4, a PMOS tube Q1, a diode D1 and a key SW1, wherein a power supply VDD is connected with one end of the first resistor R3 and the source stage of the PMOS tube Q1, the other end of the first resistor R3 is connected with the grid electrode of the PMOS tube Q1 and one end of the second resistor R4, the other end of the second resistor R4 is connected with the positive electrode of the diode D1, the negative electrode of the diode D1 is connected with one end of the key SW1, and the other end of the key SW1 is grounded. The drain of the PMOS transistor Q1 is connected to the output OUT of the enable circuit. When the key SW1 is pressed down, VDD is connected to the ground through the first resistor R3, the second resistor R4, the diode D1 and the key SW1 to form a passage, the grid voltage of the PMOS tube Q1 is reduced, the source voltage of the PMOS tube Q1 is unchanged, the PMOS tube Q1 is conducted, VDD forms high-level enable EN_high through the PMOS tube Q1, the high-level enable EN_high enters the chip U1 through the output end OUT of the enable circuit and the 3 pins of the U1, VCC and VCC_LCD form a passage, and the LCD screen is electrified to enter a working state. The key SW1 is released, no other instruction is given, the chip U1 is always in a conducting state, and the LCD screen works normally.
The low-level circuit 2 comprises a first resistor R5, a second resistor R6, a PMOS tube Q2, a diode D2 and a key SW2, wherein a power supply VDD is connected with one end of the first resistor R5 and the source stage of the PMOS tube Q2, the other end of the first resistor R5 is connected with the grid electrode of the PMOS tube Q2 and one end of the second resistor R6, the other end of the second resistor R6 is connected with the positive electrode of the diode D2, the negative electrode of the diode D2 is connected with one end of the key SW2, and the other end of the key SW2 is grounded. The drain of the PMOS transistor Q2 is connected to the input of the inverter INV, and the output of the inverter INV is connected to the output OUT of the enable circuit. When the key SW2 is pressed down, VDD is connected to the ground through the first resistor R5, the second resistor R6, the diode D2 and the key SW2 to form a passage, the gate voltage of the 2MOS tube Q2 is reduced, the source voltage of the PMOS tube Q2 is unchanged, the PMOS tube Q2 is conducted, VDD forms a high-level signal through the PMOS tube Q2, the high-level signal becomes high-level enable EN_low through the inverter INV, the high-level enable EN_low enters the chip U1 through the output end OUT of the enable circuit and the 3 pins of the U1, VCC and VCC_LCD form an open circuit, and the LCD screen is in a power failure state. The key SW2 is released, no other instruction is given, the chip U2 is always in an off state, and the LCD stands by.
When the PMOS tube Q1 and the PMOS tube Q2 are not conducted, the power supply VDD and the ground are disconnected, so that electric energy cannot be consumed, and energy consumption is saved. In this embodiment, the power supply VDD is a lithium battery.
The circuit for reducing standby power consumption is suitable for a monitoring circuit of a training room, and when a trainee trains, the key SW1 is pressed to enable the LCD to be in a working state, so that a monitoring picture is displayed. When no training is performed, the key SW2 is pressed to enable the LCD to be in a standby state, so that standby power consumption is greatly reduced.
Claims (6)
1. The circuit for reducing standby power consumption comprises a power supply VCC and a switch chip U1, wherein the power supply VCC is connected with the switch chip U1 in an adapting way, the power supply VCC forms VCC_LCD through the switch chip U1 and supplies electric energy to an LCD screen, the switch chip U1 is connected with an enabling circuit in an adapting way, and the enabling circuit sends an enabling signal to the switch chip U1 and is used for controlling whether the power supply VCC and the VCC_LCD form a passage or not; the power supply is characterized in that the enabling circuit comprises a power supply VDD, a high-level circuit and a low-level circuit are arranged between the power supply VDD and the output end of the enabling circuit, keys are arranged on the high-level circuit and the low-level circuit, the high-level enable EN_high is output by the output end of the enabling circuit when the key of the high-level circuit is pressed, a channel is formed between VCC and VCC_LCD, the LCD screen is in a working state when the power is on, the key of the low-level circuit is pressed, the low-level enable EN_low is output by the output end of the enabling circuit, the VCC and the VCC_LCD form an open circuit, and the power failure of the LCD screen is in a standby state.
2. The circuit for reducing standby power consumption according to claim 1, wherein the high-level circuit comprises a first resistor, a second resistor, a PMOS (P-channel metal oxide semiconductor) tube, a diode and a key, wherein the power supply VDD is connected with one end of the first resistor and the source stage of the PMOS tube, the other end of the first resistor is connected with the grid electrode of the PMOS tube and one end of the second resistor, the other end of the second resistor is connected with the positive electrode of the diode, the negative electrode of the diode is connected with one end of the key, and the other end of the key is grounded; the drain of the PMOS tube is connected with the output end OUT of the enabling circuit.
3. The circuit for reducing standby power consumption according to claim 2, wherein the front end structure of the low level circuit is the same as the structure of the high level circuit, the drain of the PMOS transistor of the low level circuit is connected to the input terminal of the inverter INV, and the output terminal of the inverter INV is connected to the output terminal OUT of the enable circuit.
4. The circuit for reducing standby power consumption according to claim 1, wherein the switch chip U1 is of a DIO7553ST6 type, pin 1 of the switch chip U1 is connected to the power VCC, pin 6 of the switch chip U1 outputs the vcc_lcd, and pin 3 of the switch chip U1 is connected to an output terminal of the enable circuit.
5. The circuit for reducing standby power consumption according to claim 4, wherein pin 1 of the switch chip U1 is grounded through a capacitor C1.
6. The circuit for reducing standby power consumption according to claim 4, wherein 3 pin of the switch chip U1 is grounded through a resistor R1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321365185.7U CN219778495U (en) | 2023-05-31 | 2023-05-31 | Circuit for reducing standby power consumption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321365185.7U CN219778495U (en) | 2023-05-31 | 2023-05-31 | Circuit for reducing standby power consumption |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219778495U true CN219778495U (en) | 2023-09-29 |
Family
ID=88130249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321365185.7U Active CN219778495U (en) | 2023-05-31 | 2023-05-31 | Circuit for reducing standby power consumption |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219778495U (en) |
-
2023
- 2023-05-31 CN CN202321365185.7U patent/CN219778495U/en active Active
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