CN210780130U - Power-off control circuit - Google Patents

Power-off control circuit Download PDF

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Publication number
CN210780130U
CN210780130U CN201921211425.1U CN201921211425U CN210780130U CN 210780130 U CN210780130 U CN 210780130U CN 201921211425 U CN201921211425 U CN 201921211425U CN 210780130 U CN210780130 U CN 210780130U
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power supply
power
triode
resistor
chip
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CN201921211425.1U
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陈朋金
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Shenzhen Neoway Technology Co Ltd
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Shenzhen Neoway Technology Co Ltd
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Abstract

The utility model provides a power shutoff control circuit, include: the power supply, the chip, the power supply main control module and the switch module; the power supply main control module comprises an MOS tube and a triode; the source electrode of the MOS tube is connected to the anode of the power supply, and the drain electrode of the MOS tube is connected to the power supply input end of the chip; a first resistor is arranged on a circuit which connects the source electrode of the MOS tube with the grid electrode; the collector of the triode is connected to the grid of the MOS tube, the base of the triode is connected to the power output end of the chip, and the emitter of the triode is grounded; a second capacitor is connected in series with a circuit which connects the source electrode of the MOS tube with the base electrode of the triode; the switch module is connected in parallel with the second capacitor and comprises a key and a second resistor connected with the key, one end of the second resistor is connected with the source electrode of the MOS transistor Q1, the other end of the second resistor is connected with one end of the key, and the other end of the key is connected with the base electrode of the triode.

Description

Power-off control circuit
Technical Field
The utility model relates to a power supply circuit technical field, concretely relates to power shutoff control circuit.
Background
In current internet of things equipment, some equipment such as an electricity meter or a gas meter and the like need to be powered by dry batteries in normal use. After production and delivery, the devices need a long time to be installed and used, and during the period, the batteries need to be completely disconnected, so that electric leakage is reduced. The prior art is that the control system enters the sleep mode, but the power consumption is low, and the circuit needs to be improved.
Therefore, there is a need for an improved power supply circuit in the prior art to reduce unnecessary power consumption.
SUMMERY OF THE UTILITY MODEL
In order to achieve the above object, the present invention provides a power shutoff control circuit for completely shutting off a power supply, which can solve the electric leakage problem existing in the prior art under the condition of system dormancy.
The power supply turn-off circuit comprises a power supply, a chip, a power supply main control module and a switch module, wherein the power supply main control module and the switch module are connected with the power supply and the chip; the power supply main control module comprises an MOS tube and a triode; the source electrode of the MOS tube is connected to the anode of the power supply, and the drain electrode of the MOS tube is connected to the power supply input end of the chip; a first resistor is arranged on a circuit connecting the source electrode of the MOS tube with the grid electrode; the collector of the triode is connected to the grid of the MOS tube, the base of the triode is connected to the power output end of the chip, and the emitter of the triode is grounded; a second capacitor is connected in series with a circuit which is connected with the source electrode of the MOS tube and the base electrode of the triode; the switch module is connected with the second capacitor in parallel and comprises a key and a second resistor connected with the key, one end of the second resistor is connected with the source electrode of the MOS tube Q1, the other end of the second resistor is connected with one end of the key, and the other end of the key is connected with the base electrode of the triode.
In a specific embodiment, the power shutdown control circuit further includes a power supply auxiliary control circuit, where the power supply auxiliary control circuit includes a third resistor and a third capacitor; one end of the third resistor is connected with the drain electrode of the MOS tube, and the other end of the third resistor is connected with the base electrode of the triode; one end of the third capacitor is connected with the base electrode of the triode, and the other end of the third capacitor is grounded.
In a specific embodiment, the MOS transistor is a P-type MOS transistor.
In a specific embodiment, the MOS transistor is an enhanced PMOS transistor.
In a specific embodiment, the transistor Q2 is an NPN transistor.
Without this requirement, in a specific embodiment, the power source is one of a dry cell battery, a secondary battery, or a lithium battery.
So, the power shutoff control circuit that this application provided can automatic cutout power, places the loss of electric quantity, extension battery live time.
Drawings
Fig. 1 is a circuit diagram of a power-off control circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Of course, the described embodiments are only some, not all embodiments of the invention. Based on the embodiments in the present invention, other embodiments that ordinary skilled person in the art obtained under the prerequisite that does not make creative work, such as model through changing resistance value or capacitance value or changing MOS or triode all belong to the protection scope of the present invention.
Fig. 1 is a circuit diagram of a power-off control circuit according to an embodiment of the present invention. The off-power control circuit includes a chip 10 and a power supply 20 configured to supply power to the chip 10. The power shutdown control circuit 100 further includes a power supply main control module 30, a switch module 40, and a power supply auxiliary control module 50. The power supply main control module 30, the switch module 40 and the power supply auxiliary control module 50 cooperate with each other to control the power supply 20 to supply power when the chip 10 works, or not to supply power at all when the chip 10 does not work, so as to reduce unnecessary power consumption. The power supply main control module 30 is connected with the power module 200 and the chip 10, the switch module 40 is connected with the power supply main control module 30 and the chip 10, and the power supply auxiliary control module 50 is connected with the power supply main control module 30 and the chip 10.
Further, in the present embodiment, the chip 10 includes a Power input terminal 11 (marked as Vbus in fig. 1) and a Power control terminal 12 (marked as Power-Ctr in fig. 1). The power module 20 includes a power source 21 and a first capacitor C1 connected to the power source 21. Specifically, one end of the first capacitor C1 is connected to the positive electrode of the power supply 21, and the other end is grounded. The power source 21 includes, but is not limited to, one of a dry cell battery, a secondary battery, or a lithium battery.
In this embodiment, the power supply main control module 30 includes a MOS transistor Q1, a transistor Q2, a first resistor R1, and a second capacitor C2. Specifically, the MOS transistor Q1 is connected to the positive electrode of the power supply 21. Specifically, the source S of the MOS transistor Q1 is connected to the positive electrode of the power supply 21, and the drain D of the MOS transistor Q1 is connected to the power input terminal 11 of the chip 10. The first resistor R1 is used as a pull-up resistor and is disposed on the circuit where the source S of the MOS transistor Q1 is connected to the gate G. The transistor Q2 is connected to the gate G of the MOS transistor Q1. Specifically, the gate G of the MOS transistor Q1 is connected to the collector of the transistor Q2. The base of the triode Q2 is connected to the power output end of the chip 10; the emitter of the transistor Q2 is connected to ground. The second capacitor C2 is connected in series to the circuit where the source of the MOS transistor Q1 is connected to the base of the transistor Q2, that is, one end of the second capacitor C2 is connected to the source of the MOS transistor Q1, and the other end is connected to the base of the transistor Q2.
In the present embodiment, the MOS transistor Q1 is a P-type MOS transistor, preferably an enhancement-type PMOS transistor.
In this embodiment, the transistor Q2 is an NPN transistor.
The switch module 40 includes a key S1 and a second resistor R2 connected in series with the key S1. The button S1 is used to turn on transistor Q2 in response to a user touch. The switch module 40 is connected in parallel with a second capacitor C2. Specifically, one end of the second resistor R2 is connected to the source S of the MOS transistor Q1, the other end is connected to one end of the button S1, and the other end of the button S1 is connected to the base of the transistor Q2. By default, the button S1 is normally open.
The power supply auxiliary control module 50 includes a third resistor R3 and a third capacitor C3. One end of the third resistor R3 is connected to the drain D of the MOS transistor Q1, the other end is connected to the base of the transistor Q2, one end of the third capacitor C3 is also connected to the base of the transistor Q2, and the other end is grounded. Preferably, the third resistor R3 has a resistance of 10-100K Ω. The value of the third capacitance C3 is preferably 1 UF. In other embodiments, the power supply auxiliary control block 50 may be omitted.
The chip 10 further includes a fourth capacitor C4 and a fourth resistor R4. One end of the fourth capacitor C4 is connected to the power input of the chip 10, and the other end is grounded. The fourth resistor R4 is connected in series to the power control terminal 12 of the chip 10 and the base of the transistor Q2.
In this embodiment, the resistance of the first resistor R1 is greater than the resistance of the second resistor R2. Specifically, the first resistor R1 is preferably 1M Ω, and the second resistor R2 is preferably 100K Ω. The third resistor R3 preferably has a resistance of 100K Ω, and the fourth resistor R4 preferably has a resistance of 1.5K Ω.
It can be understood that the specific working process of the power shutdown control circuit is as follows:
when the power supply 21 is installed in the off-mains control circuit, the second capacitor C2 in the power supply main control module 30 draws power from the power supply 21 and charges the transistor Q2, so that the transistor Q2 is turned on; after the Q2 is turned on, through the pull-down action of the first resistor R1, Vgs between the source S and the gate G of the MOS transistor Q1 is smaller than a preset voltage value, at this time, the MOS transistor Q1 is turned on, and a circuit between the power supply 21 and the power supply input terminal 11 of the chip 10 is turned on, and supplies power to the chip 10. The chip 10 receives power from the power supply 21, controls the operation of the device on which the chip 10 is mounted, and sets the power control terminal 12 of the chip 10 to a high level (1.8V or higher). The power control terminal 12 is set to high level, so that the transistor Q2 and the MOS transistor Q1 are always in a conducting state to maintain the chip 10 or the device in a power supply state of the power supply 21 and perform operations such as chip or system test.
When the operation, such as the test, is completed, the chip 10 controls to set the power control terminal 12 to the low level (0V). When the power control terminal 12 is set to a low level, for example, 0V, the voltage at the base of the transistor Q2 is also low, and the transistor Q2 is non-conductive. The turning off of the transistor Q2 further turns off the MOS transistor Q1, which powers down the power bus. At this time, the voltage of the power input terminal 11 of the chip 10 continuously drops, and after the voltage drops to a certain voltage, the power control terminal 12 of the chip 10 is in a high-impedance state, and at this time, the third capacitor C3 connected to the base of the transistor Q2 keeps the transistor Q2 in the off state until the power of the power input terminal 11 is completely released. At this point the chip 10 is completely unpowered and no power is lost.
When a user needs to use the device provided with the power off control circuit, the user can press a key S1 to switch on the triode Q2, switch on the triode Q2 to switch on the Q1, so that the power supply 21 supplies power to the chip 10, and the control device sets the power control end of the chip 10 to be at a high level after working, maintains the power supply and enters a working state. When the time that the user presses the switch S1 is too short, the third resistor R3 can maintain the Q2 to be turned on, so that the chip 10 can obtain a longer turn-on voltage, and the power control terminal 12 is set to a high level after the chip 10 operates.
By the above, the utility model provides a power supply requirement of the ultralow power consumption equipment of battery powered can be satisfied to the circuit, the operating time of extension battery.
It should be understood that the circuit described herein is merely for the purpose of explaining the present invention, and the present invention is not limited to such a circuit.

Claims (6)

1. A power supply turn-off control circuit comprises a power supply and a chip, and is characterized by also comprising a power supply main control module and a switch module which are connected with the power supply and the chip;
the power supply main control module comprises an MOS tube and a triode;
the source electrode of the MOS tube is connected to the anode of the power supply, and the drain electrode of the MOS tube is connected to the power supply input end of the chip; a first resistor is arranged on a circuit connecting the source electrode of the MOS tube with the grid electrode;
the collector of the triode is connected to the grid of the MOS tube, the base of the triode is connected to the power output end of the chip, and the emitter of the triode is grounded;
a second capacitor is connected in series with a circuit which is connected with the source electrode of the MOS tube and the base electrode of the triode;
the switch module is connected with the second capacitor in parallel and comprises a key and a second resistor connected with the key, one end of the second resistor is connected with the source electrode of the MOS tube Q1, the other end of the second resistor is connected with one end of the key, and the other end of the key is connected with the base electrode of the triode.
2. An off-power control circuit as claimed in claim 1, further comprising a power supply auxiliary control circuit, said power supply auxiliary control circuit comprising a third resistor and a third capacitor; one end of the third resistor is connected with the drain electrode of the MOS tube, and the other end of the third resistor is connected with the base electrode of the triode; one end of the third capacitor is connected with the base electrode of the triode, and the other end of the third capacitor is grounded.
3. The power-off control circuit of claim 2, wherein the MOS transistor is a P-type MOS transistor.
4. The power-off control circuit of claim 3, wherein the MOS transistor is an enhanced PMOS transistor.
5. An off-power control circuit as claimed in claim 3 or 4, wherein the transistor Q2 is an NPN transistor.
6. A power-off control circuit as claimed in any of claims 1 to 4, wherein the power source is one of a dry cell battery, a secondary battery or a lithium battery.
CN201921211425.1U 2019-07-27 2019-07-27 Power-off control circuit Active CN210780130U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921211425.1U CN210780130U (en) 2019-07-27 2019-07-27 Power-off control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921211425.1U CN210780130U (en) 2019-07-27 2019-07-27 Power-off control circuit

Publications (1)

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CN210780130U true CN210780130U (en) 2020-06-16

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CN201921211425.1U Active CN210780130U (en) 2019-07-27 2019-07-27 Power-off control circuit

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111983953A (en) * 2020-08-12 2020-11-24 广东电网有限责任公司广州供电局 Device and method for reducing power consumption based on collecting manhole cover state during NB-iot dormancy process
CN113489478A (en) * 2021-07-12 2021-10-08 重庆建安仪器有限责任公司 Button on/off control circuit for low-voltage power supply

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111983953A (en) * 2020-08-12 2020-11-24 广东电网有限责任公司广州供电局 Device and method for reducing power consumption based on collecting manhole cover state during NB-iot dormancy process
CN113489478A (en) * 2021-07-12 2021-10-08 重庆建安仪器有限责任公司 Button on/off control circuit for low-voltage power supply
CN113489478B (en) * 2021-07-12 2022-11-22 重庆建安仪器有限责任公司 Button on/off control circuit for low-voltage power supply

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