CN220325296U - Power-on and power-off management circuit for controlling battery output - Google Patents
Power-on and power-off management circuit for controlling battery output Download PDFInfo
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- CN220325296U CN220325296U CN202321239337.9U CN202321239337U CN220325296U CN 220325296 U CN220325296 U CN 220325296U CN 202321239337 U CN202321239337 U CN 202321239337U CN 220325296 U CN220325296 U CN 220325296U
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- 239000003990 capacitor Substances 0.000 claims description 14
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- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Abstract
The utility model discloses a power-on and power-off management circuit for controlling battery output, which comprises a battery, an output management circuit, a power control circuit, an acquisition unit, a main control unit and a load, wherein the battery is connected with the power control circuit; the first output end of the battery is connected with the input end of the output management circuit; the second output end of the battery is connected with the input end of the power control circuit; the first output end of the power control circuit is connected with the load; the acquisition unit comprises a control end and a detection end; the second output end of the power control circuit is connected with the control end of the acquisition unit; the detection end of the acquisition unit is connected with the input end of the main control unit; the output end of the main control unit is connected with the second input end of the power control circuit. By designing the power-on/off management circuit on the output path of the battery, the battery can be ensured to normally output and turn off in the on/off state, and the electric quantity loss of the battery in the power-on/off state of the load is reduced.
Description
Technical Field
The utility model belongs to the field of battery output control, and particularly relates to a power-on and power-off management circuit for controlling battery output.
Background
How to reduce the electric quantity loss of the battery in the on/off state, ensure the standby time of the high-power battery and the duration time in the using process is a major concern of electronic design engineers.
Disclosure of Invention
The utility model aims to provide an up-down electricity management circuit for controlling battery output, which can reduce electric quantity loss of a battery in a starting-up state or a closing-down state and ensure the standby time of a high-power battery and the duration time in the using process.
In order to achieve the above purpose, the technical scheme adopted by the utility model is as follows:
the power-on and power-off management circuit for controlling the output of the battery comprises the battery, an output management circuit, a power control circuit, an acquisition unit, a main control unit and a load; the first output end of the battery is connected with the input end of the output management circuit; the second output end of the battery is connected with the input end of the power control circuit; the first output end of the power control circuit is connected with the load; the acquisition unit comprises a control end and a detection end; the second output end of the power control circuit is connected with the control end of the acquisition unit; the detection end of the acquisition unit is connected with the input end of the main control unit; the output end of the main control unit is connected with the second input end of the power control circuit.
The power management circuit is designed on the output path of the battery, and comprises the output management circuit for managing the output path of the battery and the power control circuit for controlling the power output of the battery, so that the battery can be ensured to normally output and turn off in the on/off state, the electric quantity loss of the battery in the on/off state of the load is reduced, and the standby time and the service life of the battery as a power supply are prolonged.
Preferably, the output management circuit comprises a first resistor, a second resistor, a first MOS tube and a power supply; the first output end of the battery is connected with the drain electrode of the first MOS tube and is connected with the first resistor in series; the power supply is connected with the grid electrode of the first MOS tube and is connected with the second resistor in series; and the source electrode of the first MOS tube is grounded.
Preferably, the power control circuit comprises a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a second MOS tube, a third MOS tube and a fourth MOS tube; a first node is arranged between the first resistor and the drain electrode of the first MOS tube; the first node is connected with the grid electrode of the second MOS tube and is connected with the third resistor in series; the source electrode of the second MOS tube is grounded;
the second output end of the battery is connected with the drain electrode of the third MOS tube and is connected with the fourth resistor in series; a second node is arranged between the fourth resistor and the drain electrode of the third MOS tube; a third node is arranged between the control end of the acquisition unit and the grid electrode of the fourth MOS tube; the second node is connected with the third node; the output end of the main control unit is connected with the grid electrode of the third MOS tube, and the fifth resistor is connected in series between the output end of the main control unit and the grid electrode of the third MOS tube; a fourth node is arranged between the fifth resistor and the grid electrode of the third MOS tube; the fourth node is connected with the ground wire and is connected with the sixth resistor in series; the source electrode of the third MOS tube is grounded; and the drain electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube.
Preferably, the power control circuit further comprises a seventh resistor and an eighth resistor; a fifth node is arranged between the second output end of the battery and the fourth resistor; the fifth node is connected with the source electrode of the fourth MOS tube and is connected with the seventh resistor in series; and the eighth resistor is connected in series between the seventh resistor and the source electrode of the fourth MOS tube.
Preferably, the power control circuit further comprises a ninth resistor, a fifth MOS tube and a sixth MOS tube; a sixth node is arranged between the fifth node and the seventh resistor; and the fifth MOS tube and the sixth MOS tube are respectively connected in parallel between the sixth node and the load.
Preferably, the sixth node includes a first connection end and a second connection end; the first connecting end is connected with the source electrode of the fifth MOS tube; the second connecting end is connected with the source electrode of the sixth MOS tube; the load comprises a third connecting end and a fourth connecting end; the drain electrode of the fifth MOS tube is connected with the third connecting end; the drain electrode of the sixth MOS tube is connected with the fourth connecting end;
a seventh node is arranged between the seventh resistor and the eighth resistor; the seventh node comprises a fifth connecting end and a sixth connecting end; the fifth connecting end is connected with the grid electrode of the fifth MOS tube; the sixth connecting end is connected with the grid electrode of the sixth MOS tube.
Preferably, the acquisition unit comprises a key acquisition circuit; the key acquisition circuit comprises an input voltage, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode, a second diode and a key switch; one end of the key switch comprises a seventh connecting end and an eighth connecting end; the seventh connecting end is connected with the cathode of the first diode; the input voltage is connected with the positive electrode of the first diode and the tenth resistor is connected in series between the input voltage and the positive electrode of the first diode; an eighth node is arranged between the tenth resistor and the positive electrode of the first diode; the eighth node is connected with the input end of the main control unit and is connected with the eleventh resistor in series;
the eighth connecting end is connected with the cathode of the second diode; the anode of the second diode is connected with the third node and is connected with the twelfth resistor in series.
Preferably, the key acquisition circuit further comprises a first capacitor, a second capacitor and a piezoresistor; the other end of the key switch is connected with a ground wire; the first capacitor, the second capacitor and the piezoresistor are connected in parallel between the other end of the key switch and the ground wire.
Preferably, the first MOS tube, the second MOS tube and the third MOS tube are all N-MOS tubes; the fourth MOS tube, the fifth MOS tube and the sixth MOS tube are all P-MOS tubes.
Preferably, the first diode and the second diode are anti-reflection diodes.
The beneficial effects are that:
the utility model relates to a power-on and power-off management circuit for controlling battery output, which is characterized in that a power-on and power-off management circuit is designed on an output path of a battery, and comprises an output management circuit for managing the battery output path and a power control circuit for controlling battery power output, so that the battery can be ensured to normally output and turn off in an on/off state, the battery electric quantity loss of a load in the power-on and power-off state is reduced, and the standby time and the service life of the battery as a power supply are prolonged.
Drawings
Fig. 1 is a block diagram showing a system configuration of a power-on/power-off management circuit for controlling battery output according to the present embodiment;
fig. 2 is a first circuit configuration diagram of a power-on/power-off management circuit for controlling battery output according to the present embodiment;
fig. 3 is a second circuit configuration diagram of a power up-down management circuit for controlling battery output according to the present embodiment.
Reference numerals
11. A first resistor; 12. a second resistor; 13. a third resistor; 14. a fourth resistor; 15. a fifth resistor; 16. a sixth resistor; 17. a seventh resistor; 18. an eighth resistor; 19. a ninth resistor; 21. a first MOS tube; 22. a second MOS tube; 23. a third MOS tube; 24. a fourth MOS transistor; 25. a fifth MOS transistor; 26. a sixth MOS transistor; 30. an input voltage; 41. a tenth resistor; 42. an eleventh resistor; 43. a twelfth resistor; 51. a first diode; 52. a second diode; 61. a first capacitor; 62. a second capacitor; 70. a piezoresistor; 80. a key switch; 100. a battery; 201. a detection end of the acquisition unit; 202. a control end of the acquisition unit; 300. a main control unit; 400. a load; 500. and a power supply.
Detailed Description
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following description will explain the specific embodiments of the present utility model with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the utility model, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
The technical scheme of the utility model is described in detail in the following by specific embodiments.
Examples
As shown in fig. 1 to 3, a power management circuit for controlling battery output of the present embodiment includes a battery 100, an output management circuit, a power control circuit, an acquisition unit, a main control unit 300, and a load 400; a first output terminal of the battery 100 is connected with an input terminal of the output management circuit; a second output terminal of the battery 100 is connected with an input terminal of the power control circuit; the first output of the power control circuit is connected to the load 400; the acquisition unit comprises a control end 202 and a detection end 201; a second output end of the power control circuit is connected with the control end 202 of the acquisition unit; the detection end 201 of the acquisition unit is connected with the input end of the main control unit 300; an output terminal of the main control unit 300 is connected to a second input terminal of the power control circuit.
Specifically, the output management circuit of the present embodiment is used for controlling the output path of the battery 100, and when the load 400 has other power supply sources except the battery 100 to supply power to the load 400 in the power-on state, the output management circuit automatically turns off the output of the battery 100, so as to reduce the battery power loss of the load 400 in the power-on state.
Preferably, the output management circuit comprises a first resistor 11, a second resistor 12, a first MOS tube 21 and a power supply 500; the first output end of the battery 100 is connected with the drain electrode of the first MOS tube 21 and is connected with a first resistor 11 in series; the power supply 500 is connected with the grid electrode of the first MOS tube 21 and is connected with a second resistor 12 in series; the source of the first MOS transistor 21 is grounded.
Preferably, the power control circuit includes a third resistor 13, a fourth resistor 14, a fifth resistor 15, a sixth resistor 16, a second MOS transistor 22, a third MOS transistor 23, and a fourth MOS transistor 24; a first node is arranged between the first resistor 11 and the drain electrode of the first MOS tube 21; the first node is connected with the grid electrode of the second MOS tube 22 and is connected with a third resistor 13 in series; the source electrode of the second MOS tube 22 is grounded;
the second output end of the battery 100 is connected with the drain electrode of the third MOS tube 23 and is connected with a fourth resistor 14 in series; a second node is arranged between the fourth resistor 14 and the drain electrode of the third MOS tube 23; a third node is arranged between the control end 202 of the acquisition unit and the grid electrode of the fourth MOS tube 24; the second node is connected with the third node; the output end of the main control unit 300 is connected with the grid electrode of the third MOS tube 23 and is connected with a fifth resistor 15 in series; a fourth node is arranged between the fifth resistor 15 and the grid electrode of the third MOS tube 23; the fourth node is connected with the ground wire and is connected with a sixth resistor 16 in series; the source electrode of the third MOS tube 23 is grounded; the drain of the fourth MOS transistor 24 is connected to the drain of the second MOS transistor 22.
Preferably, the power control circuit further comprises a seventh resistor 17 and an eighth resistor 18; a fifth node is provided between the second output terminal of the battery 100 and the fourth resistor 14; the fifth node is connected with the source electrode of the fourth MOS tube 24 and is connected with a seventh resistor 17 in series; an eighth resistor 18 is connected in series between the seventh resistor 17 and the source of the fourth MOS transistor 24.
Preferably, the power control circuit further comprises a ninth resistor 19, a fifth MOS tube 25 and a sixth MOS tube 26; a sixth node is arranged between the fifth node and the seventh resistor 17; the sixth node is connected in parallel with a fifth MOS tube 25 and a sixth MOS tube 26 between the sixth node and the load 400 respectively.
Preferably, the sixth node includes a first connection end and a second connection end; the first connecting end is connected with the source electrode of the fifth MOS tube 25; the second connecting end is connected with the source electrode of the sixth MOS tube 26; the load 400 includes a third connection and a fourth connection; the drain electrode of the fifth MOS tube 25 is connected with the third connecting end; the drain electrode of the sixth MOS tube 26 is connected with the fourth connecting end;
a seventh node is arranged between the seventh resistor 17 and the eighth resistor 18; the seventh node comprises a fifth connecting end and a sixth connecting end; the fifth connecting end is connected with the grid electrode of the fifth MOS tube 25; the sixth connection terminal is connected to the gate of the sixth MOS transistor 26.
Preferably, the acquisition unit comprises a key acquisition circuit; the key acquisition circuit comprises an input voltage 30, a tenth resistor 41, an eleventh resistor 42, a twelfth resistor 43, a first diode 51, a second diode 52 and a key switch 80; one end of the key switch 80 includes a seventh connection end and an eighth connection end; the seventh connection terminal is connected to the negative electrode of the first diode 51; the input voltage 30 and the anode of the first diode 51 are connected in series with a tenth resistor 41; an eighth node is provided between the tenth resistor 41 and the anode of the first diode 51; the eighth node is connected with the input end of the main control unit 300 and is connected with an eleventh resistor 42 in series;
the eighth connection terminal is connected to the cathode of the second diode 52; the anode of the second diode 52 is connected to the third node and a twelfth resistor 43 is connected in series between them.
Preferably, the key acquisition circuit further comprises a first capacitor 61, a second capacitor 62 and a piezoresistor 70; the other end of the key switch 80 is connected with the ground wire; the first capacitor 61, the second capacitor 62 and the piezoresistor 70 are connected in parallel between the other end of the key switch 80 and the ground.
Preferably, the first MOS tube 21, the second MOS tube 22 and the third MOS tube 23 are all N-MOS tubes; the fourth MOS transistor 24, the fifth MOS transistor 25 and the sixth MOS transistor 26 are all P-MOS transistors.
Preferably, the first diode 51 and the second diode 52 are anti-reflection diodes.
Specifically, the power control circuit and the key acquisition circuit of the present embodiment are used for output and turn-off control when the battery 100 is used as a power source, the battery 100 is normally output as a power source when the key switch 80 is pressed, and the battery 100 is turned off when the key switch 80 is not pressed, so that the power loss of the battery 100 in the load standby state can be reduced.
Specifically, the model of the first MOS transistor 21 in this embodiment is ZXMN3B14FTA; the model of the second MOS tube 22 and the model of the third MOS tube 23 are ZXMN3B14FTA; the model of the fourth MOS tube 24 is ZXMP3A13FTA; the model of the fifth MOS tube 25 and the sixth MOS tube 26 is TPCA8123L1Q.
Specifically, the fourth resistor 14 of the present embodiment serves as a current limiting resistor; the third resistor 13, the fifth resistor 15, and the ninth resistor 19 are driving resistors; the sixth resistor 16, the seventh resistor 17, and the eighth resistor 18 serve as voltage dividing resistors; the second MOS tube 22, the third MOS tube 23 and the fourth MOS tube 24 are used as control MOS tubes; the fifth MOS tube 25 and the sixth MOS tube 26 are used as power MOS tubes; the tenth resistor 41 serves as a pull-up resistor; the eleventh resistor 42 and the twelfth resistor 43 serve as input resistors.
Specifically, when other power supplies 500 than the battery 100 supply power to the load 400, the first MOS transistor 21 is turned on, the battery 100 forms a loop with the first resistor 11 and the first MOS transistor 21, and the output of the battery 100 is turned off.
Specifically, when the load 400 is in the on state, the gate of the fourth MOS transistor 24 is grounded and turned on, at this time, the seventh resistor 17, the eighth resistor 18, the second MOS transistor 22, and the fourth MOS transistor 24 form a loop, and divide the output voltage of the battery, the fifth MOS transistor 25 and the sixth MOS transistor 26 are turned on and output, the master control unit 300 starts to work and is placed with a high power output control pin to make the third MOS transistor 23 always turned on, and at this time, the battery 100 is normally output as a power supply and is electrified. When the load 400 is in the off state, the main control unit 300 sets the power output control pin low so that the third MOS transistor 23 is always turned off, at this time, the fourth MOS transistor 24 is turned off, and the fifth MOS transistor 25 and the sixth MOS transistor 26 turn off the output, and prohibit the battery 100 from being output as a power source and powered down.
Specifically, when the key switch 80 of the present embodiment is pressed for the first time, the power-on/power-off management circuit forms a battery output control circuit and an on/power-off detection circuit, the key switch 80 and the second diode 52 and the twelfth resistor 43 form a circuit to form a battery output control circuit, the battery 100 is output as a power source to the main control unit 300 and works, the key switch 80 and the first diode 51 and the eleventh resistor 42 form a circuit to form an on/power-off detection circuit, the main control unit 300 detects an on/power-off signal to control the battery 100 as a power source to start power-on. When the key switch 80 is pressed again, the key switch 80, the first diode 51 and the eleventh resistor 42 form a loop to form an on/off detection loop, and at this time, the main control unit detects an on/off signal to control the battery 100 not to start powering down as a power source.
Specifically, the type of the key switch 80 of the present embodiment is SKSTAAE010/4N.
The above describes in detail an embodiment of a power up and down management circuit for controlling battery output. The principles and embodiments of the present utility model have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the core concepts of the utility model. It should be noted that it will be apparent to those skilled in the art that the present utility model may be modified and adapted without departing from the principles of the present utility model, and that such modifications and adaptations are intended to be within the scope of the appended claims.
Claims (10)
1. The power-on and power-off management circuit for controlling the output of the battery is characterized by comprising the battery (100), an output management circuit, a power control circuit, an acquisition unit, a main control unit (300) and a load (400); a first output end of the battery (100) is connected with an input end of the output management circuit; a second output end of the battery (100) is connected with an input end of the power control circuit; a first output of the power control circuit is connected to the load (400); the acquisition unit comprises a control end (202) and a detection end (201); the second output end of the power control circuit is connected with the control end (202) of the acquisition unit; the detection end (201) of the acquisition unit is connected with the input end of the main control unit (300); the output end of the main control unit (300) is connected with the second input end of the power control circuit.
2. The power-on/off management circuit according to claim 1, wherein the output management circuit comprises a first resistor (11), a second resistor (12), a first MOS transistor (21), and a power supply (500); the first output end of the battery (100) is connected with the drain electrode of the first MOS tube (21) and is connected with the first resistor (11) in series; the power supply (500) is connected with the grid electrode of the first MOS tube (21) and is connected with the second resistor (12) in series; the source electrode of the first MOS tube (21) is grounded.
3. The power up-down management circuit according to claim 2, wherein the power control circuit comprises a third resistor (13), a fourth resistor (14), a fifth resistor (15), a sixth resistor (16), a second MOS transistor (22), a third MOS transistor (23) and a fourth MOS transistor (24); a first node is arranged between the first resistor (11) and the drain electrode of the first MOS tube (21); the first node is connected with the grid electrode of the second MOS tube (22) and is connected with the third resistor (13) in series; the source electrode of the second MOS tube (22) is grounded;
the second output end of the battery (100) is connected with the drain electrode of the third MOS tube (23) and the fourth resistor (14) is connected in series between the second output end and the drain electrode of the third MOS tube; a second node is arranged between the fourth resistor (14) and the drain electrode of the third MOS tube (23); a third node is arranged between the control end (202) of the acquisition unit and the grid electrode of the fourth MOS tube (24); the second node is connected with the third node; the output end of the main control unit (300) is connected with the grid electrode of the third MOS tube (23) and is connected with the fifth resistor (15) in series; a fourth node is arranged between the fifth resistor (15) and the grid electrode of the third MOS tube (23); the fourth node is connected with the ground wire and is connected with the sixth resistor (16) in series; the source electrode of the third MOS tube (23) is grounded; and the drain electrode of the fourth MOS tube (24) is connected with the drain electrode of the second MOS tube (22).
4. A power up and down management circuit according to claim 3, characterized in that the power control circuit further comprises a seventh resistor (17), an eighth resistor (18); a fifth node is arranged between the second output end of the battery (100) and the fourth resistor (14); the fifth node is connected with the source electrode of the fourth MOS tube (24) and is connected with the seventh resistor (17) in series; the eighth resistor (18) is connected in series between the seventh resistor (17) and the source electrode of the fourth MOS tube (24).
5. The power up-down management circuit according to claim 4, wherein the power control circuit further comprises a ninth resistor (19), a fifth MOS transistor (25), and a sixth MOS transistor (26); a sixth node is arranged between the fifth node and the seventh resistor (17); the fifth MOS tube (25) and the sixth MOS tube (26) are connected in parallel between the sixth node and the load (400) respectively.
6. The power up and down management circuit of claim 5, wherein the sixth node comprises a first connection and a second connection; the first connecting end is connected with the source electrode of the fifth MOS tube (25); the second connecting end is connected with the source electrode of the sixth MOS tube (26); the load (400) comprises a third connection and a fourth connection; the drain electrode of the fifth MOS tube (25) is connected with the third connecting end; the drain electrode of the sixth MOS tube (26) is connected with the fourth connecting end;
a seventh node is arranged between the seventh resistor (17) and the eighth resistor (18); the seventh node comprises a fifth connecting end and a sixth connecting end; the fifth connecting end is connected with the grid electrode of the fifth MOS tube (25); the sixth connecting end is connected with the grid electrode of the sixth MOS tube (26).
7. The power up and down management circuit according to claim 6, wherein the acquisition unit comprises a key acquisition circuit; the key acquisition circuit comprises an input voltage (30), a tenth resistor (41), an eleventh resistor (42), a twelfth resistor (43), a first diode (51), a second diode (52) and a key switch (80); one end of the key switch (80) comprises a seventh connecting end and an eighth connecting end; the seventh connecting end is connected with the cathode of the first diode (51); the input voltage (30) and the positive electrode of the first diode (51) are connected and the tenth resistor (41) is connected in series; an eighth node is arranged between the tenth resistor (41) and the anode of the first diode (51); the eighth node is connected with the input end of the main control unit (300) and is connected with the eleventh resistor (42) in series;
the eighth connection terminal is connected with the cathode of the second diode (52); the anode of the second diode (52) and the third node are connected and the twelfth resistor (43) is connected in series between the anode and the third node.
8. The power-on and power-off management circuit according to claim 7, wherein the key acquisition circuit further comprises a first capacitor (61), a second capacitor (62) and a varistor (70); the other end of the key switch (80) is connected with a ground wire; the first capacitor (61), the second capacitor (62) and the piezoresistor (70) are connected in parallel between the other end of the key switch (80) and the ground wire.
9. The power-on and power-off management circuit according to claim 6, wherein the first MOS transistor (21), the second MOS transistor (22) and the third MOS transistor (23) are all N-MOS transistors; the fourth MOS tube (24), the fifth MOS tube (25) and the sixth MOS tube (26) are P-MOS tubes.
10. The power up-down management circuit according to claim 7, wherein the first diode (51) and the second diode (52) are anti-reflection diodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321239337.9U CN220325296U (en) | 2023-05-22 | 2023-05-22 | Power-on and power-off management circuit for controlling battery output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321239337.9U CN220325296U (en) | 2023-05-22 | 2023-05-22 | Power-on and power-off management circuit for controlling battery output |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220325296U true CN220325296U (en) | 2024-01-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321239337.9U Active CN220325296U (en) | 2023-05-22 | 2023-05-22 | Power-on and power-off management circuit for controlling battery output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220325296U (en) |
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2023
- 2023-05-22 CN CN202321239337.9U patent/CN220325296U/en active Active
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