CN212969439U

CN212969439U - Low-power-consumption circuit for quickly powering off chip in standby mode

Info

Publication number: CN212969439U
Application number: CN202021859346.4U
Authority: CN
Inventors: 彭洪松; 李洪斌; 胡军; 税国梅; 卿春梅; 吴凯
Original assignee: Sichuan Jiuzhou Electronic Technology Co Ltd
Current assignee: Sichuan Jiuzhou Electronic Technology Co Ltd
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2021-04-13
Anticipated expiration: 2030-08-31

Abstract

The utility model discloses a make chip standby low-power consumption circuit of unloading fast, including power, switch control circuit, load switch control circuit and system's back stage circuit's equivalent resistance R5 and equivalent capacitance C2, switch control circuit is used for control load switch control circuit, equivalent resistance R5 and equivalent capacitance C2 with the switch-on or the disconnection of power, load switch control circuit include load resistance R2, load resistance R2 ground connection, load resistance R2 connects triode Q2's projecting pole, triode Q2's collecting electrode ground connection, current-limiting resistance R4's first end is connected to the base, current-limiting resistance R4's second end and switch control circuit's control signal input end connects. The dynamic control of the load is realized through the circuit: the load is disconnected during working, so that the power consumption of the whole machine is not influenced; and the circuit is quickly responded and conducted in standby, so that the load resistor is connected into the circuit, the residual electric quantity in the circuit is consumed, and the power supply of the circuit is quickly powered off.

Description

Low-power-consumption circuit for quickly powering off chip in standby mode

Technical Field

The utility model relates to the field of electronic technology, specific theory is a make chip standby low-power consumption circuit that cuts off electricity fast.

Background

At present, the speed of a chip system is higher and higher, the capacity of matching DDR and Flash is larger and larger, and a peripheral power supply circuit is also more and more complex. A common chip system needs a plurality of groups of power supplies to supply power in a coordinated manner, and the timing requirements exist in the coordination of the plurality of groups of power supplies. For example, "after the CPU voltage of the main chip (or SOC chip) is 3.3V and the voltage must be reduced to 1.2V, the GPU voltage of the main chip (or SOC chip) can be reduced again," "low voltage is reduced first, and power is reduced after 3.3V. If the power-off time sequence of the chip does not meet the requirement, the chip system is repeatedly restarted, the standby screen flashing is carried out, the chip is halted and even the chip is damaged, and the like.

The power-off time sequence of the existing chip system is generally adjusted by the following two schemes;

firstly, a single chip microcomputer system is added on the periphery, the single chip microcomputer respectively controls an enabling signal of each power supply, and the on-off time of each power supply is controlled, so that the adjustment of the power-on and power-off time sequence is realized; the scheme adopts the singlechip which has high cost and needs to develop programs, thereby increasing the cost and the technical stability of the whole machine.

Secondly, a load resistor is added to the power supply to realize rapid power-off of a part of the power supply in a standby state, and the circuit resistor R2 is a load resistor according to the principle shown in FIG. 1. When the STANDBY time control signal STANDBY _ PWROFF is at a low level, the MOS tube Q1 is turned off, the disconnection of the 3V3_ MOS and the 3V3_ MOS _ CPU is realized, the resistor R2 is used as a load, the residual electric energy in the 3.3V _ MOS _ CPU is quickly consumed, and the purpose of quickly powering off the circuit power supply is achieved. But in the normal working state of the host, the resistor R2 still consumes a large amount of energy as a load resistor; taking the resistance R2 equal to 100 ohms and the device operating 8 hours a day as an example, the load resistance power is 0.1W, which will increase the power of the whole machine by 0.1W in the operating and standby states, and one device will consume more power 292WH a year, resulting in serious waste of resources.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a make the low-power consumption circuit of chip standby power down fast for increase load resistance mode among the solution prior art and realize leading to the great problem of normal operating condition power consumption when the power standby is power down fast.

The utility model discloses a following technical scheme solves above-mentioned problem:

the utility model provides a make chip standby low-power consumption circuit that drops electricity fast, includes power, switch control circuit, load switch control circuit and system back stage circuit's equivalent resistance R5 and equivalent capacitance C2, switch control circuit is used for controlling load switch control circuit, equivalent resistance R5 and equivalent capacitance C2 with the switch-on or the disconnection of power, load switch control circuit include load resistance R2, load resistance R2 ground connection, connect triode Q2's projecting pole between load resistance R2 and the ground connection, triode Q2's collecting electrode ground connection, triode Q2's base connect current-limiting resistance R4's first end, current-limiting resistance R4's second end and switch control circuit's control signal input end connects.

When the equipment works, a high level is input at the input end of a control signal, the power switch control circuit is conducted, the load switch control circuit and a system rear-stage circuit are electrified, and meanwhile, because the triode Q2 in the load switch control circuit is turned off, the load resistor R2 does not work, so that the power consumption of the whole machine is not influenced; when the equipment is in standby, the input end of the control signal is converted from high level to low level, the power switch control circuit is turned off, the load switch control circuit, the system rear-stage circuit and the power supply end are turned on, the equivalent energy storage capacitor C2 of the system rear-stage circuit stores a large amount of electricity at the moment of power failure, at the moment, the triode Q2 in the load switch control circuit is rapidly conducted, the load resistor R2 is connected into the circuit to work, and the residual electric energy of the system rear-stage circuit is rapidly consumed. When the two ends of the current-limiting resistor R4 are connected in parallel with the accelerating capacitor C1, the saturation conduction time of the triode Q2 is shortened, and the load resistor R2 is connected into the circuit quickly. The utility model solves the problem that the power supply of the traditional circuit is very slow in power-down speed if only depending on the consumption of the equivalent resistance R5 of the post-stage circuit of the system; and the problem of resource waste is caused by increasing the power consumption of the whole machine by increasing the large load resistor R2 in the traditional mode.

The power switch control circuit comprises a control signal input end, a resistor R3, a triode Q3, a resistor R1 and an MOS transistor Q1, wherein the first end of the resistor R3 is connected with the control signal input end, the second end of the resistor R3 is connected with the base of the triode Q3, the collector of the triode Q3 is respectively connected with the first end of the resistor R1 and the grid of the MOS transistor Q1, the second end of the resistor R1 is connected with the source of the MOS transistor Q1, and the drain of the MOS transistor Q1 is connected with the load resistor R2, the equivalent resistor R5 and the equivalent capacitor C2.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

the utility model provides a make the low-power consumption circuit of chip standby power down fast, realize the dynamic control to the load through this circuit: the load is disconnected during working, so that the power consumption of the whole machine is not influenced; and the circuit is quickly responded and conducted in standby, so that the load resistor is connected into the circuit, the residual electric quantity in the circuit is consumed, and the power supply of the circuit is quickly powered off.

Drawings

FIG. 1 is a schematic diagram of a prior art power-down sequence circuit of a chip;

FIG. 2 is a schematic circuit diagram of the present invention;

fig. 3 is a timing diagram.

Detailed Description

The present invention will be described in further detail with reference to examples, but the present invention is not limited thereto.

Example (b):

referring to fig. 2, a low power consumption circuit for enabling a chip to be in standby and rapidly powered down includes a power supply, a power switch control circuit, a load switch control circuit, an equivalent resistor R5 and an equivalent capacitor C2 of a system back-stage circuit, wherein the power switch control circuit is used for controlling the load switch control circuit, the equivalent resistor R5 and the equivalent capacitor C2 to be connected with or disconnected from the power supply, the load switch control circuit includes a load resistor R2, a load resistor R2 is grounded, an emitter of a triode Q2 is connected between the load resistor R2 and the ground, a collector of the triode Q2 is grounded, a base of the triode Q2 is connected with a first end of a current-limiting resistor R4, and a second end of the current-limiting resistor R4 is connected with a control signal input end of the power switch control circuit.

The equivalent resistor R5 is used as the equivalent load of the system rear-stage circuit, and the equivalent capacitor C2 is used as the equivalent energy storage capacitor of the system rear-stage circuit; the resistor R3, the triode Q3, the resistor R1 and the MOS transistor Q1 form a power switch control circuit; the acceleration capacitor C1, the load resistor R2, the current limiting resistor R4 and the triode Q2 form a load switch control circuit; the control signal STANDBY _ PWROFF is connected with the base of the transistor Q3 and the base of the transistor Q2 through a current-limiting resistor R4, and controls the on and off of the power switch control circuit and the load switch control circuit, wherein U0 is the voltage of the control signal STANDBY _ PWROFF, Ub is the base voltage of the transistor Q2, and Ue is the emitter voltage of the transistor Q2.

When the STANDBY circuit is in STANDBY, the control signal STANDBY _ PWROFF is at low level, the voltage U0 is approximately equal to 0, the triode Q2 is conducted, the emitter voltage Ue of the triode Q2 is approximately equal to 3.3V, the voltage U0 of the control signal STANDBY _ PWROFF is approximately equal to 0V, and the delta Ube is approximately equal to 0.7V, namely, the delta U (R2) is approximately equal to 2.6V; the circuit divides voltage through a current limiting resistor R4, and prevents the transistor Q2 from being burnt by overlarge current.

The acceleration capacitor C1 is used as an acceleration capacitor of a load switch control circuit triode Q2, and the working principle is as follows:

(1) at the stage t0-t1, the control signal STANDBY _ PWROFF is at a high level, when the voltage U0 is approximately equal to 3.3V, and the voltage U0 is approximately equal to Ue, when the circuit reaches a steady state, the triode Q2 is cut off, and the polarity of the voltage at the two ends of the acceleration capacitor C1 is positive left and negative right.

(2) At t1, at the instant when the control signal STANDBY _ PWROFF changes from high to low, the voltage difference across the accelerating capacitor C1 cannot change suddenly due to the charge storage effect of the capacitor, the polarity of the voltage originally charged in the accelerating capacitor Cl is positive left and negative right, and the voltage applied to the base of the transistor Q2 is a negative spike, as shown in fig. 3. The voltage Ub of the base electrode of the triode Q2 is a negative sharp-top pulse, so that the process that the Ub draws charges from the base region is accelerated, the current of the base electrode of the triode Q2 is rapidly increased from 0 to a large value, the triode Q2 rapidly enters a saturation state from a cut-off state, the saturation conduction of the triode Q2 is accelerated, and the saturation conduction time of the triode Q2 (the time required by the triode to enter saturation from cut-off) is shortened. The triode Q2 is conducted rapidly, so that the load resistor R2 is connected into the circuit rapidly, and the discharging effect is achieved.

(3) At the stage t1-t3, the discharging process of the capacitor C1 is accelerated, the base voltage Ub of the triode Q2 is pulsed to the U0, and finally, the base voltage Ub is maintained in the dc steady state of the U0, the saturation conduction state of the triode Q2 is maintained, and the steady state is maintained at the two ends of the capacitor.

(4) At t3, at the instant when the control signal STANDBY _ PWROFF changes from low to high, the polarity of the voltage originally charged on the accelerating capacitor Cl is negative left to positive right at the time of t1-t3 due to the charge storage effect of the capacitor, and the voltage applied to the base of the transistor Q2 is a positive spike, as shown in fig. 3. The voltage Ub of the base of the transistor Q2 is positive spike pulse, and Ub is more than Ue, so that the transistor Q2 is converted into a cut-off state from saturation at a higher speed, namely, the time for converting the transistor Q2 into the cut-off state is shortened.

(5) In the stage t3-t4, the charging process of the accelerating capacitor C1 is started, the base voltage Ub of the triode Q2 is gradually reduced to U0 in a pulse mode, the high-level direct-current steady state of the U0 is maintained finally, and the triode Q2 is maintained in a cut-off state, so that the load resistor R2 has no loop current, and the power consumption is reduced.

The utility model discloses an increase electric capacity with higher speed, load switch control circuit switching speed is showing and is promoting.

The transistor Q2 is used as a switching transistor of the load switch control circuit, and the working principle is as follows:

(1) when the power supply works, the control signal STANDBY _ PWROFF is in a high level, the triode Q3 is conducted, the Q1 is turned on, and the 3.3V _ MOS _ CPU node is electrified; meanwhile, the switching transistor Q2 is turned off, and the load resistor R2 does not work.

(2) When the STANDBY mode is in use, the control signal STANDBY _ PWROFF is in a low level, the triode Q3 is turned off, the MOS tube Q1 is turned off, and the 3.3V power supply and the node 3.3V _ MOS _ CPU are disconnected; meanwhile, the triode Q2 is conducted, the load resistor R2 works, and residual electric energy in the node 3.3V _ MOS _ CPU (namely a system rear-stage circuit) is consumed rapidly.

The load resistor R2 is used as a load resistor of the load switch control circuit, and the working principle is as follows:

when the load switch control circuit is conducted, the load resistor R2 is used as a large load of the power supply 3.3V _ MOS _ CPU, and residual electric energy in the circuit is converted into heat energy; according to the formula P ═ U²and/R, taking R2 equal to 100 ohms as an example, the power of the large load resistor is 0.1W, and the purpose of quickly dissipating energy and quickly powering down the power supply can be achieved.

The scheme is not only suitable for chips and chip systems, but also suitable for low-power-consumption designs of other equipment.

Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are merely preferred embodiments of the present invention, it is to be understood that the present invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.

Claims

1. The utility model provides a make chip standby low-power consumption circuit that cuts off electricity fast, includes power, switch control circuit, load switch control circuit and system back stage circuit's equivalent resistance R5 and equivalent capacitance C2, switch control circuit is used for controlling load switch control circuit, equivalent resistance R5 and equivalent capacitance C2 with the switch-on or disconnection of power, load switch control circuit include load resistance R2, load resistance R2 ground connection, characterized in that, connect the projecting pole of triode Q2 between load resistance R2 and the ground connection, triode Q2's collector ground connection, the first end of current-limiting resistance R4 is connected to triode Q2's base, the second end of current-limiting resistance R4 and switch control circuit's control signal input end is connected.

2. The circuit of claim 1, wherein the current limiting resistor R4 is connected in parallel with an accelerating capacitor C1.

3. The circuit of claim 1 or 2, wherein the power switch control circuit comprises a control signal input terminal, a resistor R3, a transistor Q3, a resistor R1 and a MOS transistor Q1, a first terminal of the resistor R3 is connected to the control signal input terminal, a second terminal of the resistor R3 is connected to a base of the transistor Q3, a collector of the transistor Q3 is connected to a first terminal of the resistor R1 and a gate of the MOS transistor Q1, a second terminal of the resistor R1 and a source of the MOS transistor Q1 are connected to the power supply, and a drain of the MOS transistor Q1 is connected to the load resistor R2, the equivalent resistor R5 and the equivalent capacitor C2.