CN219247705U - Charge discharging circuit, system, motor driver and vehicle - Google Patents
Charge discharging circuit, system, motor driver and vehicle Download PDFInfo
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- CN219247705U CN219247705U CN202223543608.8U CN202223543608U CN219247705U CN 219247705 U CN219247705 U CN 219247705U CN 202223543608 U CN202223543608 U CN 202223543608U CN 219247705 U CN219247705 U CN 219247705U
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- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
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Abstract
The application discloses a charge discharging circuit, a system, a motor driver and a vehicle, and relates to the technical field of circuits, wherein a base electrode of an NPN triode in the circuit is connected with an anode of a low-voltage power supply end, an emitter electrode of the NPN triode is used for being connected with a cathode of the low-voltage power supply end, and a collector electrode of the NPN triode is connected with a first end of a first resistor; the second end of the second resistor is connected with the positive electrode of the high-voltage capacitor; the grid electrode of the second PMOS tube is connected with the second end of the first resistor, the source electrode of the second PMOS tube is connected with the positive electrode of the high-voltage capacitor, and the drain electrode of the second PMOS tube is connected with the first end of the third resistor; the grid electrode of the first PMOS tube is connected with the first end of the third resistor, the source electrode of the first PMOS tube is connected with the positive electrode of the high-voltage capacitor, the drain electrode of the first PMOS tube is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the negative electrode of the high-voltage capacitor. The circuit can reduce power consumption and cost.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a charge discharging circuit, a system, a motor driver and a vehicle.
Background
The charge discharging circuit is used for discharging the charge stored in the high-voltage capacitor. Two types of charge draining circuits are provided in the prior art, each of which is described below.
First kind: and a high-power resistor is connected in parallel at the high-voltage capacitor side to discharge charges. The parallel connection mode can lead to that when the circuit board is normally electrified, the high-power resistor also works, and the power consumption is high and the heat is much.
Second kind: a buck chip is utilized. After the circuit board is electrified, the voltage reducing chip takes electricity from the high-voltage side, the post-stage charge discharging circuit is driven to work, and after the circuit board is electrified, the post-stage charge discharging circuit is closed, but the cost of the voltage reducing chip is higher, pins of the singlechip are occupied, and resource waste is caused.
Disclosure of Invention
The application provides a charge discharging circuit, a system, a motor driver and a vehicle, which can discharge charges with lower cost and lower power consumption.
In order to achieve the above purpose, the present application adopts the following technical scheme:
in a first aspect, the present application provides a charge bleed circuit comprising: the first PMOS tube, the second PMOS tube, the NPN triode, the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor;
the base electrode of the NPN type triode is used for being connected with the positive electrode of the low-voltage power supply end, the voltage of the low-voltage power supply end is smaller than a first preset threshold value, the emitter electrode of the NPN type triode is used for being connected with the negative electrode of the low-voltage power supply end, and the collector electrode of the NPN type triode is used for being connected with the first end of the first resistor;
the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the positive electrode of the high-voltage capacitor;
the grid electrode of the second PMOS tube is connected with the second end of the first resistor, the source electrode of the second PMOS tube is connected with the positive electrode of the high-voltage capacitor, and the drain electrode of the second PMOS tube is connected with the first end of the third resistor;
the first end of the third resistor is connected with the first end of the fourth resistor, and the second end of the third resistor is connected with the positive electrode of the high-voltage capacitor; the second end of the fourth resistor is connected with the negative electrode of the high-voltage capacitor;
the grid electrode of the first PMOS tube is connected with the first end of the third resistor, the source electrode of the first PMOS tube is connected with the positive electrode of the high-voltage capacitor, the drain electrode of the first PMOS tube is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the negative electrode of the high-voltage capacitor.
In some possible implementations, the charge draining circuit further includes: a first zener diode;
the cathode of the first zener diode is connected with the positive electrode of the high-voltage capacitor, and the anode of the first zener diode is connected with the grid electrode of the first PMOS tube.
In some possible implementations, the charge draining circuit further includes: a second zener diode;
and the cathode of the second zener diode is connected with the positive electrode of the high-voltage capacitor, and the anode of the second zener diode is connected with the first end of the second resistor.
In some possible implementations, the charge bleed circuit further includes a sixth resistor;
the base of NPN triode is used for connecting the anodal of low pressure power supply end, includes:
and the base electrode of the NPN triode is connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with the positive electrode of the low-voltage power supply end.
In some possible implementations, the charge bleed circuit further includes a seventh resistor;
the first end of the seventh resistor is connected with the base electrode of the NPN triode, and the second end of the seventh resistor is connected with the emission set of the NPN triode.
In some possible implementations, the first resistor has a resistance value of 300-500 ohms.
In a second aspect, the present application provides a charge draining system comprising a charge draining circuit according to any one of the first aspects above.
In a third aspect, the present application provides a motor drive comprising a charge bleed circuit as claimed in any one of the first aspects above.
In a fourth aspect, the present application provides a vehicle comprising a charge bleed circuit as defined in any one of the first aspects above.
The technical scheme of the application has the following beneficial effects:
in the application, after the low-voltage power supply end (circuit board) is electrified, the NPN triode is conducted, the second PMOS tube is conducted, and the first PMOS tube is cut off, so that no current flows in the fifth resistor (bleeder resistor), namely, the bleeder resistor does not generate loss in the normal working process of the low-voltage power supply end, and further the loss is reduced; after the low-voltage power supply end is powered down, the NPN triode is cut off, the second PMOS tube is cut off, and the first PMOS tube is conducted, so that current flows through the fifth resistor, namely, charges in the high-voltage capacitor are discharged through the discharge resistor, a voltage reduction chip is not needed, and cost is reduced.
It should be appreciated that the description of technical features, aspects, benefits or similar language in this application does not imply that all of the features and advantages may be realized with any single embodiment. Conversely, it should be understood that the description of features or advantages is intended to include, in at least one embodiment, the particular features, aspects, or advantages. Therefore, the description of technical features, technical solutions or advantageous effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and advantageous effects described in the present embodiment may also be combined in any appropriate manner. Those of skill in the art will appreciate that an embodiment may be implemented without one or more particular features, aspects, or benefits of a particular embodiment. In other embodiments, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments.
Drawings
Fig. 1 is a schematic diagram of a charge draining circuit according to an embodiment of the present application.
Detailed Description
The terms first, second, third and the like in the description and in the claims and drawings are used for distinguishing between different objects and not for limiting the specified sequence.
In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
For clarity and conciseness in the description of the following embodiments, a brief description of the related art will be given first:
the charge discharging circuit is used for discharging the charge stored in the high-voltage capacitor, and currently, the charge stored in the high-voltage capacitor is discharged in two modes.
In the first mode, a high-power resistor is connected in parallel to the high-voltage capacitor side, and in the second mode, a voltage reduction chip is utilized, and after the circuit board is powered down, power is taken from the high-voltage side to drive a later-stage charge discharging circuit to work.
In the first mode, after the circuit board is electrified, the high-power resistor is in a working state, so that unnecessary resource waste can be caused, and in the second mode, the price of the voltage reduction chip is relatively high, and the cost is relatively high.
In view of this, an embodiment of the present application provides a charge draining circuit, which includes a first PMOS transistor, a second PMOS transistor, an NPN transistor, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; the base electrode of the NPN type triode is used for being connected with the positive electrode of the low-voltage power supply end, the voltage of the low-voltage power supply end is smaller than a first preset threshold value, the emitter electrode of the NPN type triode is used for being connected with the negative electrode of the low-voltage power supply end, and the collector electrode of the NPN type triode is used for being connected with the first end of the first resistor; the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the positive electrode of the high-voltage capacitor; the grid electrode of the second PMOS tube is connected with the second end of the first resistor, the source electrode of the second PMOS tube is connected with the positive electrode of the high-voltage capacitor, and the drain electrode of the second PMOS tube is connected with the first end of the third resistor; the first end of the third resistor is connected with the first end of the fourth resistor, and the second end of the third resistor is connected with the positive electrode of the high-voltage capacitor; the second end of the fourth resistor is connected with the negative electrode of the high-voltage capacitor; the grid electrode of the first PMOS tube is connected with the first end of the third resistor, the source electrode of the first PMOS tube is connected with the positive electrode of the high-voltage capacitor, the drain electrode of the first PMOS tube is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the negative electrode of the high-voltage capacitor.
In the charge bleeder circuit, after a low-voltage power supply end (circuit board) is electrified, an NPN triode is conducted, a second PMOS tube is conducted, and a first PMOS tube is cut off, so that no current flows in a fifth resistor (bleeder resistor), namely, the bleeder resistor does not generate loss in the normal working process of the low-voltage power supply end, and further the loss is reduced; after the low-voltage power supply end is powered down, the NPN triode is cut off, the second PMOS tube is cut off, and the first PMOS tube is conducted, so that current flows through the fifth resistor, namely, charges in the high-voltage capacitor are discharged through the discharge resistor, a voltage reduction chip is not needed, and cost is reduced.
In order to make the technical scheme of the application clearer and easier to understand, the technical scheme of the application is described below with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of a charge draining circuit according to an embodiment of the present application.
The charge bleed circuit includes: the first PMOS tube M1, the second PMOS tube M2, the NPN triode Q2, the first resistor R5, the second resistor R4, the third resistor R6, the fourth resistor R3, the fifth resistor R1, the first zener diode D1, the second zener diode D2, the sixth resistor R7 and the seventh resistor R2.
The base electrode of the NPN triode Q2 is used for connecting the positive electrode of the low-voltage power supply end 100, and the voltage of the low-voltage power supply end 100 is smaller than a first preset threshold value; the first preset threshold may be 5V, 6V, etc. The low voltage power terminal 100 may be a circuit board power terminal.
The emitter of the NPN transistor Q2 is connected to the negative electrode of the low voltage power supply terminal 100, and the collector of the NPN transistor Q2 is connected to the first end of the first resistor R5.
The second end of the first resistor R5 is connected with the first end of the second resistor R4, and the second end of the second resistor R4 is connected with the positive electrode of the high-voltage capacitor C.
The grid electrode of the second PMOS tube M2 is connected with the second end of the first resistor R5, the source electrode of the second PMOS tube M2 is connected with the positive electrode of the high-voltage capacitor C, and the drain electrode of the second PMOS tube M2 is connected with the first end of the third resistor R6.
The first end of the third resistor R6 is connected with the first end of the fourth resistor R3, and the second end of the third resistor R6 is connected with the positive electrode of the high-voltage capacitor C; the second end of the fourth resistor R3 is connected to the negative electrode of the high voltage capacitor C.
The grid of the first PMOS tube M1 is connected with the first end of the third resistor R6, the source electrode of the first PMOS tube M1 is connected with the positive electrode of the high-voltage capacitor C, the drain electrode of the first PMOS tube M1 is connected with the first end of the fifth resistor R1, and the second end of the fifth resistor R1 is connected with the negative electrode of the high-voltage capacitor C.
In the application, after the low-voltage power supply end (circuit board) is electrified, the NPN triode Q2 is conducted, the second PMOS tube M2 is conducted, and the first PMOS tube M1 is cut off, so that no current flows in the fifth resistor R1 (bleeder resistor), namely, the bleeder resistor does not generate loss in the normal working process of the low-voltage power supply end, and further the loss is reduced; after the low-voltage power supply end is powered down, the NPN triode Q2 is cut off, the second PMOS tube M2 is cut off, and the first PMOS tube M1 is turned on, so that current flows through the fifth resistor R1, namely, charges in the high-voltage capacitor C are discharged through the discharging resistor, a voltage reduction chip is not needed, and cost is reduced.
The cathode of the first zener diode D1 is connected with the positive electrode of the high-voltage capacitor C, and the anode of the first zener diode D1 is connected with the grid electrode of the first PMOS tube M1. The first zener diode D1 may be BZX84C12L, and the voltage stabilizing value of the first zener diode D1 may be 12V.
The cathode of the second zener diode D2 is connected to the positive electrode of the high voltage capacitor C, and the anode of the second zener diode D2 is connected to the first end of the second resistor R4. The second zener diode D2 may be BZX84C12L, and the voltage stabilizing value of the second zener diode D2 may be 12V.
The base electrode of the NPN transistor Q3 is connected to the positive electrode of the low voltage power supply terminal 100, and specifically may be:
the base of NPN transistor Q3 is connected to the first end of sixth resistor R7, and the second end of sixth resistor R7 is connected to the positive pole of low voltage supply terminal 100.
The first end of the seventh resistor R2 is connected with the base electrode of the NPN triode Q2, and the second end of the seventh resistor R2 is connected with the emission set of the NPN triode Q2.
In some embodiments, the resistance of the fifth resistor R1 may be 300-500 ohms, and preferably, the resistance of the fifth resistor R1 is 400 ohms.
The high voltage capacitor C may be a high voltage capacitor connected in parallel to two ends of the power battery, after the whole vehicle is powered down, that is, after the low voltage power supply terminal 100 stops supplying power, the initial voltage of two ends of the high voltage capacitor C is greater than a second preset threshold, the second preset threshold may be 100V, and generally, the initial voltage of two ends of the high voltage capacitor C is 110V.
In the application, a two-stage PMOS driving circuit is adopted, the short circuit of the two-stage PMOS driving circuit is realized through the one-stage PMOS tube, the automatic closing of the low-voltage power supply end during power-on and the automatic power taking of the high-voltage side after power-down are realized, a voltage stabilizing power supply chip is not required to be adopted in a power taking mode, and the switching of the whole charge discharging circuit can be completed only by collecting a high-voltage signal through resistor voltage division. It can be seen that not only is the cost reduced, but also the power consumption is reduced.
The embodiment of the application also provides a charge draining system, which comprises the charge draining circuit of any one of the embodiments.
In a third aspect, the present application provides a motor drive comprising the charge draining circuit of any one of the above embodiments.
In a fourth aspect, the present application provides a vehicle comprising the charge draining circuit of any one of the above embodiments.
It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the present application in any way. While the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Many possible variations and modifications may be made to the disclosed technology by anyone skilled in the art, or equivalent embodiments may be made, without departing from the scope of the technology of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application, which do not depart from the content of the technical solution of the present application, still fall within the scope of protection of the technical solution of the present application.
Claims (10)
1. A charge bleed circuit, comprising: the first PMOS tube, the second PMOS tube, the NPN triode, the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor;
the base electrode of the NPN type triode is used for being connected with the positive electrode of the low-voltage power supply end, the voltage of the low-voltage power supply end is smaller than a first preset threshold value, the emitter electrode of the NPN type triode is used for being connected with the negative electrode of the low-voltage power supply end, and the collector electrode of the NPN type triode is used for being connected with the first end of the first resistor;
the second end of the first resistor is connected with the first end of the second resistor, and the second end of the second resistor is connected with the positive electrode of the high-voltage capacitor;
the grid electrode of the second PMOS tube is connected with the second end of the first resistor, the source electrode of the second PMOS tube is connected with the positive electrode of the high-voltage capacitor, and the drain electrode of the second PMOS tube is connected with the first end of the third resistor;
the first end of the third resistor is connected with the first end of the fourth resistor, and the second end of the third resistor is connected with the positive electrode of the high-voltage capacitor; the second end of the fourth resistor is connected with the negative electrode of the high-voltage capacitor;
the grid electrode of the first PMOS tube is connected with the first end of the third resistor, the source electrode of the first PMOS tube is connected with the positive electrode of the high-voltage capacitor, the drain electrode of the first PMOS tube is connected with the first end of the fifth resistor, and the second end of the fifth resistor is connected with the negative electrode of the high-voltage capacitor.
2. The charge draining circuit of claim 1, further comprising: a first zener diode;
the cathode of the first zener diode is connected with the positive electrode of the high-voltage capacitor, and the anode of the first zener diode is connected with the grid electrode of the first PMOS tube.
3. The charge draining circuit according to claim 1 or 2, further comprising: a second zener diode;
and the cathode of the second zener diode is connected with the positive electrode of the high-voltage capacitor, and the anode of the second zener diode is connected with the first end of the second resistor.
4. The charge draining circuit of claim 1, further comprising a sixth resistor;
the base of NPN triode is used for connecting the anodal of low pressure power supply end, includes:
and the base electrode of the NPN triode is connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with the positive electrode of the low-voltage power supply end.
5. The charge draining circuit of claim 1, further comprising a seventh resistor;
the first end of the seventh resistor is connected with the base electrode of the NPN triode, and the second end of the seventh resistor is connected with the emission set of the NPN triode.
6. The charge bleed circuit of claim 1, wherein the first resistor has a resistance of 300-500 ohms.
7. The charge draining circuit of claim 1, wherein an initial voltage across the high voltage capacitor is greater than a second predetermined threshold after the low voltage supply terminal ceases to supply power.
8. A charge draining system comprising the charge draining circuit of any one of claims 1-7.
9. A motor drive comprising the charge bleed circuit of any of claims 1-7.
10. A vehicle comprising a charge bleed circuit as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223543608.8U CN219247705U (en) | 2022-12-21 | 2022-12-21 | Charge discharging circuit, system, motor driver and vehicle |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223543608.8U CN219247705U (en) | 2022-12-21 | 2022-12-21 | Charge discharging circuit, system, motor driver and vehicle |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219247705U true CN219247705U (en) | 2023-06-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223543608.8U Active CN219247705U (en) | 2022-12-21 | 2022-12-21 | Charge discharging circuit, system, motor driver and vehicle |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219247705U (en) |
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2022
- 2022-12-21 CN CN202223543608.8U patent/CN219247705U/en active Active
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