CN103957002A - Grid voltage bootstrapping xor/xnor circuit and grid voltage bootstrapping single-bit full adder - Google Patents

Abstract

The invention discloses a grid voltage bootstrapping XOR/simultaneous OR circuit and a grid voltage bootstrapping one-bit full adder composed of a summation signal generating circuit and a carry signal generating circuit, which is characterized in that the grid voltage bootstrapping XOR/ The NOR circuit includes a grid voltage bootstrap NOR generation circuit and an inverter, wherein the grid voltage bootstrap NOR generation circuit is composed of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The transistor and the fourth NMOS transistor are composed of a special connection method; the advantage is that the XOR/NOR circuit is connected into a gate voltage bootstrap circuit structure, and the gate bootstrap effect improves the performance of the third NMOS transistor or the fourth NMOS transistor. Gate voltage, so that the high level passes through the first NMOS tube or the second NMOS tube smoothly, and the circuit output reaches the full swing, which improves the ability to drive the next stage and increases the operating speed of the overall circuit; the full swing is reduced The leakage power consumption of the circuit is reduced, the performance of the circuit is improved, and finally the delay, power consumption and power consumption-delay product of the whole circuit are effectively reduced.

Description

A grid voltage bootstrap XOR/XOR circuit and a grid voltage bootstrap one-bit full adder

technical field

The invention relates to an exclusive OR circuit, in particular to a gate voltage bootstrap exclusive OR/simultaneous OR circuit and a gate voltage bootstrap one-bit full adder.

Background technique

The XOR gate is one of the most widely used gate circuits, and it is often required to design it with low power consumption.

As the basic computing unit of electronic systems, the full adder is widely used in many VLSI systems. For example, in high-performance microprocessors and DSP processors, the computing power of a full adder is very important. The operation of a full adder is often in the critical path of high-performance processor system components, especially in the arithmetic logic unit, the operation performance of a full adder plays a very critical role in the performance of the processor. As microprocessors become faster and faster, the demand for fast one-bit full adders is also increasing. Its speed, power consumption, and area performance will directly affect the overall performance of the entire integrated circuit.

Delay, power consumption, and power consumption-delay product are the main three factors that reflect the performance of a full adder. Optimizing these three factors can optimize the performance of the full adder and improve the performance of the overall system. Among them, power consumption- The delay product is the product of power consumption and delay, and the unit is joules. Therefore, the power consumption-delay product is a measure of energy and can be used as a measure of the performance of a switching device. Many scholars have proposed a variety of one-bit full adders using different logics (see A.M. Shams, T.K. Darwish and M.A. Bayoumi, "Performance analysis of low-power 1-bit CMOS full adder cells," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, 2002, pp 20-29.), although these one-bit full adders have certain effects, they also have obvious shortcomings. First, there is threshold voltage loss and non-full swing output; Second, the power consumption or the power consumption-delay product is relatively large.

Contents of the invention

The technical problem to be solved by the present invention is to provide a grid voltage bootstrap XOR/XOR circuit and a grid voltage bootstrap one-bit full adder with smaller circuit delay, power consumption and power consumption-delay product.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a grid voltage bootstrap NOR/NOR circuit, including a grid voltage bootstrap NOR generation circuit and an inverter, and the grid voltage bootstrap NOR generation circuit The circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor, the source of the first PMOS transistor is connected to the positive pole of an external power supply, and the The drain of the first PMOS transistor is connected to the source of the second PMOS transistor, and the gate of the first PMOS transistor is respectively connected to the source of the first NMOS transistor and the third The source of the NMOS transistor is connected, the substrate of the second PMOS transistor is connected to the positive pole of the external power supply, the gate of the second PMOS transistor is connected to the source of the second NMOS transistor and the The source of the fourth NMOS transistor is connected, and the drain of the second PMOS transistor is respectively connected to the drain of the first NMOS transistor, the drain of the second NMOS transistor and the inverter. The input terminals are connected, the drain of the second PMOS transistor is used as the NOR output terminal of the gate voltage bootstrap XOR/NOR circuit, and the output terminal of the inverter is used as the grid voltage bootstrap XOR/Same OR The XOR output end of the circuit, the gate of the first NMOS transistor is connected to the drain of the fourth NMOS transistor, the substrate of the first NMOS transistor is grounded, and the gate of the third NMOS transistor is connected to the ground. The gate is connected to the anode of the external power supply, the drain of the third NMOS transistor is connected to the gate of the second NMOS transistor, the substrate of the second NMOS transistor is grounded, and the fourth NMOS transistor is grounded. The grid of the tube is connected to the positive pole of the external power supply.

The inverter includes a third PMOS transistor and a fifth NMOS transistor, the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor and the gate of the fifth NMOS transistor respectively connected, the source of the third PMOS transistor is connected to the positive pole of the external power supply, the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, and the drain of the third PMOS transistor The drain serves as the exclusive OR output terminal of the gate voltage bootstrap exclusive OR/simultaneous OR circuit, and the source of the fifth NMOS transistor is grounded.

The grid voltage bootstrap one-bit full adder composed of the above-mentioned grid voltage bootstrap XOR/NOR circuit includes a grid voltage bootstrap XOR/XOR circuit, a sum signal generation circuit and a carry signal generation circuit, the described The sum signal generating circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, and the carry signal generating circuit includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, and a seventh NMOS transistor. Nine NMOS transistors, the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, the source of the fifth PMOS transistor, the gate of the eighth NMOS transistor and the gate of the eighth NMOS transistor. The gate of the seventh PMOS transistor is connected, and the source of the fourth PMOS transistor is respectively connected to the source of the sixth NMOS transistor, the gate of the seventh NMOS transistor, and the fifth The gate of the PMOS transistor, the source of the sixth PMOS transistor and the source of the eighth NMOS transistor are connected, and the source of the fourth PMOS transistor is used as a gate voltage bootstrap one-bit full adder Carry input terminal, the substrate of the sixth NMOS transistor is grounded, the drain of the fourth PMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor and the drain of the seventh NMOS transistor respectively. The drain of the fifth PMOS transistor is connected, the drain of the fourth PMOS transistor is used as the summation output of the grid voltage bootstrap one-bit full adder, and the substrate of the fourth PMOS transistor is connected to the external The positive pole of the power supply is connected, the substrate of the fifth PMOS transistor is connected to the positive pole of the external power supply, the gate of the sixth NMOS transistor is connected to the source of the seventh NMOS transistor, the second The drain of the PMOS transistor, the gate of the sixth PMOS transistor and the gate of the ninth NMOS transistor are connected, the substrate of the seventh NMOS transistor is grounded, and the source of the seventh PMOS transistor The poles are respectively connected to the source of the ninth NMOS transistor and the source of the third NMOS transistor, and the drain of the sixth PMOS transistor is respectively connected to the drain of the eighth NMOS transistor and the drain of the eighth NMOS transistor. The drain of the seventh PMOS transistor and the drain of the ninth NMOS transistor are connected, the drain of the sixth PMOS transistor is used as the carry output terminal of the grid voltage bootstrap one-bit full adder, and the Both the substrate of the sixth PMOS transistor and the substrate of the seventh PMOS transistor are connected to the anode of the external power supply, and the substrates of the eighth NMOS transistor and the ninth NMOS transistor are grounded. The internal nodes of the above-mentioned gate voltage bootstrap one-bit full adder reach full swing, which improves the ability to drive the next stage, and is easy to use under low-voltage working conditions without causing logic confusion.

The channel length of the first PMOS transistor, the channel length of the second PMOS transistor, the channel length of the third PMOS transistor, the channel length of the fourth PMOS transistor, the The channel length of the fifth PMOS transistor, the channel length of the sixth PMOS transistor, the channel length of the seventh PMOS transistor, the channel length of the first NMOS transistor, and the channel length of the first NMOS transistor The channel length of the second NMOS transistor, the channel length of the third NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the fifth NMOS transistor, and the sixth NMOS transistor The channel length of the tube, the channel length of the seventh NMOS tube, the channel length of the eighth NMOS tube and the channel length of the ninth NMOS tube are the minimum channel lengths under the standard process 1~1.2 times of that.

Compared with the prior art, the present invention has the advantage that the XOR/XOR circuit is connected into a gate voltage bootstrap circuit structure, and the gate voltage of the third NMOS transistor or the fourth NMOS transistor is increased through the grid bootstrap effect , so that the high level passes through the first NMOS tube or the second NMOS tube smoothly, and the circuit output reaches the full swing, which improves the ability to drive the next stage and increases the operating speed of the overall circuit; the full swing reduces the circuit's Leakage power consumption improves the performance of the circuit, and finally effectively reduces the delay, power consumption and power consumption-delay product of the overall circuit. the

Description of drawings

Figure 1 is a structural diagram of an exclusive-or/same-or (CCMOS-XX) circuit based on a CMOS complementary logic structure;

Figure 2 is a structural diagram of an exclusive-or/simultaneous-or (TG-XX) circuit based on a transmission gate logic structure;

Figure 3 is a structural diagram of an exclusive-or/same-or (CPL-XX) circuit based on the logical structure of the transmission tube;

Fig. 4 is a summation signal generating circuit unit structural diagram;

Fig. 5 is a structural diagram of a carry signal generation circuit unit;

Figure 6 is a circuit structure diagram of a one-bit full adder (CCMOS-XX-ADDER) based on an XOR/XOR circuit unit of a CMOS complementary logic structure;

Figure 7 is a circuit structure diagram of a one-bit full adder (TG-XX-ADDER) based on transmission gate logic XOR/XOR circuit unit;

Figure 8 is a circuit structure diagram of a one-bit full adder (CPL-XX-ADDER) based on the logical XOR/XOR circuit unit of the transmission tube;

Fig. 9 is a structural diagram of the grid voltage bootstrapping XOR/XOR circuit of the present invention;

Fig. 10 is the circuit structure diagram of the grid voltage bootstrapping one full adder of the present invention;

Fig. 11 is the simulation waveform diagram based on the SMIC130nm standard process of the grid voltage bootstrapping one-bit full adder of the present invention;

Fig. 12 is the simulation waveform diagram based on the PTM90nm standard process of the grid voltage bootstrapping one-bit full adder of the present invention;

FIG. 13 is a simulation waveform diagram of the gate voltage bootstrap 1-bit full adder based on the PTM45nm standard process of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

Embodiment 1: As shown in FIG. 9, a grid voltage bootstrap NOR/NOR circuit includes a grid voltage bootstrap NOR generation circuit and an inverter, and the grid voltage bootstrap NOR generation circuit includes a first PMOS transistor , the second PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube, the inverter includes the third PMOS tube and the fifth NMOS tube, the source of the first PMOS tube is connected to the external power supply The drain of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is respectively connected to the source of the first NMOS transistor and the source of the third NMOS transistor, and the second PMOS transistor is connected to the source of the third NMOS transistor. The substrate of the transistor is connected to the positive pole of the external power supply, the gate of the second PMOS transistor is respectively connected to the source of the second NMOS transistor and the source of the fourth NMOS transistor, and the drain of the second PMOS transistor is connected to the source of the first NMOS transistor respectively. The drain of the second NMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor and the gate of the fifth NMOS transistor are connected, and the drain of the second PMOS transistor is used as the NOR of the gate voltage bootstrapped XOR/NOR circuit At the output terminal, the source of the third PMOS transistor is connected to the positive pole of the external power supply, the drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, and the drain of the third PMOS transistor is used as a gate voltage bootstrap XOR/Same The exclusive OR output terminal of the OR circuit, the source of the fifth NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the drain of the fourth NMOS transistor, the substrate of the first NMOS transistor is grounded, and the gate of the third NMOS transistor The drain of the third NMOS transistor is connected to the gate of the second NMOS transistor, the substrate of the second NMOS transistor is grounded, and the gate of the fourth NMOS transistor is connected to the positive electrode of the external power supply.

The channel length of the first PMOS transistor, the channel length of the second PMOS transistor, the channel length of the third PMOS transistor, the channel length of the fourth PMOS transistor, the channel length of the fifth PMOS transistor, and the channel length of the sixth PMOS transistor channel length, the channel length of the seventh PMOS transistor, the channel length of the first NMOS transistor, the channel length of the second NMOS transistor, the channel length of the third NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the The channel length of the fifth NMOS transistor, the channel length of the sixth NMOS transistor, the channel length of the seventh NMOS transistor, the channel length of the eighth NMOS transistor, and the channel length of the ninth NMOS transistor under the SMIC130nm standard process are all 130nm.

Embodiment 2: the remaining parts are the same as Embodiment 1, except that the channel length of the first PMOS transistor, the channel length of the second PMOS transistor, the channel length of the third PMOS transistor, and the channel length of the fourth PMOS transistor are different. channel length, the channel length of the fifth PMOS transistor, the channel length of the sixth PMOS transistor, the channel length of the seventh PMOS transistor, the channel length of the first NMOS transistor, the channel length of the second NMOS transistor, the third The channel length of the NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the fifth NMOS transistor, the channel length of the sixth NMOS transistor, the channel length of the seventh NMOS transistor, and the channel length of the eighth NMOS transistor The length and the channel length of the ninth NMOS transistor under the PTM90nm standard process are both 90nm.

Embodiment three: the remaining parts are the same as in embodiment one, except that the channel length of the first PMOS transistor, the channel length of the second PMOS transistor, the channel length of the third PMOS transistor, and the channel length of the fourth PMOS transistor are different. channel length, the channel length of the fifth PMOS transistor, the channel length of the sixth PMOS transistor, the channel length of the seventh PMOS transistor, the channel length of the first NMOS transistor, the channel length of the second NMOS transistor, the third The channel length of the NMOS transistor, the channel length of the fourth NMOS transistor, the channel length of the fifth NMOS transistor, the channel length of the sixth NMOS transistor, the channel length of the seventh NMOS transistor, and the channel length of the eighth NMOS transistor Both the channel length of the ninth NMOS transistor and the channel length of the PTM45nm standard process are 50nm.

In order to compare the gate voltage bootstrapping XOR/XOR circuit proposed by the present invention under the three standard technologies of SMIC130nm, PTM90nm and PTM45nm with respect to the XOR/Same-OR (CCMOS-XX) circuit based on CMOS complementary logic structure, The performance characteristics of the three traditional exclusive-or/same-or (TG-XX) circuits based on the transmission gate logic structure and the exclusive-or/same-or (CPL-XX) circuit based on the transmission pipe logic structure, Using the circuit simulation tool HSPICE to simulate and compare the four circuit structures under the condition that the input frequency of the circuit is 100Mhz, the corresponding power supply voltages are 1.2V, 1V, and 1V respectively.

Table 1 Performance comparison between the gate voltage bootstrap XOR/SOR circuit of the present invention and three traditional XOR/SOR circuits under the SMIC130nm standard process

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) Exclusive-or/same-or (CCMOS-XX) circuits based on CMOS complementary logic structures 0.1433 3.7816 0.5419 Exclusive OR/Exclusive OR (TG-XX) circuit based on transmission gate logic structure 0.1167 2.4019 0.2803 Exclusive-or/same-or (CPL-XX) circuit based on transmission tube logic structure 0.1938 2.5396 0.4922 The channel length of the transistor in the gate voltage bootstrap XOR/SOR circuit of the present invention is 130nm 0.1069 2.1841 0.2335

It can be drawn from Table 1 that the gate voltage bootstrapping XOR/NOR circuit of the present invention is compared with three traditional XOR/NOR circuits under the SMIC130nm standard process, and the delay is reduced by 25.4% and 8.4% respectively and 44.8%, the average total power consumption was reduced by 42.2%, 9.1% and 14% respectively, and the power consumption-delay product was reduced by 56.9%, 16.7% and 52.6% respectively.

Table 2 Performance Comparison of Gate Voltage Bootstrap XOR/Same-OR Circuit and Three Traditional XOR/Same-OR Circuits under PTM90nm Standard Technology

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) Exclusive-or/same-or (CCMOS-XX) circuits based on CMOS complementary logic structures 0.1631 3.0114 0.4912 Exclusive OR/Exclusive OR (TG-XX) circuit based on transmission gate logic structure 0.1433 2.1121 0.3026 Exclusive-or/same-or (CPL-XX) circuit based on transmission tube logic structure 0.3012 2.1421 0.6452 The channel length of the transistor in the gate voltage bootstrap XOR/XOR circuit of the present invention is 90nm 0.1321 1.8541 0.2450

It can be drawn from Table 2 that the gate voltage bootstrap XOR/NOR circuit of the present invention is compared with three traditional XOR/NOR circuits under the PTM90nm standard process, and the delay is reduced by 19% and 7.8% respectively and 56.1%, the average total power consumption was reduced by 38.4%, 12.2% and 13.4% respectively, and the power consumption-delay product was reduced by 50.1%, 19% and 62% respectively. the

Table 3 Performance Comparison of Gate Voltage Bootstrap XOR/Same-OR Circuit and Three Traditional XOR/Same-OR Circuits under PTM45nm Standard Technology

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) Exclusive-or/same-or (CCMOS-XX) circuits based on CMOS complementary logic structures 0.2901 1.4553 0.4222 Exclusive OR/Exclusive OR (TG-XX) circuit based on transmission gate logic structure 0.2421 1.0589 0.2564 Exclusive-or/same-or (CPL-XX) circuit based on transmission tube logic structure 0.5578 1.0709 0.5973 The channel length of the transistor in the gate voltage bootstrap XOR/SOR circuit of the present invention is 50nm 0.2006 0.9675 0.1941

From Table 3, it can be drawn that: from Table 2, it can be drawn that the gate voltage bootstrap XOR/NOR circuit of the present invention is compared with three traditional XOR/NOR circuits under the PTM45nm standard process, and the time delay Respectively reduced by 30.9%, 17.1% and 64%, the average total power consumption was reduced by 33.5%, 8.6% and 9.7% respectively, and the power consumption-delay product was reduced by 54%, 24.3% and 67.5% respectively.

It can be seen from the above comparative data that, without affecting the circuit performance, the gate voltage bootstrap XOR/NOR circuit proposed by the present invention has a smaller delay than the above three traditional XOR/NOR circuits. , low average total power consumption and small power consumption-delay product.

Embodiment 4: As shown in FIG. 10 , the grid voltage bootstrapping one-bit full adder composed of the grid voltage bootstrapping XOR/NOR circuit of Embodiment 1 is used, including the grid voltage bootstrapping XOR/XOR circuit, A sum signal generating circuit and a carry signal generating circuit, the sum signal generating circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, and the carry signal generating circuit includes a sixth PMOS transistor and a seventh PMOS transistor , the eighth NMOS transistor and the ninth NMOS transistor, the gate of the fourth PMOS transistor is respectively connected to the drain of the third PMOS transistor, the source of the fifth PMOS transistor, the gate of the eighth NMOS transistor and the gate of the seventh PMOS transistor The source of the fourth PMOS transistor is connected to the source of the sixth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the fifth PMOS transistor, the source of the sixth PMOS transistor, and the source of the eighth NMOS transistor. The source of the fourth PMOS transistor is used as the carry input terminal of the gate voltage bootstrap one-bit full adder, the substrate of the sixth NMOS transistor is grounded, and the drain of the fourth PMOS transistor is respectively connected to the drain of the sixth NMOS transistor. , the drain of the seventh NMOS transistor is connected to the drain of the fifth PMOS transistor, the drain of the fourth PMOS transistor is used as the summation output end of a full adder for gate voltage bootstrapping, the substrate of the fourth PMOS transistor is connected to the external The positive pole of the power supply is connected, the substrate of the fifth PMOS transistor is connected to the positive pole of the external power supply, the gate of the sixth NMOS transistor is connected to the source electrode of the seventh NMOS transistor, the drain electrode of the second PMOS transistor, and the gate of the sixth PMOS transistor respectively. pole and the gate of the ninth NMOS transistor are connected, the substrate of the seventh NMOS transistor is grounded, the source of the seventh PMOS transistor is respectively connected to the source of the ninth NMOS transistor and the source of the third NMOS transistor, and the sixth PMOS transistor The drains of the eighth NMOS transistor, the drains of the seventh PMOS transistor and the drains of the ninth NMOS transistor are respectively connected, and the drain of the sixth PMOS transistor is used as the carry output of the gate voltage bootstrap one-bit full adder Both the substrates of the sixth PMOS transistor and the seventh PMOS transistor are connected to the anode of the external power supply, and the substrates of the eighth NMOS transistor and the ninth NMOS transistor are both grounded.

The gate voltage bootstrap XOR/XOR circuit in the gate voltage bootstrap of the fourth embodiment can also adopt the circuit structure of the second or third embodiment.

In order to compare the grid voltage bootstrapping one full adder that the present invention proposes under these three kinds of standard technology of SMIC130nm, PTM90nm and PTM45nm respectively with respect to the one full adder of the exclusive OR/same OR circuit unit based on CMOS complementary logic structure (CCMOS-XX-ADDER), one-bit full adder based on transmission gate logic XOR/XOR circuit unit (TG-XX-ADDER) and one-bit full adder based on transmission tube logic XOR/XOR circuit unit (CPL-XX-ADDER) The performance characteristics of these three traditional one-bit full adders, using the circuit simulation tool HSPICE to simulate and compare the circuit structures of the four full adders under the condition that the input frequency of the circuit is 100Mhz , and the corresponding power supply voltages are 1.2V, 1V, and 1V respectively.

Table 4 under the SMIC130nm standard process, the performance comparison of the gate voltage bootstrap one-bit full adder of the present invention and three traditional one-bit full adders

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) One-bit full adder based on XOR/XOR circuit unit of CMOS complementary logic structure (CCMOS-XX-ADDER) 0.263 9.0401 2.378 One-bit full adder based on transmission gate logic XOR/XOR circuit unit (TG-XX-ADDER) 0.241 7.9227 1.909 One-bit full adder (CPL-XX-ADDER) based on transmission tube logical XOR/XOR circuit unit 0.343 8.0019 2.745 The channel length of the transistor in the gate voltage bootstrap one-bit full adder of the present invention is 130nm 0.212 7.6378 1.619

From Table 4, it can be drawn that the delay of the gate voltage bootstrap one-bit full adder of the present invention and three kinds of traditional one-bit full adders under the SMIC130nm process has been reduced by 19.4%, 12% and 38.2% respectively, with an average The total power consumption is reduced by 15.5%, 3.6% and 4.6%, respectively, and the power-delay product is reduced by 31.9%, 15.2% and 41%, respectively.

Table 5 under the PTM90nm standard process, the performance comparison of the gate voltage bootstrapping one-bit full adder of the present invention and three traditional one-bit full adders

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) One-bit full adder based on XOR/XOR circuit unit of CMOS complementary logic structure (CCMOS-XX-ADDER) 0.289 8.1011 2.341 One-bit full adder based on transmission gate logic XOR/XOR circuit unit (TG-XX-ADDER) 0.267 6.8112 1.818 One-bit full adder (CPL-XX-ADDER) based on transmission tube logical XOR/XOR circuit unit 0.391 6.7671 2.646 The channel length of the transistor in the gate voltage bootstrap one-bit full adder of the present invention is 90nm 0.265 5.9018 1.564

From Table 5, it can be drawn that the time delay of the gate voltage bootstrap one-bit full adder of the present invention and three kinds of traditional one-bit full adders under the PTM90nm process has been reduced by 8.3%, 0.7% and 32.2% respectively, with an average The total power consumption is reduced by 27.1%, 13.4% and 12.8%, respectively, and the power-delay product is reduced by 33.2%, 14% and 40.9%, respectively.

Table 6 Under the PTM45nm standard process, the gate voltage bootstrapping one-bit full adder of the present invention is compared with the performance of three traditional one-bit full adder circuits

circuit type time delay (ns) Average total power consumption (μW) Power-Delay Product (fJ) One-bit full adder based on XOR/XOR circuit unit of CMOS complementary logic structure (CCMOS-XX-ADDER) 0.576 3.979 2.292 One-bit full adder based on transmission gate logic XOR/XOR circuit unit (TG-XX-ADDER) 0.534 3.312 1.769 One-bit full adder (CPL-XX-ADDER) based on transmission tube logical XOR/XOR circuit unit 0.801 3.201 2.564 The channel length of the transistor in the grid voltage bootstrap one-bit full adder of the present invention is 50nm 0.516 2.911 1.502

From Table 6, it can be drawn that the delay of the grid voltage bootstrapping one full adder of the present invention and three kinds of traditional one full adder circuits under the PTM45nm process has been reduced by 10.4%, 3.4% and 35.6% respectively, The average total power consumption is reduced by 26.8%, 12.1% and 9.1%, respectively, and the power-delay product is reduced by 34.5%, 15.1% and 41.4%, respectively.

As can be seen from the above comparison data, under the premise of not affecting the performance of the circuit, the gate voltage bootstrap one-bit full adder of the present invention has the advantages of small delay and average total power The advantages of low power consumption and small power-delay product.

Table 7 The cell state transition table of the grid voltage bootstrapping one-bit full adder of the present invention

A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C _in 0 1 0 1 0 1 0 1 Sum 0 1 1 0 1 0 0 1 C _out 0 0 0 1 0 1 1 1

It can be seen from the simulation waveform diagrams in FIGS. 11 to 13 combined with the results in Table 7 that the gate voltage bootstrap one-bit full adder of the present invention has correct logic functions.

Claims (4)

1. A Bootstrap XOR/with or circuit, it is characterized in that comprising that Bootstrap is same or produce circuit and inverter, described Bootstrap with or produce circuit and comprise a PMOS pipe, the 2nd PMOS pipe, the one NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe and the 4th NMOS pipe, described a source electrode for PMOS pipe and the positive pole of external power source are connected, the drain electrode of a described PMOS pipe is connected with the source electrode of the 2nd described PMOS pipe, the grid of a described PMOS pipe is connected with the source electrode of the source electrode of a described NMOS pipe and described the 3rd NMOS pipe respectively, described the 2nd substrate of PMOS pipe and the positive pole of external power source are connected, the grid of the 2nd described PMOS pipe is connected with the source electrode of the source electrode of described the 2nd NMOS pipe and described the 4th NMOS pipe respectively, the drain electrode of the 2nd described PMOS pipe respectively with the drain electrode of a described NMOS pipe, the input of the drain electrode of the 2nd described NMOS pipe and described inverter is connected, the drain electrode of the 2nd described PMOS pipe as Bootstrap XOR/with or the same or output of circuit, the output of described inverter as Bootstrap XOR/with or the XOR output of circuit, the grid of a described NMOS pipe is connected with the drain electrode of the 4th described NMOS pipe, the substrate ground connection of a described NMOS pipe, described the 3rd grid of NMOS pipe and the positive pole of external power source are connected, the drain electrode of the 3rd described NMOS pipe is connected with the grid of the 2nd described NMOS pipe, the substrate ground connection of the 2nd described NMOS pipe, described the 4th grid of NMOS pipe and the positive pole of external power source are connected.
2. A kind of Bootstrap XOR according to claim 1/with or circuit, it is characterized in that described inverter comprises the 3rd PMOS pipe and the 5th NMOS pipe, the grid of the 3rd described PMOS pipe is connected with the grid of the drain electrode of described the 2nd PMOS pipe and described the 5th NMOS pipe respectively, described the 3rd source electrode of PMOS pipe and the positive pole of external power source are connected, the drain electrode of the 3rd described PMOS pipe is connected with the drain electrode of the 5th described NMOS pipe, the drain electrode of the 3rd described PMOS pipe as Bootstrap XOR/with or the XOR output of circuit, the source ground of the 5th described NMOS pipe.
3. Right to use require Bootstrap XOR described in 1/with or the Bootstrap one-bit full addres of the electric circuit constitute, it is characterized in that comprising Bootstrap XOR/same or circuit, summing signal produces circuit and carry signal produces circuit, described summing signal produces circuit and comprises the 4th PMOS pipe, the 5th PMOS pipe, the 6th NMOS pipe and the 7th NMOS pipe, described carry signal produces circuit and comprises the 6th PMOS pipe, the 7th PMOS pipe, the 8th NMOS pipe and the 9th NMOS pipe, the grid of the 4th described PMOS pipe respectively with the drain electrode of described the 3rd PMOS pipe, the source electrode of the 5th described PMOS pipe, the grid of the grid of the 8th described NMOS pipe and the 7th described PMOS pipe is connected, the source electrode of the 4th described PMOS pipe respectively with the source electrode of described the 6th NMOS pipe, the grid of the 7th described NMOS pipe, the grid of the 5th described PMOS pipe, the source electrode of the source electrode of the 6th described PMOS pipe and the 8th described NMOS pipe is connected, the source electrode of the 4th described PMOS pipe is as the carry input of Bootstrap one-bit full addres, the substrate ground connection of the 6th described NMOS pipe, the drain electrode of the 4th described PMOS pipe respectively with the drain electrode of described the 6th NMOS pipe, the drain electrode of the drain electrode of the 7th described NMOS pipe and the 5th described PMOS pipe is connected, the drain electrode of the 4th described PMOS pipe is as the summation output of Bootstrap one-bit full addres, described the 4th substrate of PMOS pipe and the positive pole of external power source are connected, described the 5th substrate of PMOS pipe and the positive pole of external power source are connected, the grid of the 6th described NMOS pipe respectively with the source electrode of described the 7th NMOS pipe, the drain electrode of the 2nd described PMOS pipe, the grid of the grid of the 6th described PMOS pipe and the 9th described NMOS pipe is connected, the substrate ground connection of the 7th described NMOS pipe, the source electrode of the 7th described PMOS pipe is connected with the source electrode of the source electrode of described the 9th NMOS pipe and described the 3rd NMOS pipe respectively, the drain electrode of the 6th described PMOS pipe respectively with the drain electrode of described the 8th NMOS pipe, the drain electrode of the drain electrode of the 7th described PMOS pipe and the 9th described NMOS pipe is connected, the drain electrode of the 6th described PMOS pipe is as the carry output of Bootstrap one-bit full addres, the substrate of the substrate of the 6th described PMOS pipe and the 7th described PMOS pipe is all connected with the positive pole of external power source, the equal ground connection of substrate of the substrate of the 8th described NMOS pipe and the 9th described NMOS pipe.
4. 4. Bootstrap one-bit full addres according to claim 3, the channel length that it is characterized in that a described PMOS pipe, the channel length of the 2nd described PMOS pipe, the channel length of the 3rd described PMOS pipe, the channel length of the 4th described PMOS pipe, the channel length of the 5th described PMOS pipe, the channel length of the 6th described PMOS pipe, the channel length of the 7th described PMOS pipe, the channel length of a described NMOS pipe, the channel length of the 2nd described NMOS pipe, the channel length of the 3rd described NMOS pipe, the channel length of the 4th described NMOS pipe, the channel length of the 5th described NMOS pipe, the channel length of the 6th described NMOS pipe, the channel length of the 7th described NMOS pipe, the channel length of the channel length of the 8th described NMOS pipe and the 9th described NMOS pipe is 1 ~ 1.2 times of minimum channel length under standard technology.