CN103957002B - A kind of Bootstrap XOR/same or circuit and Bootstrap one-bit full addres - Google Patents
A kind of Bootstrap XOR/same or circuit and Bootstrap one-bit full addres Download PDFInfo
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- CN103957002B CN103957002B CN201410150247.1A CN201410150247A CN103957002B CN 103957002 B CN103957002 B CN 103957002B CN 201410150247 A CN201410150247 A CN 201410150247A CN 103957002 B CN103957002 B CN 103957002B
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Abstract
The invention discloses a kind of Bootstrap XOR/same or circuit and the Bootstrap one-bit full addres collectively constituted with summing signal generation circuit and carry signal generation circuit, feature be Bootstrap XOR/with or circuit include Bootstrap with or generation circuit and phase inverter, wherein Bootstrap with or generation circuit be made up of the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube special connected mode；Advantage is that XOR/same or circuit is connected into Bootstrap circuit structure, pass through grid bootstrap effect, improve the grid voltage of the 3rd NMOS tube or the 4th NMOS tube, and then high level is passed through the first NMOS tube or the second NMOS tube, circuit output reaches full swing, the ability of driving next stage is improved, the speed of service of integrated circuit is increased；Full swing reduces the leakage power consumption of circuit, improves the performance of circuit, finally significantly reduces delay, power consumption and the power-consumption design of integrated circuit.
Description
Technical field
The present invention relates to a kind of XOR circuit, especially a kind of Bootstrap XOR/same or circuit and Bootstrap one
Full adder.
Background technology
XOR gate belongs to one of widely used gate circuit, generally requires to carry out it design of low-power consumption.
Full adder has application widely as the basic processing unit of electronic system in many VLSI systems,
Such as in high-performance microprocessor and DSP Processor, the operational capability of one-bit full addres is most important.One-bit full addres computing is normal
Often in the critical path in high-performance processor system unit, the computing of one-bit full addres especially in ALU
Performance plays very crucial effect to the performance of processor.It is more and more faster with the arithmetic speed of microprocessor, to quick one
The demand also more and more higher of position full adder.The performance of its speed and power consumption and area etc. will directly influence whole integrated circuit
Overall performance.
Delay, power consumption and power consumption-delay product are to embody main three factors of one-bit full addres performance, optimize these three because
Element can optimize the performance of full adder so as to improve the performance of total system, wherein, power consumption-delay product is power consumption and multiplying for being delayed
Product, unit is joule, therefore power consumption-delay product is the measurement of energy, can as a switching device performance measurement.It is many
Scholar proposes the one-bit full addres of a variety of use Different Logics (see document A.M.Shams, T.K.Darwish and
M.A.Bayoumi,“Performance analysis of low-power 1-bit CMOS full adder cells,”
IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol.10,2002, pp 20-29.), these one
Though a position full adder has certain effect but there is also distinct disadvantage, and first, there is threshold voltage loss, Non-full swing output；The
Two, power consumption or power consumption-delay product are larger.
The content of the invention
It is less that the technical problems to be solved by the invention are to provide a kind of circuit delay, power consumption and power consumption-delay product
Bootstrap XOR/same or circuit and Bootstrap one-bit full addres.
The present invention solve the technical scheme that is used of above-mentioned technical problem for：A kind of Bootstrap XOR/same or circuit, bag
Include Bootstrap with or generation circuit and phase inverter, described Bootstrap with or generation circuit include the first PMOS, second
PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube and the 4th NMOS tube, the source electrode of described the first PMOS with
The positive pole of external power source is connected, and the drain electrode of the first described PMOS is connected with the source electrode of the second described PMOS, described
Source electrode of the grid of first PMOS respectively with the source electrode of the first described NMOS tube and the 3rd described NMOS tube is connected, described
The substrate of the second PMOS be connected with the positive pole of external power source, the grid of described the second PMOS is respectively with described second
The source electrode of NMOS tube and the source electrode of the 4th described NMOS tube are connected, and the drain electrode of described the second PMOS is respectively with described the
The input of the draining of one NMOS tube, the drain electrode of the second described NMOS tube and described phase inverter is connected, and described second
The drain electrode of PMOS as Bootstrap XOR/with or circuit same or output end, the output end of described phase inverter is used as grid
Pressure bootstrapping XOR/with or circuit XOR output end, the grid of described the first NMOS tube and the leakage of the 4th described NMOS tube
Extremely it is connected, the Substrate ground of described the first NMOS tube, the grid of the 3rd described NMOS tube is connected with the positive pole of external power source,
The drain electrode of the 3rd described NMOS tube is connected with the grid of the second described NMOS tube, and the substrate of the second described NMOS tube connects
Ground, the grid of the 4th described NMOS tube is connected with the positive pole of external power source.
Described phase inverter includes the 3rd PMOS and the 5th NMOS tube, the grid of described the 3rd PMOS respectively with institute
The grid of the drain electrode for the second PMOS stated and the 5th described NMOS tube is connected, the source electrode of described the 3rd PMOS with it is outside
The positive pole of power supply is connected, and the drain electrode of the 3rd described PMOS is connected with the drain electrode of the 5th described NMOS tube, and the described the 3rd
The drain electrode of PMOS as Bootstrap XOR/with or circuit XOR output end, the source ground of described the 5th NMOS tube.
The Bootstrap one-bit full addres constituted using above-mentioned Bootstrap XOR/same or circuit, including Bootstrap are different
Or/with or circuit, summing signal generation circuit and carry signal generation circuit, described summing signal generation circuit includes the 4th
PMOS, the 5th PMOS, the 6th NMOS tube and the 7th NMOS tube, described carry signal generation circuit include the 6th PMOS
Pipe, the 7th PMOS, the 8th NMOS tube and the 9th NMOS tube, the grid of described the 4th PMOS is respectively with the described the 3rd
The draining of PMOS, the source electrode of the 5th described PMOS, the grid of the 8th described NMOS tube and the 7th described PMOS
Grid be connected, source electrode, the 7th described NMOS of the source electrode of described the 4th PMOS respectively with the 6th described NMOS tube
The grid of pipe, the grid of the 5th described PMOS, the source of the source electrode of the 6th described PMOS and the 8th described NMOS tube
Extremely be connected, the source electrode of described the 4th PMOS as Bootstrap one-bit full addres carry input, the described the 6th
The Substrate ground of NMOS tube, the drain electrode of described the 4th PMOS respectively with the draining of the 6th described NMOS tube, described the
The drain electrode of seven NMOS tubes and the drain electrode of the 5th described PMOS are connected, and the drain electrode of the 4th described PMOS is used as Bootstrap
The summation output end of one-bit full addres, the substrate of the 4th described PMOS is connected with the positive pole of external power source, and the described the 5th
The substrate of PMOS is connected with the positive pole of external power source, the grid of described the 6th NMOS tube respectively with the 7th described NMOS tube
Source electrode, the draining of described second PMOS, the grid of the grid of the 6th described PMOS and the 9th described NMOS tube
Be connected, the Substrate ground of described the 7th NMOS tube, the source electrode of described the 7th PMOS respectively with the 9th described NMOS tube
Source electrode and the source electrode of described the 3rd NMOS tube be connected, the drain electrode of described the 6th PMOS respectively with the 8th described NMOS
The draining of pipe, the drain electrode of the 7th described PMOS and the drain electrode of the 9th described NMOS tube are connected, the 6th described PMOS
Drain electrode be used as the carry output of Bootstrap one-bit full addres, the substrate and the described the 7th of described the 6th PMOS
The substrate of PMOS is connected with the positive pole of external power source, the substrate of described the 8th NMOS tube and the 9th described NMOS tube
Substrate is grounded.The internal node of above-mentioned Bootstrap one-bit full addres all reaches full swing, improves the energy of driving next stage
Power, it is easy to used under the conditions of low voltage operating, and logical miss will not be caused.
The channel length of the first described PMOS, the channel length of the second described PMOS, the 3rd described PMOS
The channel length of pipe, the channel length of the 4th described PMOS, the channel length of the 5th described PMOS, the described the 6th
It is the channel length of PMOS, the channel length of the 7th described PMOS, the channel length of the first described NMOS tube, described
The channel length of second NMOS tube, the channel length of the 3rd described NMOS tube, the channel length of the 4th described NMOS tube, institute
The channel length for the 5th NMOS tube stated, the channel length of the 6th described NMOS tube, the 7th described NMOS tube raceway groove it is long
The channel length of degree, the channel length of the 8th described NMOS tube and the 9th described NMOS tube is most ditch under standard technology
1~1.2 times of road length.
Compared with prior art, the advantage of the invention is that XOR/same or circuit is connected into Bootstrap circuit structure,
By grid bootstrap effect, the grid voltage of the 3rd NMOS tube or the 4th NMOS tube is improved, and then passes through high level
First NMOS tube or the second NMOS tube, circuit output reach full swing, improve the ability of driving next stage, increase overall electricity
The speed of service on road；Full swing reduces the leakage power consumption of circuit, improves the performance of circuit, finally significantly reduces overall electricity
Delay, power consumption and the power consumption on road-delay product.
Brief description of the drawings
Fig. 1 is the structure chart of the XOR based on CMOS complementary logic structures/same or (CCMOS-XX) circuit；
Fig. 2 is the structure chart of the XOR based on transmission gate logical construction/same or (TG-XX) circuit；
Fig. 3 is the structure chart of the XOR based on Pass-transistor logic structure/same or (CPL-XX) circuit；
Fig. 4 is summing signal generation circuit cellular construction figure；
Fig. 5 is carry signal generation circuit cellular construction figure；
Fig. 6 is the one-bit full addres (CCMOS-XX- of the XOR based on CMOS complementary logic structures/same or circuit unit
ADDER circuit structure diagram)；
Fig. 7 is the circuit knot of the one-bit full addres (TG-XX-ADDER) based on transmission gate logic XOR/same or circuit unit
Composition；
Fig. 8 is the circuit of the one-bit full addres (CPL-XX-ADDER) based on Pass-transistor logic XOR/same or circuit unit
Structure chart；
Fig. 9 is the structure chart of Bootstrap XOR/same or circuit of the present invention；
Figure 10 is the circuit structure diagram of the Bootstrap one-bit full addres of the present invention；
Figure 11 is the Bootstrap one-bit full addres of the present invention based on SMIC130nm standard technology simulation waveforms；
Figure 12 is the Bootstrap one-bit full addres of the present invention based on PTM90nm standard technology simulation waveforms；
Figure 13 is the Bootstrap one-bit full addres of the present invention based on PTM45nm standard technology simulation waveforms.
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment one：As shown in figure 9, a kind of Bootstrap XOR/with or circuit, including Bootstrap with or generation circuit
And phase inverter, Bootstrap with or generation circuit include the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube,
3rd NMOS tube and the 4th NMOS tube, phase inverter include the 3rd PMOS (figure is not shown) and the 5th NMOS tube (figure is not shown),
The source electrode of first PMOS is connected with the positive pole of external power source, and the drain electrode of the first PMOS is connected with the source electrode of the second PMOS,
The grid of first PMOS is connected with the source electrode of the first NMOS tube and the source electrode of the 3rd NMOS tube respectively, the substrate of the second PMOS
It is connected with the positive pole of external power source, the source electrode and the source electrode of the 4th NMOS tube of the grid of the second PMOS respectively with the second NMOS tube
It is connected, the drain electrode drained respectively with the first NMOS tube of the second PMOS, the drain electrode of the second NMOS tube, the grid of the 3rd PMOS
And the 5th the grid of NMOS tube be connected, the drain electrode of the second PMOS as Bootstrap XOR/with or circuit same or output end,
The source electrode of 3rd PMOS is connected with the positive pole of external power source, and the drain electrode of the 3rd PMOS is connected with the drain electrode of the 5th NMOS tube,
The drain electrode of 3rd PMOS as Bootstrap XOR/with or circuit XOR output end, the source ground of the 5th NMOS tube, the
The grid of one NMOS tube is connected with the drain electrode of the 4th NMOS tube, the Substrate ground of the first NMOS tube, the grid of the 3rd NMOS tube with
The positive pole of external power source is connected, and the drain electrode of the 3rd NMOS tube is connected with the grid of the second NMOS tube, and the substrate of the second NMOS tube connects
Ground, the grid of the 4th NMOS tube is connected with the positive pole of external power source.
The channel length of first PMOS, the channel length of the second PMOS, the channel length of the 3rd PMOS, the 4th
The channel length of PMOS, the channel length of the 5th PMOS, the channel length of the 6th PMOS, the 7th PMOS raceway groove it is long
Degree, the channel length of the first NMOS tube, the channel length of the second NMOS tube, the channel length of the 3rd NMOS tube, the 4th NMOS tube
Channel length, the channel length of the 5th NMOS tube, the channel length of the 6th NMOS tube, the channel length of the 7th NMOS tube,
The channel length of the channel length of eight NMOS tubes and the 9th NMOS tube under SMIC130nm standard technologies is 130nm.
Embodiment two：Remainder is identical with embodiment one, and its difference is the channel length of the first PMOS,
The channel length of two PMOSs, the channel length of the 3rd PMOS, the channel length of the 4th PMOS, the raceway groove of the 5th PMOS
Length, the channel length of the 6th PMOS, the channel length of the 7th PMOS, the channel length of the first NMOS tube, the 2nd NMOS
The channel length of pipe, the channel length of the 3rd NMOS tube, the channel length of the 4th NMOS tube, the channel length of the 5th NMOS tube,
Channel length, the channel length of the 7th NMOS tube, the channel length of the 8th NMOS tube and the 9th NMOS tube of 6th NMOS tube exist
Channel length under PTM90nm standard technologies is 90nm.
Embodiment three：Remainder is identical with embodiment one, and its difference is the channel length of the first PMOS,
The channel length of two PMOSs, the channel length of the 3rd PMOS, the channel length of the 4th PMOS, the raceway groove of the 5th PMOS
Length, the channel length of the 6th PMOS, the channel length of the 7th PMOS, the channel length of the first NMOS tube, the 2nd NMOS
The channel length of pipe, the channel length of the 3rd NMOS tube, the channel length of the 4th NMOS tube, the channel length of the 5th NMOS tube,
Channel length, the channel length of the 7th NMOS tube, the channel length of the 8th NMOS tube and the 9th NMOS tube of 6th NMOS tube exist
Channel length under PTM45nm standard technologies is 50nm.
In order to relatively Bootstrap XOR proposed by the invention/with or circuit respectively in SMIC130nm, PTM90nm and
Relative to the XOR based on CMOS complementary logic structures/same or (CCMOS-XX) circuit, base under these three standard technologies of PTM45nm
In transmission gate logical construction XOR/with or (TG-XX) circuit and XOR based on Pass-transistor logic structure/with or (CPL-XX)
Circuit these three traditional XORs/with or circuit performance characteristics, using circuit simulation tools HSPICE circuit input frequency
Rate is that four kinds of circuit structures have been carried out with Comparative Simulation under conditions of 100Mhz, corresponding supply voltage be respectively 1.2V,
1V、1V。
The Bootstrap XOR of the invention under SMIC130nm standard technologies of table 1/with or circuit and three kinds it is traditional different
Or the performance comparision of/same or circuit
As can be drawn from Table 1：The Bootstrap XOR of the present invention/same or circuit and three kinds of traditional XOR/same or electricity
Road is compared under SMIC130nm standard technologies, and delay reduces 25.4%, 8.4% and 44.8% respectively, average total power consumption difference
42.2%, 9.1% and 14% is reduced, power consumption-time delay integration does not reduce 56.9%, 16.7% and 52.6%.
The Bootstrap XOR of the invention under PTM90nm standard technologies of table 2/with or circuit and three kinds of traditional XORs/
The performance comparision of same or circuit
As can be drawn from Table 2：The Bootstrap XOR of the present invention/same or circuit and three kinds of traditional XOR/same or electricity
Road is compared under PTM90nm standard technologies, and delay reduces 19%, 7.8% and 56.1% respectively, and average total power consumption is reduced respectively
38.4%, 12.2% and 13.4%, power consumption-time delay integration do not reduce 50.1%, 19% and 62%.
The Bootstrap XOR of the invention under PTM45nm standard technologies of table 3/with or circuit and three kinds of traditional XORs/
The performance comparision of same or circuit
As can be drawn from Table 3：As can be drawn from Table 2：The Bootstrap XOR of the present invention/same or circuit and three kinds of biographies
The XOR of system/with or circuit under PTM45nm standard technologies compared with, delay reduce 30.9%, 17.1% and 64% respectively, put down
Equal total power consumption reduces 33.5%, 8.6% and 9.7% respectively, power consumption-time delay integration do not reduce 54%, 24.3% and
67.5%.
From above-mentioned comparison data, on the premise of circuit performance is not influenceed, Bootstrap proposed by the invention
XOR/same or more above-described three kinds of traditional the XORs of circuit/same or circuit has small, the average total power consumption that is delayed low and work(
Less advantage is accumulated in consumption-delay.
Example IV：As shown in Figure 10, the Bootstrap constituted using Bootstrap XOR/same or circuit of embodiment one
One-bit full addres, including Bootstrap XOR/same or circuit, summing signal generation circuit and carry signal generation circuit, summation
Signal generating circuit includes the 4th PMOS, the 5th PMOS, the 6th NMOS tube and the 7th NMOS tube, carry signal generation circuit
Including the 6th PMOS, the 7th PMOS, the 8th NMOS tube and the 9th NMOS tube, the grid of the 4th PMOS is respectively with the 3rd
The drain electrode of PMOS, the source electrode of the 5th PMOS, the grid of the grid of the 8th NMOS tube and the 7th PMOS are connected, the 4th PMOS
The source electrode of pipe respectively with the source electrode of the 6th NMOS tube, the grid of the 7th NMOS tube, the grid of the 5th PMOS, the 6th PMOS
Source electrode and the source electrode of the 8th NMOS tube are connected, and the source electrode of the 4th PMOS is inputted as the carry of Bootstrap one-bit full addres
End, the Substrate ground of the 6th NMOS tube, the drain electrode, the leakage of the 7th NMOS tube that drain respectively with the 6th NMOS tube of the 4th PMOS
The drain electrode of pole and the 5th PMOS is connected, the drain electrode of the 4th PMOS as Bootstrap one-bit full addres summation output end,
The substrate of 4th PMOS is connected with the positive pole of external power source, and the substrate of the 5th PMOS is connected with the positive pole of external power source, the
The grid of six NMOS tubes respectively with the source electrode of the 7th NMOS tube, the drain electrode of the second PMOS, the 6th PMOS grid and the 9th
The grid of NMOS tube is connected, the Substrate ground of the 7th NMOS tube, the source electrode of the source electrode of the 7th PMOS respectively with the 9th NMOS tube
And the 3rd the source electrode of NMOS tube be connected, drain electrode drain electrode, the leakage of the 7th PMOS respectively with the 8th NMOS tube of the 6th PMOS
The drain electrode of pole and the 9th NMOS tube is connected, the drain electrode of the 6th PMOS as Bootstrap one-bit full addres carry output,
The substrate of 6th PMOS and the substrate of the 7th PMOS are connected with the positive pole of external power source, the substrate of the 8th NMOS tube and
The substrate of nine NMOS tubes is grounded.
Bootstrap XOR/same or circuit in the Bootstrap one-bit full addres of example IV can also use embodiment two
Or the circuit structure of embodiment three.
For relatively Bootstrap one-bit full addres proposed by the invention respectively in SMIC130nm, PTM90nm and
One under these three standard technologies of PTM45nm relative to the XOR based on CMOS complementary logic structures/same or circuit unit is complete
Plus device (CCMOS-XX-ADDER), the one-bit full addres (TG-XX-ADDER) based on transmission gate logic XOR/same or circuit unit
These three are traditional with the one-bit full addres (CPL-XX-ADDER) based on Pass-transistor logic XOR/same or circuit unit one is complete
Plus the performance characteristics of device, using circuit simulation tools HSPICE under conditions of the incoming frequency of circuit is 100Mhz it is complete to four kinds
Plus the circuit structure of device has carried out Comparative Simulation, corresponding supply voltage is respectively 1.2V, 1V, 1V.
The Bootstrap one-bit full addres of the invention under SMIC130nm standard technologies of table 4 and three kinds of traditional one are complete
Plus the performance comparision of device
As can be drawn from Table 4：The Bootstrap one-bit full addres and three kinds of traditional one-bit full addres of the present invention exist
Delay under SMIC130nm techniques reduces 19.4%, 12% and 38.2% respectively, and average total power consumption is reduced respectively
15.5%th, 3.6% and 4.6%, power consumption-time delay integration does not reduce 31.9%, 15.2% and 41%.
The Bootstrap one-bit full addres of the invention under PTM90nm standard technologies of table 5 and three kinds of traditional one add entirely
The performance comparision of device
As can be drawn from Table 5：The Bootstrap one-bit full addres and three kinds of traditional one-bit full addres of the present invention exist
Delay under PTM90nm techniques reduces 8.3%, 0.7% and 32.2% respectively, average total power consumption reduces 27.1% respectively,
13.4% and 12.8%, power consumption-time delay integration does not reduce 33.2%, 14% and 40.9%.
The Bootstrap one-bit full addres of the invention under PTM45nm standard technologies of table 6 and three kinds of traditional one add entirely
The performance comparision of device circuit
As can be drawn from Table 6：The Bootstrap one-bit full addres and three kinds of traditional one-bit full addres circuits of the present invention
Delay under PTM45nm techniques reduces 10.4%, 3.4% and 35.6% respectively, and average total power consumption is reduced respectively
26.8%th, 12.1% and 9.1%, power consumption-time delay integration does not reduce 34.5%, 15.1% and 41.4%.
From above-mentioned comparison data, on the premise of circuit performance is not influenceed, Bootstrap one of the invention is complete
Plus small, averagely total power consumption is low and power consumption-delay product is smaller with being delayed for the more above-described three kinds of traditional one-bit full addres of device
Advantage.
The location mode conversion table of the Bootstrap one-bit full addres of the present invention of table 7
| A | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| B | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| Cin | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 |
| Sum | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 |
| Cout | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 |
From the result of Figure 11~Figure 13 simulation waveform combination table 7, Bootstrap one-bit full addres of the invention
With correct logic function.
Claims (4)
1. a kind of Bootstrap XOR/with or circuit, it is characterised in that including Bootstrap with or generation circuit and phase inverter, institute
The Bootstrap stated is same or generation circuit includes the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd
NMOS tube and the 4th NMOS tube, the described source electrode of the first PMOS are connected with the positive pole of external power source, the first described PMOS
The drain electrode of pipe is connected with the source electrode of the second described PMOS, and the grid of described the first PMOS is respectively with described first
The source electrode of NMOS tube and the source electrode of the 3rd described NMOS tube are connected, and the substrate and external power source of described the second PMOS are just
Extremely be connected, the grid of described the second PMOS respectively with the source electrode of the second described NMOS tube and the 4th described NMOS tube
Source electrode is connected, the drain electrode of described the second PMOS respectively with the draining of the first described NMOS tube, the second described NMOS tube
Drain electrode and the input of described phase inverter be connected, the drain electrode of described the second PMOS as Bootstrap XOR/with or
The same or output end of circuit, the output end of described phase inverter is used as the XOR output end of Bootstrap XOR/same or circuit, institute
The grid for the first NMOS tube stated is connected with the drain electrode of the 4th described NMOS tube, the Substrate ground of described the first NMOS tube,
The grid of the 3rd described NMOS tube is connected with the positive pole of external power source, the drain electrode of described the 3rd NMOS tube and described second
The grid of NMOS tube is connected, the Substrate ground of described the second NMOS tube, the grid and external power source of described the 4th NMOS tube
Positive pole be connected.
2. a kind of Bootstrap XOR according to claim 1/same or circuit, it is characterised in that described phase inverter includes
3rd PMOS and the 5th NMOS tube, the drain electrode respectively with the second described PMOS of the grid of described the 3rd PMOS and institute
The grid of the 5th NMOS tube stated is connected, and the source electrode of the 3rd described PMOS is connected with the positive pole of external power source, and described the
The drain electrode of three PMOSs is connected with the drain electrode of the 5th described NMOS tube, and the drain electrode of the 3rd described PMOS is used as Bootstrap
XOR/with or circuit XOR output end, the source ground of described the 5th NMOS tube.
3. the Bootstrap one-bit full addres of Bootstrap XOR/same or circuit composition described in usage right requirement 2, its feature
It is to include Bootstrap XOR/same or circuit, summing signal generation circuit and carry signal generation circuit, described summation letter
Number generation circuit includes the 4th PMOS, the 5th PMOS, the 6th NMOS tube and the 7th NMOS tube, and described carry signal is produced
Circuit includes the 6th PMOS, the 7th PMOS, the 8th NMOS tube and the 9th NMOS tube, and the grid of the 4th described PMOS divides
Not with the draining of the 3rd described PMOS, the source electrode of the 5th described PMOS, the grid of the 8th described NMOS tube and institute
The grid of the 7th PMOS stated is connected, the source electrode of described the 4th PMOS source electrode respectively with the 6th described NMOS tube,
The grid of the 7th described NMOS tube, the grid of the 5th described PMOS, the source electrode of the 6th described PMOS and described
The source electrode of 8th NMOS tube is connected, and the source electrode of the 4th described PMOS is inputted as the carry of Bootstrap one-bit full addres
End, the Substrate ground of described the 6th NMOS tube, the drain electrode of described the 4th PMOS respectively with the 6th described NMOS tube
Drain electrode, the drain electrode of described 7th NMOS tube and the drain electrode of the 5th described PMOS are connected, the leakage of described the 4th PMOS
Pole is used as the summation output end of Bootstrap one-bit full addres, the positive pole phase of the substrate and external power source of described the 4th PMOS
Even, the substrate of the 5th described PMOS is connected with the positive pole of external power source, the grid of described the 6th NMOS tube respectively with institute
The source electrode for the 7th NMOS tube stated, the draining of the second described PMOS, the grid and described of the 6th described PMOS
The grids of nine NMOS tubes is connected, the Substrate ground of described the 7th NMOS tube, the source electrode of described the 7th PMOS respectively with institute
The source electrode for the 9th NMOS tube stated and the source electrode of the 3rd described NMOS tube are connected, the drain electrode of described the 6th PMOS respectively with
The draining of the 8th described NMOS tube, the drain electrode of the 7th described PMOS and the drain electrode of the 9th described NMOS tube are connected, institute
The drain electrode for the 6th PMOS stated is used as the carry output of Bootstrap one-bit full addres, the substrate of described the 6th PMOS
And the substrate of the 7th described PMOS is connected with the positive pole of external power source, the substrate of described the 8th NMOS tube with it is described
The substrate of 9th NMOS tube is grounded.
4. Bootstrap one-bit full addres according to claim 3, it is characterised in that the raceway groove of the first described PMOS
Length, the channel length of the second described PMOS, the channel length of the 3rd described PMOS, described the 4th PMOS
Channel length, the channel length of the 5th described PMOS, the channel length of the 6th described PMOS, the 7th described PMOS
The channel length of pipe, the channel length of the first described NMOS tube, the channel length of the second described NMOS tube, the described the 3rd
It is the channel length of NMOS tube, the channel length of the 4th described NMOS tube, the channel length of the 5th described NMOS tube, described
The channel length of 6th NMOS tube, the channel length of the 7th described NMOS tube, the channel length of the 8th described NMOS tube and
The channel length of the 9th described NMOS tube be under SMIC130nm standard technologies or PTM90nm standard technologies under or PTM45nm
1~1.2 times of minimum channel length under standard technology.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410150247.1A CN103957002B (en) | 2014-04-15 | 2014-04-15 | A kind of Bootstrap XOR/same or circuit and Bootstrap one-bit full addres |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410150247.1A CN103957002B (en) | 2014-04-15 | 2014-04-15 | A kind of Bootstrap XOR/same or circuit and Bootstrap one-bit full addres |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103957002A CN103957002A (en) | 2014-07-30 |
| CN103957002B true CN103957002B (en) | 2017-10-31 |
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| CN110995238B (en) * | 2019-11-26 | 2023-04-25 | 宁波大学 | Full adder based on swing recovery transmission pipe logic |
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