CN113409870A - Flash memory erasing method, sector selection circuit, device and electronic equipment - Google Patents
Flash memory erasing method, sector selection circuit, device and electronic equipment Download PDFInfo
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- CN113409870A CN113409870A CN202110737198.1A CN202110737198A CN113409870A CN 113409870 A CN113409870 A CN 113409870A CN 202110737198 A CN202110737198 A CN 202110737198A CN 113409870 A CN113409870 A CN 113409870A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
Abstract
The invention discloses a flash memory erasing method, a sector selection circuit, a device and electronic equipment, wherein the erasing method sequentially erases and verifies sectors after a whole block is erased, sectors which pass the erasing verification are not selected by sector DEC any more, sectors which do not pass the erasing verification are selected by sector DEC, the differential pressure of the unselected sectors is smaller than the erasing voltage and can not be erased, and the differential pressure of the selected sectors is larger than the erasing voltage and can be erased again. The erasing method avoids the over-erasing result caused by inconsistent erasing speed (particularly repeated erasing) in the traditional mode, greatly reduces required over-erasing detection and repairing actions, and greatly improves the performance and efficiency of block erasing.
Description
Technical Field
The invention belongs to the technical field of memories, and particularly relates to a flash memory erasing method, a sector selection circuit, a flash memory erasing device and electronic equipment.
Background
As shown in the prior art flash memory architecture and decoding circuit schematic diagrams of FIGS. 1 and 2, sector ADDR (address lines) are connected to sector DEC (decoder), which receive logic signals and are decoded by the decoder to output sector select signals (sector _ sel <16.0 >) and inverted sector select signals (sector _ sel _ b <16.0 >), wherein the inverted sector select signals are coupled to an inverter in the driver circuit to select a sector.
There are many different instructions for an erase operation of a NOR flash, in terms of erase blocks (typical values):
1. the minimum number of erasures is 4 word lines per sector;
2. the maximum number of erasures is 64 wordlines in one block, i.e., 16 sectors.
When a user issues a sector erasing instruction, a sector DEC is responsible for resolving a 4-bit sector address input by the user to 1 selected sector (a traditional 4-16 decoder), so that WL (WORDLINE) = -10V and TPW (TRIPLE P-WELL, P WELL region) =10V of the sector are controlled to erase the sector;
when a user issues a block erase command, it is conventional to force all sector select signals (16) to be selected in sector DEC (decoder) by a logic signal, so that WL in all sectors is 10V and TPW is 10V by the sector driving circuit. Thereby achieving block erase. The advantage of this is that when block erase is needed, all sectors can be erased at the same time and completed almost at the same time if their erase characteristics are identical, reducing time.
However, such a structure has a significant disadvantage in block erase. When a user issues a block erase command, the 15 sectors which are not erased repeatedly can be erased quickly, and the sectors which are erased repeatedly can be erased slowly, so that the erasing action must be finished until the sectors which are erased repeatedly are finished. And because the traditional sector DEC can only select one sector or all sectors, other sectors which are not erased repeatedly can still not be separated during the erasing action even if the sectors are judged to be sectors which are erased by the algorithm, and the sectors which are not erased repeatedly can still be erased continuously while the sectors which are erased repeatedly are erased. The consequence of this is that the NOR flash cells of a sector that has not been erased repeatedly are over-erased, and the leakage that it brings affects the current of all NOR flash cells on the same bitline. After the NOR flash cell continues to erase and write, the erasing performance of the NOR flash cell is significantly reduced, and the erasing time becomes very long.
Accordingly, the prior art is in need of improvement and development.
Disclosure of Invention
Embodiments of the present invention provide a flash memory erasing method, a sector selection circuit, an apparatus, and an electronic device, which can shield an erasing operation of a sector that is erased quickly, thereby avoiding an over-erasing result caused by an inconsistent erasing speed (especially, whether there is repeated erasing), greatly reducing required over-erasing detection and repair actions, and greatly improving performance and efficiency of block erasing.
In a first aspect, an embodiment of the present invention provides a flash memory erasing method, including the following steps:
after the erasing operation is carried out on the block, sequentially carrying out erasing verification on the sectors in the block;
continuing to execute the erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the verification, and finishing erasing the block; and the number of the first and second groups,
the bias voltage for the erase-verified sector is set to a second voltage such that the erase-verified sector is not erased again before erasing the block is completed.
Optionally, erasing the block comprises applying a first voltage to all word lines of the block.
Optionally, the first voltage is-10V.
Optionally, the second voltage is 2V.
Therefore, according to the flash memory erasing method provided by the invention, after the whole block is erased, erasing verification is carried out on the sectors in sequence, the sectors passing the erasing verification are not selected by the sector DEC any more, the sectors not passing the erasing verification are selected by the sector DEC, the differential pressure of the unselected sectors is smaller than the erasing voltage and cannot be erased, and the differential pressure of the selected sectors is larger than the erasing voltage and is erased again. The erasing method avoids the over-erasing result caused by inconsistent erasing speed (particularly repeated erasing) in the traditional mode, greatly reduces required over-erasing detection and repairing actions, and greatly improves the performance and efficiency of block erasing.
In a second aspect, the sector selection circuit provided in the embodiments of the present invention is configured to select a sector according to an erase verification signal of the sector, so as to apply different bias voltages to a sector that passes the erase verification and a sector that does not pass the erase verification, and includes an and gate, a latch, and a nor gate, where a first input terminal of the and gate is connected to the erase verification passing signal, a second input terminal of the and gate is connected to an enable signal, and an output terminal of the and gate is connected to a second input terminal of the latch;
the first input end of the latch is connected with a sector selection signal, the third input end of the latch is connected with an inverted signal of a reset signal, and the output end of the latch is connected with the second output end of the NOR gate;
the first input end of the NOR gate is connected to the inverted signal of the sector selection signal, and the output end of the NOR gate is output to the sector.
Optionally, the latch includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first inverter, and a second inverter, where the PMOS transistor, the first NMOS transistor, and the second NMOS transistor are sequentially connected in series between Vdd and GND, the PMOS transistor and the first NMOS transistor are connected to one end of the first inverter and one end of the second inverter that are cross-connected, the other end of the first inverter and the other end of the second inverter that are cross-connected are connected to a second input end of the nor gate, a gate of the PMOS transistor is connected to an inverted signal of the reset signal, a gate of the first NMOS transistor is connected to an output end of the and gate, and a gate of the second NMOS transistor is connected to the sector selection signal.
In a third aspect, an embodiment of the present invention provides a flash memory erasing apparatus, including:
the verification module is used for sequentially performing erasure verification on the sectors in the block after the erasure operation is performed on the block;
the erasing module is used for continuously executing erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the erasing verification, and finishing erasing the block; and the number of the first and second groups,
and a voltage setting module for setting the bias voltage of the erase-verified sector to a second voltage so that the erase-verified sector is not erased again before the erase of the block is completed.
In a fourth aspect, an electronic device according to an embodiment of the present invention includes a processor and a memory, where the memory stores a computer program, and the processor is configured to execute any one of the methods described above by calling the computer program stored in the memory.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
FIG. 1 is a diagram of a prior art flash memory structure.
Fig. 2 is a schematic diagram of a decoding circuit of the prior art.
FIG. 3 is a block diagram of a flash memory erase method according to the present invention.
FIG. 4 is a diagram of a decoding circuit according to the present invention.
FIG. 5 is a circuit diagram of a sector selection circuit according to the present invention.
FIG. 6 is a circuit diagram of a latch in the sector select circuit according to the present invention.
Fig. 7 is a truth table of fig. 6.
Fig. 8 is a timing diagram of the operation of the circuit of fig. 5.
Fig. 9 is a schematic view of the electronic device of the present invention.
Description of reference numerals: 1. an AND gate; 2. a latch; 21. a PMOS tube; 22. a first NMOS transistor; 23. a second NMOS transistor; 24. a first inverter; 25. a second inverter; 3. a NOR gate; 4. an electronic device; 41. a processor; 42. a memory.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 3, a flash memory erasing method includes the following steps:
after the erasing operation is carried out on the block, sequentially carrying out erasing verification on the sectors in the block;
continuing to execute the erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the verification, and finishing erasing the block; and the number of the first and second groups,
the bias voltage for the erase-verified sector is set to a second voltage such that the erase-verified sector is not erased again before erasing the block is completed.
There are various methods for implementing the above erasing, which are not limited herein, and only one of the above erasing methods is provided below:
firstly, erasing a block;
step two, selecting the first sector in the block and carrying out erasure verification, and judging whether the sector erasure verification operation passes;
step three, when the erasing verification is passed, the sector is deselected, when the erasing verification is failed, the sector is selected continuously, and after the erasing verification of the sector is completed, the erasing verification of the next sector is continued until the erasing verification of all sectors in the block is completed;
step four, applying a first voltage to the word lines of all selected sectors and applying a second voltage to the word lines of all unselected sectors;
and step five, if at least one sector fails to pass the erasing verification, jumping to the step one, and finishing the block erasing operation after all sectors pass the erasing verification.
In some embodiments, erasing a block includes applying a first voltage to all word lines of the block.
In certain embodiments, the first voltage is-10V.
In some embodiments, the second voltage is 2V.
In the erasing method of the invention, the sector DEC (decoder) selects the WL of the sector and performs the verification after applying the erasing voltage, if at least one sector in the block does not pass the erasing verification, the erasing operation will continue. The sector passing the erase verification cannot be selected by the sector DEC, in the subsequent erase operation, the WL of the sector not passing the erase verification is applied with a higher bias typical value of 2V in the sector DEC, and conversely, the sector not passing the erase verification is continuously selected by the sector DEC, and the voltage applied to the WL in the subsequent erase operation is-10V.
During the whole block erasing operation, once the sector completes the erasing verification, the WL is biased to 2V by the unselected sector in the subsequent erasing operation, so that the pressure difference between the TPW and the WL is only 10V-2V =8V, and the erasing is not enough to occur. While the WL of the sector that does not pass the erase verify would be biased to-10V, with a 10V- (-10V) =20V differential to the TPW, sufficient for an erase to occur.
By means of the design, the erasing operation shielding of the sector which is erased quickly is completed, so that the over-erasing result caused by inconsistent erasing speed (particularly repeated erasing or erasing) in the traditional mode is avoided, the required over-erasing detection and repair actions are greatly reduced, and the performance and the efficiency of block erasing are greatly improved.
Fig. 5 shows a circuit schematic of the sector selection circuit of the present invention. The erasing and verifying circuit comprises an AND gate 1, a latch 2 and a NOR gate 3, wherein a first input end of the AND gate 1 is connected to an erasing and verifying passing signal, a second input end of the AND gate 1 is connected to an enabling signal, and an output end of the AND gate 1 is connected to a second input end of the latch 2; a first input end of the latch 2 is connected with a sector selection signal, a third input end of the latch 2 is connected with an inverted signal of a reset signal, and an output end of the latch 2 is connected with a second output end of the NOR gate 3; a first input terminal of the nor gate 3 is connected to an inverted signal of the sector selection signal, and an output terminal of the nor gate 3 is output to the sector.
In fig. 5, ev _ pass is an erase verify pass signal, which indicates an erase verify pass when it is high, and indicates an erase verify fail when it is low; lat _ sec is an enable signal of the latch 2, and the latch 2 is active when it is high and inactive when it is low; rst _ sec _ lat is a reset signal of the latch 2, rst _ sec _ lat _ b is an inverted signal of the reset signal of the latch 2, sel is a selected signal output by the decoder, sector _ sel _ b is an inverted signal of sel, sel and sector _ sel _ b are output by sector DEC, output sector =1 indicates that the sector is selected, and output sector =0 indicates that the sector is not selected.
Fig. 6 shows a circuit schematic of the latch 2 in the sector selection circuit of the present invention. The latch 2 comprises a PMOS tube 21, a first NMOS tube 22, a second NMOS tube 23, a first phase inverter 24 and a second phase inverter 25, the PMOS tube 21, the first NMOS tube 22 and the second NMOS tube 23 are sequentially connected between Vdd and GND in series, one ends of the first phase inverter 24 and the second phase inverter 25 which are connected in a cross mode are connected between the PMOS tube 21 and the first NMOS tube 22, the other ends of the first phase inverter 24 and the second phase inverter 25 which are connected in the cross mode are connected to the second input end of the NOR gate 3, the grid of the PMOS tube 21 is connected to the inverted signal of the reset signal, the grid of the first NMOS tube 22 is connected to the output end of the AND gate 1, the grid of the second NMOS tube 23 is connected to one end of the sector selection signal, and the other ends of the first phase inverter 24 and the second phase inverter 25 which are connected in the cross mode are connected to the second input end of the NOR gate 3.
According to the circuit and the truth table shown in fig. 7, the specific operation process is as follows:
when rst _ sec _ lat _ b is 1 and sel and inhibit signals are 1 at the same time, the PMOS tube 21 is cut off, the first NMOS tube 22 and the second NMOS tube 23 are conducted, and after the phases of the signals are reversed through the first inverter 24 and the second inverter 25, pass _ lat is output as 1; when rst _ sec _ lat _ b is 0, the PMOS tube 21 is conducted, sel and inhibit signals are not any signals with 1 at the same time, and pass _ lat is output as 0 after the phases of the signals are inverted by the first inverter 24 and the second inverter 25.
The circuit according to the above, its specific operation process is as follows:
as shown in the timing chart of fig. 8, when a user issues a block erase command, rst _ sec _ lat _ b =0 is reset for all latches 2, and pass _ lat =0, so that the secotr driving circuit is determined by a sector DEC, all sectors are forcibly selected by a block _ erase signal, the voltage of all word lines in the block is set to-10V, and all memory cells are simultaneously erased. And after the erasing operation is finished, performing erasing verification operation on each sector respectively.
When a Sector is selected for erase verification (i.e., Sector EV period), the sel terminal of the Sector latch is selected and the verification results are reflected on the EV _ pass signal. If the current sel =1, rst _ sec _ lat _ b =0, ev _ pass =1 and inhibit =1 when the erase verification passes, then the output signal of sector latch pas _ lat =1 and output sector =0, the sector is no longer selected, meaning that the sector is selected for erase first, and the erase verification passes and is canceled; when the erase verification fails, ev _ pass =0 and inhibit =0, then the output signal pass _ lat =0 and output sector =1 of the sector latch means that the sector is selected to be erased first, and is not passed the erase verification, and is still selected by the sector DEC. The sector erase and erase verify are completed and the operation continues to be repeated for the next sector.
The present invention also provides a flash memory erasing apparatus, comprising:
the erasing module is used for erasing the block;
the cyclic operation module is used for circularly executing the erasing verification operation on the sector of the erasing module;
the judging and selecting module is used for deselecting the sectors which pass the erasure verification and continuously selecting the sectors which do not pass the erasure verification;
the cyclic operation module can cyclically execute the erasing verification operation on the sector of the erasing module, and the judgment and selection module can continuously select the sector which does not pass the erasing verification or deselect the sector which passes the erasing verification in the cyclic operation module so as to execute the erasing operation or jump out the erasing operation.
As shown in fig. 9, the present invention also provides an electronic device. The electronic device 4 comprises a processor 41 and a memory 42. The processor 41 is electrically connected to the memory 42. The processor 41 is a control center of the electronic device 4, connects various parts of the entire electronic device with various interfaces and lines, and performs various functions of the electronic device and processes data by running or calling a computer program stored in the memory 42 and calling data stored in the memory 42, thereby monitoring the electronic device 4 as a whole.
In this embodiment, the processor 41 in the electronic device 4 loads instructions corresponding to one or more processes of the computer program into the memory 42 according to the following steps, and the processor 41 runs the computer program stored in the memory 42, so as to implement various functions: after the erasing operation is carried out on the block, sequentially carrying out erasing verification on the sectors in the block;
continuing to execute the erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the verification, and finishing erasing the block; and the number of the first and second groups,
the bias voltage for the erase-verified sector is set to a second voltage such that the erase-verified sector is not erased again before erasing the block is completed.
The memory 42 may be used to store computer programs and data. The memory 42 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 41 executes various functional applications and data processing by calling a computer program stored in the memory 42.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present invention, and is not intended to limit the scope of the present invention, and it will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A flash memory erasing method for erasing a block in a flash memory, comprising the steps of:
after the erasing operation is carried out on the block, sequentially carrying out erasing verification on the sectors in the block;
continuing to execute the erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the verification, and finishing erasing the block; and the number of the first and second groups,
the bias voltage for the erase-verified sector is set to a second voltage such that the erase-verified sector is not erased again before erasing the block is completed.
2. The method of claim 1, wherein erasing the block comprises applying the first voltage to all word lines of the block.
3. The method of claim 2, wherein the first voltage is-10V.
4. The method of claim 1, wherein the second voltage is 2V.
5. A sector selection circuit for selecting a sector in accordance with an erase verification signal of the sector to apply different bias voltages to a sector which passes erase verification and a sector which does not pass erase verification, comprising:
the sector erase verification device comprises an AND gate (1), a latch (2) and a NOR gate (3), wherein a first input end of the AND gate (1) is connected to an erase verification pass signal of a sector, a second input end of the AND gate (1) is connected to an enable signal, and an output end of the AND gate (1) is connected to a second input end of the latch (2);
a first input end of the latch (2) is connected with a sector selection signal, a third input end of the latch (2) is connected with an inverted signal of a reset signal, and an output end of the latch (2) is connected with a second output end of the NOR gate (3);
the first input end of the NOR gate (3) is connected to the inverted signal of the sector selection signal, and the output end of the NOR gate (3) is output to the sector.
6. A sector selection circuit according to claim 5, characterised in that the latch (2) comprises a PMOS transistor (21), a first NMOS transistor (22), a second NMOS transistor (23), a first inverter (24), the PMOS transistor (21), the first NMOS transistor (22) and the second NMOS transistor (23) are sequentially connected in series between Vdd and GND, the PMOS transistor (21) and the first NMOS transistor (22) are connected to one ends of the first inverter (24) and the second inverter (25) in cross connection, the other ends of the first inverter (24) and the second inverter (25) in cross connection are connected to the second input end of the NOR gate (3), the grid of the PMOS transistor (21) is connected to an inverted signal of a reset signal, the grid of the first NMOS transistor (22) is connected to the output end of the AND gate (1), and the grid of the second NMOS transistor (23) is connected to a sector selection signal.
7. A flash memory erasing apparatus for erasing a block in a flash memory, comprising:
the verification module is used for sequentially performing erasure verification on the sectors in the block after the erasure operation is performed on the block;
the erasing module is used for continuously executing erasing operation on the sector with the failed erasing verification until all the sectors in the block pass the erasing verification, and finishing erasing the block; and the number of the first and second groups,
and a voltage setting module for setting the bias voltage of the erase-verified sector to a second voltage so that the erase-verified sector is not erased again before the erase of the block is completed.
8. An electronic device, characterized in that it comprises a processor (41) and a memory (42), a computer program being stored in the memory (42), the processor (41) being adapted to perform the method according to any one of claims 1-4 by calling the computer program stored in the memory (42).
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| CN104008777A (en) * | 2013-02-25 | 2014-08-27 | 北京兆易创新科技股份有限公司 | Erasing method of nonvolatile memory, and apparatus thereof |
| CN112313747A (en) * | 2018-12-25 | 2021-02-02 | 英特尔公司 | Reduced number of erase verifications for non-volatile storage media |
| CN111667876A (en) * | 2019-03-05 | 2020-09-15 | 爱思开海力士有限公司 | Semiconductor device with a plurality of transistors |
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