CN115312100B - Post-programming method, erasing method, device, electronic equipment and storage medium - Google Patents
Post-programming method, erasing method, device, electronic equipment and storage medium Download PDFInfo
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- CN115312100B CN115312100B CN202211229109.3A CN202211229109A CN115312100B CN 115312100 B CN115312100 B CN 115312100B CN 202211229109 A CN202211229109 A CN 202211229109A CN 115312100 B CN115312100 B CN 115312100B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
Abstract
The invention relates to the technical field of chips, and particularly discloses a post-programming method, an erasing method, a device, electronic equipment and a storage medium, wherein the post-programming method comprises the following steps: acquiring an over-erased sector; dividing all over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector; performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed; the post-programming method divides the over-erased sector in the memory array into a plurality of operation areas for post-programming operation, and distinguishes the post-programming operation which is originally performed on the whole over-erased sector at one time for a plurality of times and independently aiming at the memory cells on different word lines, thereby ensuring that a bit line charge pump which provides post-programming voltage in a bit line has enough driving capability relative to the memory cells, and improving the programming capability of the post-programming operation.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a post-programming method, an erasing apparatus, an electronic device, and a storage medium.
Background
In the use process of a flash memory chip, it is often necessary to perform an erase operation on a memory cell (generally, a sector is used as an erase unit), an over erase phenomenon may occur after the erase operation, the threshold voltage of the over erased memory cell is particularly low, and in the process of reading data of the memory cells, the memory cell has leakage under a non-selection gate voltage (generally, 0V), so that a problem that correct data cannot be read on a word line is caused, and particularly, after multiple erase cycles, uncertainty of the threshold voltage is increased.
Therefore, in the prior art, after the erase process, an over-erase repair process is performed on the over-erased sector having the over-erased memory cells, and the repair process is generally performed by a post-program (also called a light program) operation, which is generally a light program operation performed on a sector basis, so as to adjust the threshold voltage of the memory cells in the sector to be higher than a normal range (generally verified by a verify voltage read).
The existing post-programming operation uses a sector as an operation unit, that is, a post-programming voltage is applied by a charge pump on a word line and a bit line of the sector to perform a light-level programming operation, the bit line charge pump needs to apply the post-programming voltage to all memory cells (cells) on the bit line to generate a corresponding post-programming current, and because the number of the memory cells on the same bit line is large, the programming current is pulled very low, the problem of insufficient driving capability of the bit line charge pump often occurs, and even the post-programming operation fails.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The present application aims to provide a post-programming method, an erasing apparatus, an electronic device, and a storage medium, which ensure that a post-programming operation is smoothly performed without changing the driving capability of a bit line charge pump.
In a first aspect, the present application provides a post-programming method for performing a post-programming process on an over-erased sector of a memory array having over-erased memory cells, the post-programming method comprising the steps of:
acquiring the over-erased sector;
dividing all the over-erased sectors into a plurality of operation areas according to the word line distribution condition in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
and performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
According to the post-programming method, the post-programming operation which is originally performed on the whole over-erased sector at one time is divided into multiple independent post-programming operations aiming at the memory cells on different word lines, so that the current generated on each memory cell corresponding to the post-programming voltage applied by the bit line is pulled high, namely, the bit line charge pump which provides the post-programming voltage in the bit line has enough driving capability relative to the memory cells, and the over-erased memory cells are repaired smoothly.
The post-programming method, wherein the number of word lines occupied by the operating area in each of the over-erased sectors is continuous.
In the post-programming method of the example, when each operation area has a plurality of memory cells corresponding to word lines in a corresponding over-erased sector, the word lines are numbered consecutively, that is, the memory cells are adjacently connected memory cells in the spatial arrangement of the memory array, so that the uniform post-programming processing operation can be conveniently carried out on the memory cells.
The post-programming method, wherein the number of word lines occupied by the operating area in each of the over-erased sectors is equal.
In the post-programming method of the example, the number of the memory cells of the operation area corresponding to each bit line in each over-erased sector, which need to be subjected to the post-programming operation, is equal, so that the time consumed by the post-programming operation corresponding to the memory cells in each over-erased sector in each operation area is ensured to be similar, and the phenomenon that the efficiency of the whole post-programming operation is influenced by the overlarge time difference consumed by the post-programming operation due to the fact that the operation area contains different numbers of the memory cells in different over-erased sectors is avoided.
The post-programming method comprises the steps that the number of the operation areas is positive even number, the total number of the word lines of each over-erased sector can be divided by the total number of the word lines of each over-erased sector, and the number of the word lines occupied by each operation area is equal.
The post-programming method, wherein the word lines occupied by the operation area in each of the over-erased sectors are the same in number.
In the post-programming method of this example, the word line numbers occupied by the operation regions in each over-erased sector are the same, which indicates that the positions of the memory cells occupied by each operation region in each over-erased sector are the same, i.e. the distances between the corresponding memory cells and the word line charge pump and the bit line charge pump are equal, so as to further ensure that the time consumed by the post-programming operation performed for each operation region is similar, and to facilitate quick selection of the memory cells corresponding to the operation regions, and to facilitate control of the post-programming voltage applied to the entire operation region.
The post-programming method, wherein the step of performing the post-programming operation on the operation regions one by one includes:
and performing post-programming operation on the operation areas one by one according to the word line arrangement sequence in the over-erased sector.
In a second aspect, the present application further provides an erasing method for erasing a target area in a memory array, the erasing method including the steps of:
carrying out erasing operation on the target area;
acquiring an over-erased sector with an over-erased storage unit in the target area;
dividing all the over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
and performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
According to the erasing method, after the target area is erased, the over-erased sector in the target area is divided into the plurality of operation areas to carry out the post-programming operation, and the post-programming operation which is originally carried out on the whole over-erased sector at one time is divided into the plurality of independent post-programming operations aiming at the storage units on different word lines, so that the programming capability of the post-programming operation is improved, the post-programming operation on the over-erased storage units can be smoothly carried out, and the smooth completion of the whole erasing processing is ensured.
In a third aspect, the present application further provides a post-programming apparatus for performing a post-programming process on an over-erased sector of a memory array having over-erased memory cells, the post-programming apparatus comprising:
an obtaining module, configured to obtain the over-erased sector;
the dividing module is used for dividing all the over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, so that each operation area comprises storage units corresponding to a plurality of word lines in each over-erased sector;
and the post-programming module is used for performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
According to the post-programming device, the division module is utilized to divide the post-programming operation which is originally performed on the whole over-erased sector at one time to the multiple independent post-programming operations aiming at the memory cells on different word lines, so that the current generated on each memory cell corresponding to the post-programming voltage applied by the bit line is pulled high, namely the bit line charge pump which provides the post-programming voltage in the bit line is ensured to have enough driving capability relative to the memory cells, and the over-erased memory cells are repaired smoothly.
In a fourth aspect, the present application further provides an electronic device comprising a processor and a memory, wherein the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a fifth aspect, the present application further provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method as provided in the first aspect.
As can be seen from the above, the present application provides a post-programming method, an erasing method, an apparatus, an electronic device, and a storage medium, wherein the post-programming method divides an over-erased sector in a storage array into a plurality of operation regions for performing a post-programming operation, each of the operation regions corresponds to a region where each of the over-erased sectors occupies corresponding to a plurality of word lines, and distinguishes the post-programming operation originally performed on the entire over-erased sector for a plurality of times and independently aims at storage units on different word lines, so that a current generated on each of the storage units corresponding to a post-programming voltage applied to a bit line is pulled up, that is, a bit line charge pump providing the post-programming voltage in the bit line has sufficient driving capability with respect to the storage units, thereby improving the programming capability of the post-programming operation without changing the driving capability of the bit line charge pump, and ensuring that the post-programming operation can be performed on the over-erased storage units smoothly, so as to repair the over-erased storage units smoothly.
Drawings
Fig. 1 is a flowchart of a post-programming method according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of an erasing method according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a post-programming device according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 201. an acquisition module; 202. a dividing module; 203. a post-programming module; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In the existing post-programming operation, a sector is taken as an operation unit, that is, a post-programming voltage is applied by a charge pump on a word line and a bit line of the sector to perform a light programming operation, the bit line charge pump needs to apply the post-programming voltage on all memory cells (cells) on the bit line to generate a corresponding post-programming current, taking a NOR FLASH chip as an example, the post-programming operation needs to apply a post-programming voltage of 1.5V on all word line ends and apply a post-programming voltage of 4V on the bit line end, for one bit line, the more memory cells are connected in series (the more word lines in the sector), the smaller the post-programming current in the bit line direction is, so that the weaker programming capability of the post-programming operation is, the more difficult the threshold voltage of the memory cells on the corresponding bit line is to be regulated and increased, and therefore, the problem of insufficient driving capability of the bit line charge pump often occurs, and even the post-programming operation fails; the above problem is also solved by increasing the driving capability of the bit line charge pump (generally by changing the circuit structure of the bit line charge pump), but the bit line charge pump is increased in size by this processing method, which is not favorable for the development of refinement and light weight of the chip.
In a first aspect, referring to fig. 1, fig. 1 is a post-programming method for performing a post-programming process on an over-erased sector of a memory array having over-erased memory cells, in some embodiments of the present application, the post-programming method including the steps of:
s101, acquiring an over-erased sector;
specifically, the memory array is composed of a plurality of independent sectors, and each sector in the memory array generally has the same specification (i.e., the number of word lines is equal to the number of bit lines), and has the same number of memory cells.
More specifically, the post-programming method in the embodiments of the present application mainly performs repair processing on over-erased memory cells, and in the prior art, the erase operation of a flash memory chip is generally performed by using a sector as an operation unit, the memory cells in the erased sector generally have different threshold voltages, the memory cells with too low threshold voltages are over-erased memory cells (over erase cells), and new data cannot be written into the over-erased memory cells when the over-erased memory cells are normally programmed once, so that the normal use of the chip is affected, and therefore, before reusing the memory cells, the over-erased memory cells need to be subjected to post-programming processing, and the threshold voltages of the over-erased memory cells are adjusted to a normal range; in order to save circuit resources and improve operation efficiency, generally, the position of the over-erased memory cell is not specifically positioned and post-programming operation is performed on the over-erased memory cell, but all over-erased sectors where the over-erased memory cell is located are simultaneously subjected to post-programming operation, so that the threshold voltages of the memory cells in the whole over-erased sector slightly rise until the threshold voltages of all the memory cells are within a normal range (generally, a plurality of verification voltages are adopted to verify the distribution of the threshold voltages of the memory cells) to repair the whole over-erased sector.
S102, dividing all over-erased sectors into a plurality of operation areas according to word line distribution conditions in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
specifically, each divided operation region includes a certain number of memory cells in each over-erased sector, and the memory cells are selected and divided into corresponding operation regions by using word lines as reference units, generally speaking, the number of memory cells corresponding to each word line in the memory array is the same, so that the number of memory cells included in the operation region and the number of memory cells corresponding to each word line are in integral multiple relation, and if the number of memory cells corresponding to each word line is n (i.e., the number of corresponding bit lines is n), each operation region correspondingly includes memory cells corresponding to m word lines, that is, the operation region includes m × n memory cells (m and n are positive integers).
More specifically, after the division process, each of the over-erased sectors is divided into a plurality of small areas according to the word line distribution, each of the small areas being a small portion of the corresponding operating area, whereby each of the mutually independent over-erased sectors is entirely divided into the corresponding operating area.
And S103, performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
Specifically, completing the post-program operation on all over-erased sectors in the entire memory array is considered as completing the post-program operation on the entire memory array.
More specifically, as can be seen from the foregoing, the conventional post-program operation is generally performed on all over-erased sectors, and for each over-erased sector, the post-program operation is performed directly on the entire over-erased sector, that is, all word lines in the over-erased sector are selected at one time to perform the post-program operation, and then the post-program operation is performed on all memory cells in the over-erased sector by applying corresponding post-program voltages to the word lines and bit lines in the over-erased sector, and the operation of selecting all memory cells at one time causes the voltage applied to the bit lines to be pulled to be low corresponding to the current generated on each memory cell, so that for each memory cell, the post-program operation takes a long time to complete, and the repair of the over-erased memory cells may fail because the threshold voltage of the over-erased memory cells cannot be pulled up due to too low current; in the embodiment of the application, the memory cells in each over-erased sector are divided into a plurality of operation areas according to the characteristics of word line distribution, so that the post-programming operation performed on each operation area is the post-programming operation performed by selecting the memory cells corresponding to the corresponding number of word lines in each over-erased sector, the number of the memory cells applying voltage corresponding to each bit line is effectively reduced, and under the condition that the voltage applied to the bit line is not changed, the current generated on each memory cell corresponding to the post-programming voltage applied to the bit line is pulled up, i.e. the bit line charge pump providing the post-programming voltage in the bit line has enough driving capability relative to the memory cells, so that the programming capability of the post-programming operation is improved, and the post-programming operation on the over-erased memory cells can be smoothly performed, so as to smoothly repair the over-erased memory cells; each over-erased sector is independent of the other, so that the post-program voltages applied to the word lines and bit lines do not affect each other in response to different over-erased sectors.
More specifically, the post-program operation is performed on the operation regions one by one, and for an over-erased sector, although the number of post-program operations is increased, the post-program efficiency of each memory cell can be improved, so that the time consumed in the whole post-program process by the post-program method of the embodiment of the present application is similar to the time consumed by the post-program method of the prior art.
More specifically, in the post-programming method in the prior art, the whole over-erased sector is subjected to post-programming processing, and if an over-erased unit with a severe over-erase exists, the threshold voltages of all the memory cells with a relatively high threshold voltage originally are programmed to be higher after the whole over-erased sector is subjected to post-programming processing.
The post-programming method divides an over-erased sector in a memory array into a plurality of operation areas for post-programming operation, each operation area corresponds to each over-erased sector and occupies an area corresponding to a plurality of word lines, the post-programming operation originally performed on the whole over-erased sector for one time is divided into a plurality of independent post-programming operations aiming at memory cells on different word lines, so that the current generated on each memory cell by the post-programming voltage applied by a bit line is correspondingly increased, namely, the bit line charge pump providing the post-programming voltage in the bit line has enough driving capability relative to the memory cells, the programming capability of the post-programming operation is improved, the post-programming operation on the over-erased memory cells can be smoothly performed, and the over-erased memory cells can be smoothly repaired.
In addition, the post-programming method of the embodiment of the application can also ensure that the post-programming operation can be smoothly carried out under the limited driving capability of the bit line charge pump, so that the bit line charge pump does not need to increase the size to improve the driving capability and can be made smaller, the circuit size in the whole chip is reduced, and the light weight of the chip is facilitated.
In some preferred embodiments, the operating regions occupy consecutive numbers of word lines in each over-erased sector.
Specifically, when each operation area has a plurality of memory cells corresponding to word lines in a corresponding over-erased sector, the word lines are numbered consecutively, that is, the memory cells are adjacent and connected memory cells in the spatial arrangement of the memory array, which facilitates uniform post-programming operation of the memory cells.
More specifically, in the prior art, word lines in a sector have corresponding numbers in an arrangement order, which is convenient for a word line selector (decoder) to select the corresponding word lines for operation, where the word line numbers are denoted as WL <0>, WL <1>, WL <2> \8230, WL < m-1>, and m is the number of word lines in each sector, and if an operation region occupies memory cells corresponding to the first three word lines in an over-erased sector, all the memory cells in WL <0>, WL <1>, and WL <2> in the over-erased sector are included.
In some preferred embodiments, the operating area occupies an equal number of word lines in each over-erased sector.
Specifically, the fact that the number of word lines occupied by the operation regions in each over-erased sector is equal indicates that the number of memory cells included in each over-erased sector in the operation regions is equal, that is, the number of memory cells corresponding to each bit line in each over-erased sector in the operation regions, which need to be subjected to the post-programming operation, is equal, so that it is ensured that the time consumed for the post-programming operation performed on the memory cells corresponding to each over-erased sector in each operation region is similar, and the problem that the time difference consumed by the post-programming operation is too large due to the fact that the number of memory cells included in different over-erased sectors in the operation regions is different, and the efficiency of the whole post-programming operation is affected is avoided.
In some preferred embodiments, the number of operation regions is a positive even number, and the total number of word lines of each over-erased sector can be divided by the total number of word lines, and each operation region occupies the same number of word lines.
Specifically, the total number of word lines per sector in the existing flash memory chip is generally 2 n The positive even number of operation areas can equally divide the memory cells in each over-erased sector, so that the time consumed by the post-programming operation performed on each operation area is similar; for example, when each sector includes 8 word lines, the number of the operation regions may be 2, 4, or 8, and the operation regions occupy the memory cells corresponding to 4, 2, or 1 word line in each over-erased sector; for a general flash memory chip, the number of the operation regions is set to 2 or 4, so that the bit line charge pump can be effectively ensured to have enough driving capability to perform the post-programming operation on the over-erased memory cells.
More specifically, the number of the operation regions is 2, 4, 8, or 16, and the number of the operation regions needs to be adjusted according to the driving capability of the bit line charge pump, that is, the number of the operation regions needs to be determined according to the magnitude of the post-programming current generated when the bit line charge pump performs the post-programming operation on the same number of memory cells connected in series, and the magnitude of the post-programming current needs to be ensured to satisfy the repairing use of the over-erased memory cell; the smaller the driving capability of the bit line charge pump is, the more the number of the corresponding operation areas is, so as to pull up the post-programming current and ensure the smooth post-programming operation.
In some preferred embodiments, the operating regions occupy the same number of word lines in each over-erased sector.
Specifically, since the word line numbers are sorted according to the positions of the word lines in the sectors, the word line numbers occupied by the operating regions in each over-erased sector are the same, which indicates that the positions of the memory cells occupied by each operating region in each over-erased sector are the same, that is, the distances between the corresponding memory cells and the word line charge pump and the bit line charge pump are equal, so as to further ensure that the time consumed by the post-programming operation performed on each operating region is similar, facilitate the rapid selection of the memory cells corresponding to the operating regions, and facilitate the control of the post-programming voltage applied to the entire operating region.
In some preferred embodiments, the step of performing the post-program operation on the operation regions one by one includes:
the post-program operation is performed on the operation regions one by one in the word line arrangement order in the over-erased sector.
Specifically, performing the post-program operation according to the word line arrangement order is beneficial to programming the post-program logic, and ensures that the post-program operation can be smoothly performed so that the post-program operation can cover all over-erased sectors in the whole memory array, thereby completing the over-erase repair of the memory array.
More specifically, taking an example of an over-erased sector split into 4 operating regions based on 8 word lines, the 4 operating regions respectively correspond to memory cells on word lines WL <0> -WL <1>, WL <2> -WL <3>, WL <4> -WL <5>, and WL <6> -WL <7>, and when step S103 is executed, a post-program operation is performed on all memory cells on word lines WL <0> -WL <1>, then on all memory cells on word lines WL <2> -WL <3>, then on all memory cells on word lines WL <4> -WL <5>, and finally on all memory cells on word lines WL <6> -WL <7>, so as to complete the post-program operation of all over-erased sectors in the entire memory array.
In a second aspect, please refer to fig. 2, fig. 2 is an erasing method provided in some embodiments of the present application for performing an erasing process on a target area in a memory array, the erasing method includes the following steps:
s201, erasing the target area;
specifically, the target area is an area formed by a plurality of sectors which need to be emptied of stored data according to actual use requirements in the memory array, the erasing operation is to apply an erasing voltage to the sectors to reduce the threshold voltages of all memory cells in the sectors so as to clear all stored data, and since the erasing operation is performed by taking the sectors as minimum units, the threshold voltages of part of the memory cells are easily erased too low, so that an over-erasing phenomenon occurs.
More specifically, before the target area is erased, all data in the target area needs to be read, which generally includes three cases: if the data in the target area are all 1, indicating that all the memory cells in the target area are not written with data, and only performing post-programming operation on the target area to enable all the memory cells to be located in a normal range of the threshold voltage; if the data in the target area are all 0, indicating that all the storage units in the target area are written with data, and starting to execute step S201; if the data in the target area has 0 and 1, it indicates that only part of the memory cells in the target area have data written therein, so that the target area needs to be pre-programmed to make all the memory cells in the target area have data written therein, and then step S201 is performed.
S202, acquiring an over-erased sector with an over-erased storage unit in a target area;
s203, dividing all over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
and S204, performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
Specifically, the threshold voltages of all the memory cells in the target area may not be adjusted to be within the normal range in one erase and post-program cycle during the whole erase process of the target area, and therefore, the threshold voltages of all the memory cells in the whole target area can be adjusted to be within the normal range by performing multiple erase and post-program operations with different voltages.
According to the erasing method, after the target area is erased, the over-erased sector in the target area is divided into the multiple operation areas to perform the post-programming operation, each operation area corresponds to the area where each over-erased sector occupies the corresponding word line, the post-programming operation which is originally performed on the whole over-erased sector for one time is divided into multiple independent post-programming operations aiming at the memory units on different word lines, the current which is correspondingly generated on each memory unit by the post-programming voltage applied by the bit line is pulled up, namely the bit line charge pump which provides the post-programming voltage in the bit line is ensured to have enough driving capacity relative to the memory units, so that the programming capacity of the post-programming operation is improved, the post-programming operation on the over-erased memory units can be smoothly performed, the over-erased memory units can be smoothly repaired, and the whole erasing process is smoothly completed.
In a third aspect, referring to fig. 3, fig. 3 is a post-programming apparatus for performing post-programming processing on an over-erased sector having over-erased memory cells in a memory array according to an embodiment of the present disclosure, where the post-programming apparatus includes:
an obtaining module 201, configured to obtain an over-erased sector;
a dividing module 202, configured to divide all over-erased sectors into multiple operation areas according to word line distribution conditions in the sectors, so that each operation area includes memory cells corresponding to a plurality of word lines in each over-erased sector;
and the post-programming module 203 is used for performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
In the post-programming apparatus of the embodiment of the present application, the dividing module 202 is utilized to divide the over-erased sectors in the memory array into a plurality of operation areas for performing the post-programming operation, each operation area corresponds to each over-erased sector and occupies a corresponding area of a plurality of word lines, and the post-programming module 203 is utilized to divide the post-programming operation originally performed on the entire over-erased sector for one time into multiple independent post-programming operations for memory cells on different word lines, so that the current generated on each memory cell corresponding to the post-programming voltage applied by the bit line is pulled up, that is, it is ensured that a bit line charge pump providing the post-programming voltage in the bit line has sufficient driving capability relative to the memory cells, thereby improving the programming capability of the post-programming operation, and ensuring that the post-programming operation can be performed on the over-erased memory cells smoothly, so as to repair the over-erased memory cells smoothly.
In some preferred embodiments, a post-programming apparatus of the embodiments of the present application is preferably configured to perform a post-programming method provided in the first aspect.
In a fourth aspect, please refer to fig. 4, where fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.
In a fifth aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, embodiments of the present application provide a post-programming method, an erasing apparatus, an electronic device, and a storage medium, where the post-programming method divides an over-erased sector in a storage array into a plurality of operation regions for performing post-programming operation, each operation region corresponds to a region where each over-erased sector occupies corresponding to a plurality of word lines, and distinguishes the post-programming operation originally performed on the entire over-erased sector for a plurality of times of independent post-programming operations for storage units on different word lines, so that a current generated on each storage unit corresponding to a post-programming voltage applied to a bit line is pulled up, that is, a bit line charge pump providing the post-programming voltage in the bit line has sufficient driving capability with respect to the storage units, thereby improving the programming capability of the post-programming operation without changing the driving capability of the bit line charge pump, and ensuring that the post-programming operation can be performed on the over-erased storage units smoothly, so as to repair the over-erased storage units smoothly.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A post-programming method for performing a post-programming process on an over-erased sector of a memory array having over-erased memory cells, the post-programming method comprising the steps of:
acquiring the over-erased sector;
dividing all the over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
and performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
2. A method of post-programming according to claim 1, wherein the operating areas occupy consecutive numbers of word lines in each of the over-erased sectors.
3. A method of post-programming according to claim 1, wherein said operating area occupies an equal number of word lines in each of said over-erased sectors.
4. The method of claim 3, wherein the number of said operation regions is a positive even number, and the total number of word lines of each said over-erased sector is divisible by the total number of word lines, and the number of word lines occupied by each said operation region is equal.
5. A method of post-programming according to claim 3, wherein the word lines occupied by the operating area in each of the over-erased sectors are numbered identically.
6. A method of post-programming according to claim 3, wherein said step of performing post-programming operations on said operation regions one by one comprises:
and performing post-programming operation on the operation areas one by one according to the word line arrangement sequence in the over-erased sector.
7. An erasing method for performing an erasing process on a target area in a memory array, the erasing method comprising the steps of:
carrying out erasing operation on the target area;
acquiring an over-erased sector with an over-erased storage unit in the target area;
dividing all the over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, and enabling each operation area to comprise storage units corresponding to a plurality of word lines in each over-erased sector;
and performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
8. A post-program apparatus for performing a post-program process on an over-erased sector of a memory array having over-erased memory cells, the post-program apparatus comprising:
an obtaining module, configured to obtain the over-erased sector;
the dividing module is used for dividing all the over-erased sectors into a plurality of operation areas according to the distribution condition of word lines in the sectors, so that each operation area comprises storage units corresponding to a plurality of word lines in each over-erased sector;
and the post-programming module is used for performing post-programming operation on the operation areas one by one until the post-programming operation of the whole storage array is completed.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 6.
10. A storage medium on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1-6.
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