CN115458020A - Method for reducing over-erasing probability of memory chip, electronic equipment and storage medium - Google Patents
Method for reducing over-erasing probability of memory chip, electronic equipment and storage medium Download PDFInfo
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- CN115458020A CN115458020A CN202211220501.1A CN202211220501A CN115458020A CN 115458020 A CN115458020 A CN 115458020A CN 202211220501 A CN202211220501 A CN 202211220501A CN 115458020 A CN115458020 A CN 115458020A
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- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
Abstract
The application relates to the technical field of memory chips, and particularly provides a method for reducing the over-erasing probability of a memory chip, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring an easily-erasable storage unit group in the storage chip, wherein the easily-erasable storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip; replacing the group of easy-to-erase storage units with a redundant unit; the method comprises the steps of firstly obtaining the easily-erased storage unit group in the storage chip, and then replacing the easily-erased storage unit group by the redundant unit so as to replace the most easily-erased storage unit in the storage array, thereby reducing the number of the easily-erased storage units in the storage array as much as possible and further effectively reducing the probability of over-erasing phenomenon of the storage chip.
Description
Technical Field
The present application relates to the field of memory chip technologies, and in particular, to a method for reducing an over-erase probability of a memory chip, an electronic device, and a storage medium.
Background
When the NOR Flash memory chip performs an erase operation, threshold voltages of all memory cells to be erased need to be erased to the left of a read voltage, and if there are memory cells that are easy to erase in the NOR Flash memory chip, the memory cells that are easy to erase are easy to leak after being erased to the left of the read voltage, thereby causing an over-erase phenomenon.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The present application is directed to a method, an electronic device, and a storage medium for reducing the probability of over-erasing of a memory chip, so as to effectively reduce the probability of over-erasing of the memory chip.
In a first aspect, the present application provides a method for reducing probability of over-erasing a memory chip, for reducing probability of over-erasing the memory chip, including the following steps:
acquiring an easily-erasable storage unit group in the storage chip, wherein the easily-erasable storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip;
the group of easily erasable memory cells is replaced with a redundant cell.
According to the method for reducing the over-erasing probability of the memory chip, the easily-erased memory unit group in the memory chip is obtained firstly, and then the easily-erased memory unit group is replaced by the redundant unit so as to replace the most easily-erased memory unit in the memory array, so that the number of easily-erased memory units in the memory array is reduced as much as possible, and the over-erasing probability of the memory chip is effectively reduced.
Optionally, the step of obtaining the easily erasable memory cell group in the memory chip, where the easily erasable memory cell group is a plurality of memory cells with the lowest threshold voltage in the memory chip, further includes, before the step of obtaining the easily erasable memory cell group in the memory chip, a step of:
and carrying out redundancy replacement on the memory chip.
According to the technical scheme, before the easily-erased storage unit group in the storage chip is obtained, the storage chip is subjected to redundancy replacement to replace the storage unit which cannot be erased or damaged in the storage chip, so that the situation that the easily-erased storage unit group in the storage chip cannot be obtained due to the fact that the storage unit which cannot be erased or damaged exists in the storage chip is avoided.
Optionally, the step of replacing the easily erasable memory cell group with a redundant cell includes:
and replacing the easily-erased storage unit group by using the redundant units left after the redundant replacement.
Optionally, the step of obtaining the easily erasable memory cell group in the memory chip includes:
and erasing the memory chip based on a preset variable first voltage and/or a preset variable first pulse signal to obtain the number of first bit lines and the number of second bit lines, so that the number of the first bit lines is equal to the number of the second bit lines, the first bit lines are bit lines where the easy-to-erase memory cell groups are located, and the second bit lines are bit lines where the residual redundant cells after the redundancy replacement are located.
Optionally, the step of obtaining the easily erasable memory cell group in the memory chip includes:
and simultaneously erasing the memory chip and the redundant units left after the redundancy replacement based on a first voltage with preset change and/or a first pulse signal with preset change so as to obtain the number of first bit lines and the number of third bit lines, wherein the number of the first bit lines is equal to the number of the third bit lines, the first bit lines are bit lines where the memory unit group easy to erase is located, the third bit lines are bit lines on which all the redundant units are valid residual redundant units, and the valid residual redundant units are the redundant units which are not erased in the residual redundant units.
Since the third bit line is a bit line on which all the redundant cells are the non-erased redundant cells, the technical scheme can ensure that all the memory cells which are most easily erased in the memory array are replaced by the non-erased redundant cells in the redundant array.
Optionally, the step of replacing the easily erasable memory cell group with a redundant cell includes:
and replacing the first bit line with the third bit line.
Optionally, the step of obtaining the easily erasable memory cell group in the memory chip includes:
and carrying out erasing operation on the memory chip based on a preset first voltage and/or a preset first pulse signal so as to obtain the easily-erased memory unit group.
Optionally, the first voltage is smaller than a second voltage, and the second voltage is an erase voltage used when the memory chip performs an erase operation.
In a second aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer-readable instructions, and the computer-readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a third aspect, the present application also provides a storage medium having a computer program stored thereon, where the computer program runs the steps of the method as provided in the first aspect when executed by a processor.
In view of the above, according to the method for reducing the over-erase probability of the memory chip, the electronic device and the storage medium provided by the application, the easily-erasable memory unit group in the memory chip is obtained first, and then the redundant unit is used to replace the easily-erasable memory unit group so as to replace the memory unit which is most easily erased in the memory array, thereby reducing the number of the easily-erased memory units in the memory array as much as possible, and further effectively reducing the over-erase probability of the memory chip.
Additional features and advantages of the present application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
FIG. 1 is a distribution diagram of threshold voltages of memory cells including a normally programmed state and a normally erased state.
FIG. 2 is a distribution diagram of threshold voltages of memory cells erased from a normal programmed state to an over-erase condition.
Fig. 3 is a flowchart of a method for reducing over-erase probability of a memory chip according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 101. a processor; 102. a memory; 103. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
The NOR Flash memory chip comprises a memory array and a redundancy array, wherein the memory array comprises a plurality of memory cells, and the redundancy array comprises a plurality of redundancy units. As shown in fig. 1, fig. 1 is a distribution diagram of threshold voltages of memory cells including a normal Program (Program) state and a normal Erase (Erase) state, when a NOR Flash memory chip performs an Erase operation, it is necessary to Erase the threshold voltages (Vth) of all memory cells to be erased to the left of a read Voltage (VRF), as shown in fig. 2, fig. 2 is a distribution diagram of threshold voltages of memory cells erased from the normal Program state to when an over-Erase phenomenon occurs, if there are memory cells that are easily erased in the memory cells to be erased of the NOR Flash memory chip, the memory cells that are easily erased are easily over-erased after all the memory cells are completely erased, so that leakage occurs, that is, the over-Erase phenomenon occurs.
As shown in fig. 3, in a first aspect, the present application provides a method for reducing probability of over-erasing a memory chip, for reducing probability of over-erasing the memory chip, including the following steps:
s1, obtaining an easily-erased storage unit group in a storage chip, wherein the easily-erased storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip;
and S2, replacing the easily-erased storage unit group by using the redundant unit.
The reading voltage is used when the memory chip performs reading operation, and if the reading voltage is higher than the threshold voltage of the memory unit, the data obtained by reading the memory unit is 1; if the read voltage is lower than the threshold voltage of the memory cell, the data obtained by reading the memory cell is 0, so that whether the corresponding memory cell completes the erasing/programming operation can be judged according to the read data. The memory unit of step S1 is located in a memory array of a memory chip, and the principle of step S1 is as follows: the memory array comprises memory cells which are easy to erase and memory cells which are difficult to erase, and the memory cells which are easy to erase (with relatively low threshold voltage) can be erased successfully more quickly in a complete erasing operation process, so that after a certain erasing voltage is applied to the memory array in the memory chip to perform erasing operation, whether the threshold voltage of the memory cells is low is judged by reading whether data in the memory cells is 1, and a plurality of memory cells with the lowest threshold voltage in the memory array are the memory cells which are easy to erase, so that the group of the memory cells which are easy to erase in the memory chip can be obtained. It should be understood that, in order to avoid that the memory cell is judged as a memory cell with a lower threshold voltage because the memory cell has the memory data of 1, the memory chip needs to be programmed in a full slice before step S1 is performed, so that the memory data of all the memory cells of the memory chip are 0.
And S2, replacing the physical addresses of the memory units in the easily-erased memory unit group by the physical addresses of the redundant units in the redundant array so as to replace the easily-erased memory unit group by the redundant units. And S2, replacing the memory cells in the easily-erased memory cell group by the redundancy cells in the redundancy array to replace the memory cells which are most easily erased in the memory array, so that the number of the easily-erased memory cells in the memory array is reduced as much as possible, and the probability of over-erasing of the memory chip is effectively reduced. It should be understood that the replacement process of step S2 is similar to the process of redundancy replacement of the prior art, with the difference that: the replaced object of the present application is an easy-to-erase memory cell group, the easy-to-erase memory cell group is not an unusable memory cell, and the redundantly replaced object of the prior art is an unusable (e.g. unusable or damaged) memory cell.
According to the method for reducing the over-erasing probability of the memory chip, the easily-erased memory unit group in the memory chip is obtained firstly, and then the easily-erased memory unit group is replaced by the redundant unit so as to replace the most easily-erased memory unit in the memory array, so that the number of easily-erased memory units in the memory array is reduced as much as possible, and the over-erasing probability of the memory chip is effectively reduced. In addition, because the threshold voltage of the memory cell which is easy to erase is different from the threshold voltage of the memory cell which is not easy to erase relative to the memory cell which is easy to erase, the consistency of the threshold voltage of each memory cell can be improved by replacing the easy-to-erase memory cell group by the redundant cell, so that the repair time required when the over-erase phenomenon occurs is effectively reduced, and the erase efficiency of the memory chip is effectively improved.
In order to improve the convenience of redundancy replacement, the bit line where the redundant cell is located is generally used to replace the bit line where the memory cell that cannot be erased or damaged is located, and since the replacement process of the present application is similar to the redundancy replacement process of the prior art, in order to improve the convenience of replacing the group of easily erasable memory cells with the redundant cell, in some preferred embodiments, step S2 includes:
and S21, replacing the bit line where the easy-to-erase storage unit group is located by the bit line where the redundant unit is located.
The embodiment can effectively improve the convenience of replacing the easily-erased memory cell group by the redundancy cell, and when a plurality of memory cells with the lowest threshold voltage exist on the same word line, the embodiment can replace all the memory cells with the lowest threshold voltage on the word line into the redundancy cell at one time.
In some preferred embodiments, after the easily erasable memory cell group is obtained, the redundant cells in the redundant array are erased based on the same erase condition to obtain the un-erased redundant cells in the redundant array, and step S2 replaces the easily erasable memory cell group with the un-erased redundant cells in the redundant array to further improve the uniformity of the threshold voltages of the memory cells.
When an easily erasable memory chip set in a memory chip is obtained, if a memory unit that cannot be erased or damaged exists in the memory chip, the memory chip may not perform an erase operation on the memory unit, so that an easily erasable memory unit group in the memory chip cannot be obtained. In order to solve the technical problem, in some embodiments, step S1 is preceded by the steps of:
and S0, performing redundancy replacement on the memory chip.
The specific work flow of the step S0 is as follows: 1. acquiring a storage unit which cannot be erased or damaged in a storage chip; 2. the memory cells that cannot be erased or damaged are replaced with redundant cells. According to the technical scheme, before the easily-erasable storage unit group in the storage chip is obtained, the redundancy replacement is carried out on the storage chip firstly to replace the storage unit which cannot be erased or damaged in the storage chip, so that the situation that the easily-erasable storage unit group in the storage chip cannot be obtained due to the storage unit which cannot be erased or damaged in the storage chip is avoided.
In some embodiments, after completing the redundancy replacement of the memory chip, step S2 includes:
and S21', replacing the easily-erased storage unit group by using the redundant units left after the redundant replacement.
Because the embodiment replaces the easily-erased memory cell group by the redundant cell remaining after the redundancy replacement, the embodiment can effectively avoid the situation that the memory cell which cannot be erased or damaged in the redundant array after the redundancy replacement is replaced to the memory array again. In some preferred embodiments, step S21' may replace the bit line where the group of easy-to-erase memory cells is located with the bit line where the redundant cell remaining after the redundancy replacement is located.
Example 1
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s1, carrying out erasing operation on a memory chip based on a preset first voltage to obtain an easily-erased memory unit group;
and S2, replacing the easily-erased storage unit group by using the redundant unit.
The preset first voltage in step S1 is smaller than a second voltage, and the second voltage is an erase voltage used when the memory chip performs an erase operation. The working principle of the embodiment is as follows: the method comprises the steps that erasing operation is carried out on a storage chip based on a smaller first voltage, and threshold voltages of storage units in the storage chip are obtained, the threshold voltage distribution of the storage units in a storage array is in normal distribution, the storage units which are easy to erase and the storage units which are difficult to erase exist in the storage array, the storage units which are easy to erase (the threshold voltages are relatively lower) can be erased successfully more quickly in a complete erasing operation process, and under the condition that other erasing conditions are the same as the erasing conditions when the storage chip is in a normal state, a plurality of storage units with the lowest threshold voltages are the storage units which are easy to erase in the storage array, so that the group of easy-to-erase storage units in the storage chip can be obtained.
Example 2
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s1, erasing a memory chip based on a preset first pulse signal to obtain an easily-erased memory unit group;
and S2, replacing the easily-erased storage unit group by using the redundant unit.
The preset first pulse signal in step S1 is shorter than the second pulse signal, and the second pulse signal is a pulse signal used when the memory chip performs an erase operation. The working principle of the embodiment is as follows: the method comprises the steps of carrying out erasing operation on a storage chip based on a shorter first pulse signal and obtaining threshold voltages of all storage units in the storage chip, wherein the threshold voltage distribution of the storage units in a storage array is in normal distribution, the storage units which are easy to erase and the storage units which are difficult to erase exist in the storage array, in the whole erasing operation process, the storage units which are easy to erase (the threshold voltages are relatively lower) can be erased more quickly and successfully, and under the condition that other erasing conditions are the same as the erasing conditions when the storage chip is in a normal state, a plurality of storage units with the lowest threshold voltages are the storage units which are easy to erase in the storage array, so that the storage unit group which is easy to erase in the storage chip is obtained.
Example 3
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s1, erasing a memory chip based on a preset first voltage and a preset first pulse signal to obtain an easily-erasable memory unit group;
and S2, replacing the easily-erased storage unit group by using the redundant unit.
The preset first voltage in step S1 is smaller than the second voltage, the second voltage is an erasing voltage used when the memory chip performs an erasing operation, the preset first pulse signal is shorter than the second pulse signal, and the second pulse signal is a pulse signal used when the memory chip performs an erasing operation. The working principle of the embodiment is as follows: the memory chip is erased based on a smaller first voltage and a shorter first pulse signal, and as the threshold voltage distribution of the memory cells in the memory array is in normal distribution, the memory cells which are easy to erase and the memory cells which are difficult to erase exist in the memory array, in a complete erasing operation process, the memory cells which are easy to erase (the threshold voltage is relatively lower) can be erased more quickly and successfully, and under the condition that other erasing conditions are the same as the erasing conditions when the memory chip is in a normal state, a plurality of memory cells with the lowest threshold voltages are the memory cells which are easy to erase in the memory array, so that the easy-to-erase memory cell group in the memory chip can be obtained.
Example 4
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, erasing operation is carried out on a memory chip based on a preset and variable first voltage to obtain the number of first bit lines and the number of second bit lines, so that the number of the first bit lines is equal to that of the second bit lines, the first bit lines are bit lines where memory cell groups are easy to erase, and the second bit lines are bit lines where residual redundant cells are located after redundant replacement;
and S2, replacing the first bit line with the second bit line.
The type of the preset change in step S1 may be an incremental type, a decremental type, or a step type, and the type of the preset change is preferably an incremental type. The working principle of the embodiment is as follows: when the other erasing conditions are the same as the erasing conditions of the memory chip in the normal state, the number of the first bit lines obtained by erasing the memory chip based on the first voltages with different magnitudes may be different, so that the number of the first bit lines is equal to the number of the second bit lines by erasing the memory chip based on the first voltages with preset changes. Since the number of the first bit lines is equal to the number of the second bit lines, compared to embodiments 1 to 3, this embodiment can avoid the situation that the first bit lines cannot be completely replaced due to the number of the first bit lines being greater than the number of the second bit lines or the second bit lines are left due to the number of the first bit lines being less than the number of the second bit lines.
Example 5
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, erasing a memory chip based on a first pulse signal with preset change to obtain the number of first bit lines and the number of second bit lines, wherein the number of the first bit lines is equal to that of the second bit lines, the first bit lines are bit lines where memory cell groups are easy to erase, and the second bit lines are bit lines where residual redundant cells are located after redundant replacement;
and S2, replacing the first bit line with the second bit line.
The type of the preset change in step S1 may be an incremental type, a decreasing type, or a step type, and the type of the preset change is preferably an incremental type. The working principle of the embodiment is as follows: when other erasing conditions are the same as the erasing conditions when the memory chip is in a normal state, the number of the first bit lines obtained by erasing the memory chip based on the first pulse signals with different lengths may be different, so that the number of the first bit lines is equal to the number of the second bit lines by erasing the memory chip based on the first pulse signals with preset changes. Since the number of the first bit lines is equal to the number of the second bit lines, compared to embodiments 1 to 3, this embodiment can avoid a situation that the first bit lines cannot be completely replaced due to the number of the first bit lines being greater than the number of the second bit lines or the second bit lines are left due to the number of the first bit lines being less than the number of the second bit lines.
Example 6
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, erasing a memory chip based on a first voltage with preset change and a first pulse signal with preset change to obtain the number of first bit lines and the number of second bit lines, so that the number of the first bit lines is equal to that of the second bit lines, the first bit lines are bit lines where a memory unit group is easy to erase, and the second bit lines are bit lines where residual redundant units are located after redundant replacement;
and S2, replacing the first bit line with the second bit line.
The type of the preset change in step S1 may be an incremental type, a decreasing type, or a step type, and the type of the preset change is preferably an incremental type. The working principle of the embodiment is as follows: when other erasing conditions are the same as the erasing conditions when the memory chip is in a normal state, the number of the first bit lines obtained by erasing the memory chip based on the first voltages with different magnitudes and the first pulse signals with different lengths may be different, so that the number of the first bit lines is equal to the number of the second bit lines by erasing the memory chip based on the first voltages with preset changes and the first pulse signals with preset changes. Since the number of the first bit lines is equal to the number of the second bit lines, compared to embodiments 1 to 3, this embodiment can avoid the situation that the first bit lines cannot be completely replaced due to the number of the first bit lines being greater than the number of the second bit lines or the second bit lines are left due to the number of the first bit lines being less than the number of the second bit lines. In addition, since the embodiment performs the erasing operation on the memory chip based on the first voltage of the preset variation and the first pulse signal of the preset variation, the embodiment can also avoid the situation that the number of the first bit lines is still larger than the number of the second bit lines when the first voltage is changed to the minimum or the first pulse signal is changed to the shortest.
Example 7
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, simultaneously erasing the memory chip and the residual redundant units after redundancy replacement based on a preset changed first voltage to obtain the number of first bit lines and the number of third bit lines, so that the number of the first bit lines is equal to that of the third bit lines, the first bit lines are bit lines where memory unit groups are easy to erase, the third bit lines are bit lines on which all redundant units are valid residual redundant units, and the valid residual redundant units are the residual redundant units which are not erased;
and S2, replacing the first bit line with the third bit line.
The type of the preset change in step S1 may be an incremental type, a decremental type, or a step type, and the type of the preset change is preferably an incremental type. Since the third bit line is a bit line on which all the redundant cells are unerased redundant cells, the embodiment can ensure that all the most easily erased memory cells in the memory array are replaced by the unerased redundant cells in the redundant array, and since the embodiment simultaneously performs the erase operation on the memory chip and the redundant cells remaining after the redundant replacement, after acquiring the number of the first bit lines, it is not necessary to perform the erase operation on the remaining redundant cells to acquire the number of the third bit lines, thereby effectively simplifying the flow of acquiring the number of the first bit lines and the number of the third bit lines.
Example 8
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, simultaneously erasing the memory chip and the redundant units left after redundant replacement based on a first pulse signal with preset change so as to obtain the number of first bit lines and the number of third bit lines, wherein the number of the first bit lines is equal to the number of the third bit lines, the first bit lines are bit lines where the memory unit groups are easy to erase, the third bit lines are bit lines on which all redundant units are valid redundant units, and the valid redundant units are the redundant units which are not erased in the remaining redundant units;
and S2, replacing the first bit line by using the third bit line.
The type of the preset change in step S1 may be an incremental type, a decremental type, or a step type, and the type of the preset change is preferably an incremental type. Since the third bit lines are bit lines on which all redundancy units are not erased, the embodiment can ensure that all the most easily erased memory units in the memory array are replaced by the un-erased redundancy units in the redundancy array, and since the embodiment simultaneously performs the erasing operation on the memory chip and the redundancy units remaining after the redundancy replacement, after acquiring the number of the first bit lines, it is not necessary to perform the erasing operation on the remaining redundancy units to acquire the number of the third bit lines, thereby effectively simplifying the flow of acquiring the number of the first bit lines and the number of the third bit lines.
Example 9
The method for reducing the over-erasing probability of the memory chip comprises the following steps:
s0, performing redundancy replacement on the memory chip;
s1, simultaneously erasing a memory chip and residual redundant units after redundancy replacement based on a first voltage with preset change and a first pulse signal with preset change to obtain the number of first bit lines and the number of third bit lines, so that the number of the first bit lines is equal to that of the third bit lines, the first bit lines are bit lines where a memory unit group is easy to erase, the third bit lines are bit lines on which all redundant units are valid residual redundant units, and the valid residual redundant units are the residual redundant units which are not erased;
and S2, replacing the first bit line with the third bit line.
The type of the preset change in step S1 may be an incremental type, a decremental type, or a step type, and the type of the preset change is preferably an incremental type. Since the third bit line is a bit line on which all the redundant cells are unerased redundant cells, the embodiment can ensure that all the most easily erased memory cells in the memory array are replaced by the unerased redundant cells in the redundant array, and since the embodiment simultaneously performs the erase operation on the memory chip and the redundant cells remaining after the redundant replacement, after acquiring the number of the first bit lines, it is not necessary to perform the erase operation on the remaining redundant cells to acquire the number of the third bit lines, thereby effectively simplifying the flow of acquiring the number of the first bit lines and the number of the third bit lines.
Therefore, according to the method for reducing the over-erasing probability of the memory chip, the easily-erasable memory unit group in the memory chip is obtained first, and then the easily-erasable memory unit group is replaced by the redundant unit so as to replace the most easily-erased memory unit in the memory array, so that the number of the easily-erased memory units in the memory array is reduced as much as possible, and the over-erasing probability of the memory chip is effectively reduced.
In a second aspect, please refer to fig. 4, where fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device including: a processor 101 and a memory 102, the processor 101 and the memory 102 being interconnected and in communication with each other via a communication bus 103 and/or other form of connection mechanism (not shown), the memory 102 storing a computer program executable by the processor 101, the computer program being executable by the processor 101 to, when executed by a computing device, perform the method in any of the alternative implementations of the embodiments to implement the following functions: acquiring an easily-erasable storage unit group in a storage chip, wherein the easily-erasable storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip; the group of easily erasable memory cells is replaced with a redundant cell.
In a third aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program executes the method in any optional implementation manner of the embodiments to implement the following functions: acquiring an easily-erasable storage unit group in a storage chip, wherein the easily-erasable storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip; the group of easily erasable memory cells is replaced with a redundant cell. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In view of the above, according to the method for reducing the over-erase probability of the memory chip, the electronic device and the storage medium provided by the application, the easily-erasable memory unit group in the memory chip is obtained first, and then the easily-erasable memory unit group is replaced by the redundant unit to replace the most easily-erased memory unit in the memory array, so that the number of easily-erased memory units in the memory array is reduced as much as possible, and the probability of the over-erase phenomenon of the memory chip is further effectively reduced.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, for example, the division of the above-described units is only a logical functional division, and other division manners may be available in actual implementation, and for example, a plurality of units or components may be combined or integrated into another robot, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may ascend to one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. The method for reducing the probability of over-erasing of the memory chip is used for reducing the probability of over-erasing of the memory chip, and is characterized by comprising the following steps of:
acquiring an easily-erasable storage unit group in the storage chip, wherein the easily-erasable storage unit group is a plurality of storage units with the lowest threshold voltage in the storage chip;
and replacing the group of easy-to-erase storage units by a redundant unit.
2. The method according to claim 1, wherein the step of obtaining the easily erasable memory cell group in the memory chip, the easily erasable memory cell group being the memory cells with the lowest threshold voltage in the memory chip, further comprises the steps of:
and carrying out redundancy replacement on the memory chip.
3. The method of claim 2, wherein the step of replacing the group of easy-to-erase memory cells with redundant cells comprises:
and replacing the easily-erased storage unit group by using the residual redundant units after the redundant replacement.
4. The method according to claim 2, wherein the step of obtaining the group of easily erasable memory cells in the memory chip comprises:
and erasing the memory chip based on a preset variable first voltage and/or a preset variable first pulse signal to obtain the number of first bit lines and the number of second bit lines, so that the number of the first bit lines is equal to that of the second bit lines, the first bit lines are bit lines where the easily-erased memory cell groups are located, and the second bit lines are bit lines where the residual redundant cells after redundancy replacement are located.
5. The method according to claim 2, wherein the step of obtaining the group of easily erasable memory cells in the memory chip comprises:
and simultaneously erasing the memory chip and the residual redundant units after the redundancy replacement based on a first voltage with preset change and/or a first pulse signal with preset change so as to obtain the number of first bit lines and the number of third bit lines, wherein the number of the first bit lines is equal to the number of the third bit lines, the first bit lines are bit lines where the easy-to-erase memory unit group is located, the third bit lines are bit lines on which all the redundant units are valid residual redundant units, and the valid residual redundant units are the redundant units which are not erased in the residual redundant units.
6. The method of claim 5, wherein the step of replacing the group of easy-to-erase memory cells with redundant cells comprises:
replacing the first bit line with the third bit line.
7. The method for reducing the over-erase probability of the memory chip according to claim 1, wherein the step of obtaining the easily-erasable memory cell group in the memory chip comprises:
and carrying out erasing operation on the memory chip based on a preset first voltage and/or a preset first pulse signal so as to obtain the easily-erased memory unit group.
8. The method of claim 7, wherein the first voltage is less than a second voltage, and the second voltage is an erase voltage used when the memory chip is erased.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 8.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-8.
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