CN113409863A - Method and device for reducing erasing time, electronic equipment and storage medium - Google Patents
Method and device for reducing erasing time, electronic equipment and storage medium Download PDFInfo
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- CN113409863A CN113409863A CN202110719874.2A CN202110719874A CN113409863A CN 113409863 A CN113409863 A CN 113409863A CN 202110719874 A CN202110719874 A CN 202110719874A CN 113409863 A CN113409863 A CN 113409863A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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Abstract
The invention discloses a method and a device for reducing erasing time, electronic equipment and a storage medium, wherein the method comprises the following steps: s1, pre-programming the storage units in the sectors; s2, erasing the memory cells in the sector; s3, verifying the erased sectors and neglecting all sectors successfully erased in the storage units; s4, repeating the steps S2-S3 until the memory cells of all the sectors are erased; s5, performing over-erasure detection and repair on the storage units in all the sectors; the method can erase the sector in a periodic cycle, mark and ignore the sector which is erased, gradually ignore the sector which is erased to execute the erasing operation in a targeted way, can avoid the invalid operation of the erased sector, effectively avoid over-erasing the sector which is erased, reduce the repair time of the over-erasing and improve the erasing efficiency of the NOR Flash chip.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a method and an apparatus for reducing erase time, an electronic device, and a storage medium.
Background
The NOR Flash supports Erase operation commands such as Chip Erase (Chip Erase), Block Erase (Block Erase), and Sector Erase (Sector Erase), in which 1 Block with a capacity of 64KB is equivalent to 16 sectors with a capacity of 4 KB. After a sector in a block address undergoes multiple erase program cycles (e.g., 100K), the threshold voltage (Vth) of the memory cells in the sector shifts to the right, in that the erase speed slows down as the number of erase program cycles increases.
The conventional NOR Flash erasing method comprises the following steps: and (3) erasing the blocks after pre-programming, performing erase verification on the memory units in the address to be erased after the blocks are erased (the erase verification is an operation for confirming whether the memory units are erased or not), repeating the erase operation if the memory units do not pass the erase verification, repeating the operation until the memory units pass the erase verification, and performing erased check and repair on the erased area.
However, if one or more sectors that have undergone multiple erase programming cycles are included in a block address, threshold voltage distributions of memory cells in different sectors in the block are not uniform (the sectors that have undergone multiple erase programming cycles are more difficult to erase, and more erase pulses need to be input), in order to take care of the sectors that have undergone multiple erase programming cycles, more erase pulses need to be input into the whole block, which is prone to cause over-erase (over-erase) because too many erase pulses are input into sectors that are in the same block address and have not undergone multiple erase programming cycles, and thus the over-erase repair time is greatly increased, and the overall erase operation time is greatly increased.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, an electronic device, and a storage medium for reducing an erase time, so as to prevent an erased sector from being continuously erased for multiple times, thereby reducing an over-erased memory cell, so as to reduce an over-erased repair time and an erase operation time.
In a first aspect, an embodiment of the present application provides a method for reducing an erase time, where the method is used for a NOR Flash erase operation, and the method includes the following steps:
s1, pre-programming the storage units in the sectors;
s2, erasing the memory cells in the sector;
s3, verifying the erased sectors and neglecting all sectors successfully erased in the storage units;
s4, repeating the steps S2-S3 until the memory cells of all the sectors are erased;
and S5, performing over-erasure detection and repair on the storage units in all the sectors.
The method for reducing the erasing time of the embodiment of the application executes the steps S2-S3 in a periodic cycle manner, gradually ignores the sectors which are subjected to the erasing operation to execute the erasing operation in a targeted manner, and ignores the sectors which are subjected to the erasing operation, so that invalid operations can be reduced, the resource utilization rate is improved, meanwhile, the sectors which are subjected to the erasing operation are effectively prevented from being over-erased, and the over-erased repair time is indirectly reduced, namely the overall erasing time is reduced.
The method for reducing erasing time further includes, before executing step S1, the steps of:
s0, checking whether the memory cells in each sector are in an erasing state, and ignoring the sectors in which the memory cells are in the erasing state.
The method for reducing erasing time further includes marking the sectors of the memory cells in the erased state in step S0.
The method for reducing the erasing time further includes, in step S3, marking the sectors that are completely erased according to the number of times of the circular erasing so as to distinguish the erasing speed of the corresponding sectors.
In the method for reducing erasing time, the determination condition of "until all the memory cells of all the sectors are erased" in step S4 is to determine whether all the sectors are in an erased state or to determine whether all the sectors are ignored.
The method for reducing the erasing time is described, wherein the pre-programming process in step S1 is to program all "0" for the memory cells in all sectors to be erased.
The method for reducing the erasing time includes the following sub-steps in step S5:
s51, checking whether an over-erased storage unit exists;
s52, repairing the over-erased storage unit;
s53, repeating the steps S51-S52 until the over-erased memory cell is not checked.
In a second aspect, an embodiment of the present application further provides an apparatus for reducing an erase time, which is used for a NOR Flash erase operation, and includes:
the pre-programming module is used for pre-programming the storage units in the sector to be erased;
the erasing module is used for erasing the memory unit;
the verifying module is used for verifying whether all the storage units in the sector are successfully erased;
the mark neglecting module is used for marking and neglecting all sectors successfully erased by the memory units;
the over-erasure detection and repair module is used for detecting and repairing over-erased memory cells;
the erasing module is used for erasing the memory units which are pre-programmed by the pre-programming module, the verification module and the mark neglecting module are matched to circularly erase all the sectors in which the memory units are not successfully erased to the erasing module again until the memory units of all the sectors are completely erased, and the over-erasing detection and repair module can circularly perform over-erasing detection and repair on all the memory units which are completely erased until all the over-erased memory units are completely repaired.
According to the device for reducing the erasing time, the all 0 programming is carried out on the storage unit in the sector of the target object to be erased through the pre-programming module, then the sector erasing is carried out through the erasing module periodically and circularly, the verification module is matched with the mark ignoring module to carry out verification, marking and ignoring on the sector which is erased, the sector which is erased is gradually ignored to carry out the erasing operation pertinently, the invalid operation on the erased sector can be avoided, the over erasing on the sector which is erased is effectively avoided, the repairing time of the over erasing is reduced, the erasing efficiency of the NOR Flash chip is improved, the over erasing detection and repairing of the storage unit are finished through the over-erasing detection repairing module, and the normal use of the storage unit after the erasing is ensured.
In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.
In a fourth aspect, embodiments of the present application further provide a storage medium, on which a computer program is stored, where the computer program runs the steps in the method provided in the first aspect when executed by a processor.
As can be seen from the above, the method, the apparatus, the electronic device, and the storage medium for reducing the erasing time provided in the embodiments of the present application perform sector erasing through periodic cycle, mark and ignore sectors that have been erased, gradually ignore sectors that have been erased to perform the erasing operation in a targeted manner, which can avoid an invalid operation on erased sectors, effectively avoid over-erasing the sectors that have been erased, reduce the repair time of over-erasing, and improve the erasing efficiency of the NOR Flash chip.
Drawings
Fig. 1 is a flowchart of a method for reducing an erase time according to an embodiment of the present disclosure.
Fig. 2 is a logic diagram of a method for reducing an erase time according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of an apparatus for reducing an erase time according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1-2, in a first aspect, fig. 1-2 illustrate a method for reducing erase time in some embodiments of the present application for NOR Flash erase operations, the method comprising:
s1, pre-programming the storage units in the sectors;
specifically, the target to be erased is subjected to full programming treatment, so that the situation that the local storage units in the sector are in a non-programming state and excessive over-erased storage units are generated during erasing is avoided, the overall order of the erasing process can be ensured, and meanwhile, the subsequent verification is facilitated.
S2, erasing the memory cells in the sector;
specifically, the erase operation of the memory cell can be achieved by applying an erase pulse to the memory cell that exceeds its threshold voltage.
S3, verifying the erased sectors and neglecting all sectors successfully erased in the storage units;
specifically, since the partial sector passes through multiple erase programming cycles, the memory cells in the partial sector after a single erase complete the erase operation, and the partial sector also contains the memory cells that have not yet completed the erase operation, in this step, the scan detects whether all the memory cells in the sector that has undergone the erase operation in the previous step S2 successfully perform the erase process, i.e., detects whether all the memory cell data in the corresponding sector are "1", if all the data are "1", it indicates that the sector has successfully completed the erase, and excludes the sector in the cycle by ignoring the sector, and the remaining sectors that have not yet completed the erase, i.e., still have unsuccessfully erased memory cells.
S4, repeating the steps S2-S3 until the memory cells of all the sectors are erased;
specifically, after step S3 is executed, sectors that have been erased are omitted, the remaining sectors that have not been erased are cycled to step S2 for re-erasing operation, then sector verification is performed again through step S3, sectors that have been erased are further omitted, and steps S2-S3 are cycled periodically until all sectors are sectors that have been erased after step S3 is verified, so as to ensure that all memory cells are completely erased.
And S5, performing over-erasure detection and repair on the storage units in all the sectors.
Specifically, since the erase operation in the embodiment of the present application uses a sector as an operation unit, the over-erased memory cells may still appear in a single sector, and therefore, it is necessary to perform over-erase detection and repair on all the memory cells participating in the erase operation, so as to avoid that the memory cells are in an over-erased state and cannot be used normally.
The method for reducing the erasing time of the embodiment of the application executes the steps S2-S3 in a periodic cycle manner, gradually ignores the sectors which are subjected to the erasing operation to execute the erasing operation in a targeted manner, and ignores the sectors which are subjected to the erasing operation, so that invalid operations can be reduced, the resource utilization rate is improved, meanwhile, the sectors which are subjected to the erasing operation are effectively prevented from being over-erased, and the over-erased repair time is indirectly reduced, namely the overall erasing time is reduced.
In addition, the method for reducing the erasing time in the embodiment of the present application is generally used for full Chip Erase (Chip Erase) and Block Erase (Block Erase), wherein a full Chip includes a plurality of blocks, and a Block includes a plurality of sectors, and the sectors in the embodiment of the present application are used as an operation unit for distinguishing whether erasing is completed or not, so that the method is suitable for Chip Erase and Block Erase; the sector comprises a plurality of storage units, the erasing condition of the storage unit in the erasing object can be effectively reflected by taking the sector as a distinguishing unit, and the verification efficiency of the step S3 in the erasing process is improved.
In some preferred embodiments, before executing step S1, the method further includes the following steps:
s0, checking whether the memory cells in each sector are in an erasing state, and ignoring the sectors in which the memory cells are in the erasing state.
Specifically, for some block addresses including sectors that are not programmed and still remain erased (i.e. all memory cells included in the sectors are erased, i.e. all memory cell data in the sectors are "1") and sectors that are programmed, in order to improve the uniformity of the distribution of the memory cells, a conventional block erase method is to pre-program an entire block of addresses, all of which are programmed, and then perform an erase operation on all the memory cells; however, sectors that are actually already erased are not necessary to be pre-programmed and re-erased because they are themselves already erased, erasing this portion of the sector only wastes programming, erasing time and resources; therefore, step S0 is designed in this embodiment of the application, before the pre-programming of step S1, the object to be erased is scanned to check whether sectors in a fully erased state (including memory cells that have not been programmed yet and have not been programmed again by performing an over-erase operation before the program operation) are included, and then the fully erased sectors are ignored, so that the sectors do not enter the operations of steps S1 to S5, thereby avoiding the time and resources for programming, erasing, over-erase detection and repair of the sectors, effectively increasing the total erase time of the chip, and saving resources.
In some preferred embodiments, step S0 further includes marking sectors where all the cells in the memory are in the erased state.
Specifically, the completely erased sectors are marked in the erased state by means of the mark, and it is favorable for the mark to determine whether the sector enters step S1, so as to clearly distinguish between the ignored sectors and the non-ignored sectors, such as marking the sectors in the erased state as erase _0, i.e. indicating that the sectors are completely erased at the time of step S0, and it is not necessary to enter steps S1-S5 for the erase operation.
More specifically, the marking process can also mark that the sector does not participate in the erasing operation, and can reflect the use state of the local storage unit of the chip, for example, reflect some sectors which are never programmed from beginning to end, and the reading, writing and erasing capabilities of the sector are better than those of other sectors, so that the subsequent comprehensive development and use are facilitated; in addition, the flag and the historical use case such as the number of times of erasing participating in step S2 may be combined to calculate the total number of times of erasing of the flag ignoring sector, and the like.
In some preferred embodiments, in step S3, the sectors whose storage units are all successfully erased are marked by a marking method, the sectors are marked as successfully erased states, the sectors marked as successfully erased states are ignored, and the unmarked sectors are performed with the erasing operation of step S2 again, so that the sectors that are completely erased can be sequentially and definitely screened out step by step, the range of the erased objects is gradually reduced, the target object can be ensured to complete the erasing successfully, meanwhile, the invalid operation on the sectors that are completely erased is reduced, and the excessive over-erased storage units generated in the sectors that are completely erased are also avoided, thereby effectively reducing the over-erase repair time.
In some preferred embodiments, step S3 further includes marking the sectors that have been erased according to the number of times of erasing in cycles to distinguish the erasing speed of the corresponding sectors.
Specifically, the sector marked as erased does not participate in the erase operation of step S2 again, but the embodiment of the present application can also record the number of times that the sector participates in the erase operation of step S2 by marking, so as to reflect the erase difficulty of the most difficult memory cells in the sector and reflect the number of times that these memory cells are programmed; the erasing difficulty and distribution of the corresponding sectors in the block can be effectively distinguished through the marking data, and the using condition of the chip can be reflected in a digital mode; if the sector in which erasing is completed in the cycle is marked as erase _ n, where n is the number of times corresponding to entering the cycle erasing, that is, the sector in which erasing is completed by executing steps S2-S3 for the first time is marked as erase _1, therefore, the number of times of erasing corresponding to successful erasing in the current erasing operation can be reflected by the mark.
More specifically, data erasing can be performed according to the marking times, for example, when the subsequent storage unit is erased, the sector with the smaller marking times can be erased first, so as to balance the use frequency of the sector; the sectors with similar mark times can be erased, and because the threshold voltages required by the sectors during erasing are similar, the generated over-erased storage unit is smaller, and the overall erasing efficiency is effectively improved. In some preferred embodiments, the determination condition of "until all the sectors' storage units are erased" in step S4 is to determine whether all the sectors are in an erased state or to determine whether all the sectors are ignored.
Specifically, when the determination condition of "until all the memory cells of all the sectors are erased" in step S4 is to determine whether all the sectors are in the erased state, each time step S4 is executed, all the memory cells in all the sectors need to be scanned and checked, and step S5 is not executed until all the write data of all the memory cells are erased; this way of checking can effectively ensure that the data of the memory cells are all erased.
In some preferred embodiments, the judgment condition of "until all the sectors of the memory cells are erased" in step S4 in this embodiment is to judge whether all the sectors are ignored. Specifically, step S3 is executed in a loop to gradually skip erased sectors in the target object, and when all sectors are skipped, it indicates that there are no unerased sectors, in this determination manner, step S4 is executed by the skipping operation of step S3, and there is no need to scan and check the data of the storage unit again; therefore, the determination method is more efficient than another determination condition.
In some preferred embodiments, the pre-programming process in step S1 is to program all "0" for the memory cells in all sectors to be erased.
Specifically, the data of the memory cell in the NOR Flash in the erase state is 1, and the data of the program state is 0, so that the memory cell of the target object to be erased in the chip is programmed with all '0', the distribution consistency of the memory cells is ensured, and excessive over-erased memory cells are prevented from being generated in the erase process.
In some preferred embodiments, step S5 includes the following sub-steps:
s51, checking whether an over-erased storage unit exists;
s52, repairing the over-erased storage unit;
s53, repeating the steps S51-S52 until the over-erased memory cell is not checked.
Specifically, the repair of the over-erased storage units is gradually completed through periodic cycle detection, so that the normal use of the erased storage units in the target object can be effectively ensured after the erasing.
According to the method for reducing the erasing time, the sectors are erased in a periodic cycle mode, the sectors which are erased are marked and ignored, the sectors which are erased are gradually ignored to execute the erasing operation in a targeted mode, the invalid operation on the erased sectors can be omitted, the sectors which are erased are effectively prevented from being over-erased, the repairing time of the over-erasure is shortened, and the erasing efficiency of a NOR Flash chip is improved.
In a second aspect, please refer to fig. 3, fig. 3 is a block diagram of an apparatus for reducing an erase time in some embodiments of the present application, for a NOR Flash erase operation, including:
the pre-programming module is used for pre-programming the storage units in the sector to be erased;
the erasing module is used for erasing the memory unit;
the verifying module is used for verifying whether all the storage units in the sector are successfully erased;
the mark neglecting module is used for marking and neglecting all sectors successfully erased by the memory units;
the over-erasure detection and repair module is used for detecting and repairing over-erased memory cells;
the erasing module is used for erasing the memory units which are pre-programmed by the pre-programming module, the verification module and the mark neglecting module are matched to circularly erase all the sectors in which the memory units are not successfully erased to the erasing module again until the memory units of all the sectors finish the erasing operation, and the over-erasing detection and repair module can circularly perform over-erasing detection and repair on all the memory units which finish the erasing operation until all the over-erased memory units finish the repair.
According to the device for reducing the erasing time, the all 0 programming is carried out on the storage unit in the sector of the target object to be erased through the pre-programming module, then the sector erasing is carried out through the erasing module periodically and circularly, the verification module is matched with the mark ignoring module to carry out verification, marking and ignoring on the sector which is erased, the sector which is erased is gradually ignored to carry out the erasing operation pertinently, the invalid operation on the erased sector can be avoided, the over erasing on the sector which is erased is effectively avoided, the repairing time of the over erasing is reduced, the erasing efficiency of the NOR Flash chip is improved, the over erasing detection and repairing of the storage unit are finished through the over-erasing detection repairing module, and the normal use of the storage unit after the erasing is ensured.
In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the present application provides an electronic device 3, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.
In a fourth aspect, the present application provides a storage medium, and when being executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, the method, the device, the electronic device and the storage medium for reducing the erasing time provided by the embodiments of the present application perform sector erasing through periodic cycle, mark and ignore sectors that have been erased, gradually ignore sectors that have been erased to perform the erasing operation in a targeted manner, which can avoid invalid operations on erased sectors, effectively avoid over-erasing the sectors that have been erased, reduce the repair time of over-erasing, and improve the erasing efficiency of the NOR Flash chip.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A method for reducing erase time for NOR Flash erase operations, the method comprising the steps of:
s1, pre-programming the storage units in the sectors;
s2, erasing the memory cells in the sector;
s3, verifying the erased sectors and neglecting all sectors successfully erased in the storage units;
s4, repeating the steps S2-S3 until the memory cells of all the sectors are erased;
and S5, performing over-erasure detection and repair on the storage units in all the sectors.
2. The method of claim 1, wherein the step of performing S1 is further preceded by the step of:
s0, checking whether the memory cells in each sector are in an erasing state, and ignoring the sectors in which the memory cells are in the erasing state.
3. The method of claim 2, wherein step S0 further comprises marking the sectors where all the cells are in an erased state.
4. The method of claim 1, wherein step S3 further comprises marking erased sectors according to the number of times of circular erasing to distinguish the erasing speed of the corresponding sectors.
5. The method of claim 4, wherein the determination condition of "until all sectors' memory cells are erased" in step S4 is to determine whether all sectors are erased or whether all sectors are ignored.
6. The method of claim 1, wherein the pre-programming in step S1 is to program all "0" memory cells in all sectors to be erased.
7. The method of claim 1, wherein step S5 includes the following sub-steps:
s51, checking whether an over-erased storage unit exists;
s52, repairing the over-erased storage unit;
s53, repeating the steps S51-S52 until the over-erased memory cell is not checked.
8. An apparatus for reducing erase time for a NOR Flash erase operation, comprising:
the pre-programming module is used for pre-programming the storage units in the sector to be erased;
the erasing module is used for erasing the memory unit;
the verifying module is used for verifying whether all the storage units in the sector are successfully erased;
the mark neglecting module is used for marking and neglecting all sectors successfully erased by the memory units;
the over-erasure detection and repair module is used for detecting and repairing over-erased memory cells;
the erasing module is used for erasing the memory units which are pre-programmed by the pre-programming module, the verification module and the mark neglecting module are matched to circularly erase all the sectors in which the memory units are not successfully erased to the erasing module again until the memory units of all the sectors are completely erased, and the over-erasing detection and repair module can circularly perform over-erasing detection and repair on all the memory units which are completely erased until all the over-erased memory units are completely repaired.
9. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method of any of claims 1-7.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1-7.
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| WO2024032560A1 (en) * | 2022-08-11 | 2024-02-15 | 东芯半导体股份有限公司 | Method for over-erase repair, and storage apparatus |
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