CN112927743A - Erasing verification method and device for storage unit, computer equipment and storage medium - Google Patents
Erasing verification method and device for storage unit, computer equipment and storage medium Download PDFInfo
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- CN112927743A CN112927743A CN201911233562.XA CN201911233562A CN112927743A CN 112927743 A CN112927743 A CN 112927743A CN 201911233562 A CN201911233562 A CN 201911233562A CN 112927743 A CN112927743 A CN 112927743A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
Abstract
The embodiment of the invention discloses an erasing verification method and device of a storage unit, computer equipment and a storage medium. The method comprises the following steps: when the requirement for erasing verification of a storage block is determined to be generated, acquiring a current erasing circulation statistical result of the storage block; and inquiring an erasing verification mode matched with the current erasing circulation statistical result to perform erasing verification on each storage unit in the storage block. The embodiment of the invention can reduce the erasing loss of the flash memory while considering the erasing verification.
Description
Technical Field
The embodiment of the invention relates to the field of data processing, in particular to an erasing verification method and device of a storage unit, computer equipment and a storage medium.
Background
Current non-volatile memory products have electronic programming and erase functions. For example, in the field of Flash memories (Flash memories), Flash memories are semiconductor-based memories and have the functional characteristics that internal information can be still retained and online erasing can be performed after a system is powered off, and at present, Flash memories are mainly classified into two categories, including NOR Flash memories (NOR Flash) and NAND Flash memories (NAND Flash), wherein the NOR Flash memories program devices through a hot electron injection mechanism and erase devices through a tunnel effect, and the programming and erasing of the NAND Flash memories are both realized through the tunnel effect.
Specifically, the physical structure of the NAND flash determines that the erase operation is block erase, that is, the erase operation is performed simultaneously on a plurality of memory cells included in a certain memory block (a certain area), but not individually on each memory cell. The erasing operation is actually to apply zero voltage or negative voltage to the control gate of each memory cell of a certain memory block and positive voltage to the P-type silicon semiconductor substrate. After the erasing operation is executed, erasing verification is needed, and when each memory unit in the memory block passes the erasing verification, the memory block is determined to be successfully erased. The existing erase verification methods include word line simultaneous verification (all word line verify) and word line alternate verification (alternate word line verify).
The word line simultaneous verification method is prone to over-erasure, which causes a large number of interface defects in the memory device during the cyclic erasing process, and further causes the degradation of the cyclic erasing capability. In the word line alternate verification mode, in the initial use of the memory device, the coupling between a programming unit and an erasing unit is easy to occur in programming due to the shallow erasing depth, so that the error reading probability is increased.
Disclosure of Invention
The embodiment of the invention provides an erasing verification method and device of a storage unit, computer equipment and a storage medium, which can reduce erasing loss of a flash memory while considering erasing verification.
In a first aspect, an embodiment of the present invention provides an erase verification method for a memory cell, including:
when the requirement for erasing verification of a storage block is determined to be generated, acquiring a current erasing circulation statistical result of the storage block;
and inquiring an erasing verification mode matched with the current erasing circulation statistical result to perform erasing verification on each storage unit in the storage block.
In a second aspect, an embodiment of the present invention provides an erase verification apparatus for a memory cell, including:
the current erasing cycle statistical result obtaining module is used for obtaining the current erasing cycle statistical result of the storage block when the erasing verification requirement on the storage block is determined to be generated;
and the erasing verification module is used for inquiring an erasing verification mode matched with the current erasing circulation statistical result to carry out erasing verification on each storage unit in the storage block.
In a third aspect, an embodiment of the present invention further provides an apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the method for verifying erasure of a memory cell according to any one of the embodiments of the present invention when executing the computer program.
In a fourth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the erase verification method for the memory cell according to any one of the embodiments of the present invention.
According to the embodiment of the invention, the erasing verification mode is selected according to the erasing cycle statistical result, so that the erasing verification mode is selected according to the erasing times, the problem that the cycle erasing capability is degraded due to the fact that only a word line simultaneous verification mode is adopted or the error reading probability is increased due to the fact that only a word line alternate verification mode is adopted in the prior art is solved, the proper erasing verification method is selected according to the erasing times of the memory unit, the loss of the cycle erasing capability is reduced, and the error reading probability is reduced.
Drawings
FIG. 1 is a flowchart illustrating a method for verifying erase of a memory cell according to a first embodiment of the present invention;
FIG. 2 is a flowchart illustrating a method for verifying erase of a memory cell according to a second embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an erase verification apparatus for a memory cell according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of a computer device in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
For the convenience of understanding, the erase verification process of the memory cell in the prior art will be briefly described first.
Non-volatile memory products integrate the ability to electronically program and erase memory cells. Electronic programming is actually writing data in a memory cell, specifically storing data by changing the number of electrons in the floating gate. Erasing refers to erasing the data written in the memory, and the erasing can be realized by reversing the voltage during the electronic programming. The minimum unit of an erase operation of a memory is a block, which is determined by the physical structure of the memory, that is, each erase operation is performed simultaneously for a certain number of memory cells in a certain area, and an erase operation is not performed individually for each memory cell. The erasing operation of the memory is to apply zero voltage or negative voltage to the control gates of a certain number of memory cells in a certain area and positive voltage to the substrate. Because the memory cells may not be identical due to process variations, fatigue aging, and the like, it cannot be guaranteed that all the memory cells in the erase region are successfully erased after one erase operation is completed, that is, all the memory cells in the erase region may not pass the erase verification after one erase operation. That is, a round of erase operations is not considered complete until all memory cells in the area are successfully erased, so a complete round of erase operations may include multiple erase operations.
Example one
Fig. 1 is a flowchart of a method for verifying an erase of a memory cell according to a first embodiment of the present invention, where the method is applicable to a case where the memory cell is verified by erasing after the memory cell is erased, and the method can be executed by an apparatus for verifying an erase of a memory cell according to an embodiment of the present invention, where the apparatus can be implemented in a software and/or hardware manner, and can be generally integrated into an electronic device, such as a terminal device or a server. As shown in fig. 1, the method of this embodiment specifically includes:
s110, when the requirement for the erasing verification of the storage block is determined to be generated, the current erasing circulation statistical result of the storage block is obtained.
Specifically, in a memory, a memory block (block) is the smallest unit of erase. Generally, in a memory, a plurality of memory cells form one page (page) and a plurality of pages form one memory block, where a page is the smallest unit of reading and writing. One memory cell may include a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) structure including a floating gate. Meanwhile, bit lines (bitlines) and word lines (wordlines) are configured in the memory to establish a connection relationship between the memory cells for controlling the plurality of memory cells.
The erase verification of the memory block is used to determine whether the stored data of the memory cells in the memory block is erased, i.e., whether the threshold voltage of the memory cells exceeds a preset erase verification voltage threshold.
The erase verify requirement is used to determine whether the memory block is in an erase verify process. Illustratively, when a memory block completes an erase operation, it is determined that an erase verification requirement for the memory block is generated.
Optionally, the determining generates an erase verification requirement for the memory block, including: and determining to generate an erase verification requirement for the memory block after the erase state of the memory block is completed.
In fact, before programming, that is, writing data, it is necessary to ensure that the history data in the memory is erased completely, so as to avoid that the history stored data interferes with the subsequent programming, resulting in data storage errors. It will be appreciated that erase verification must be performed after the erase operation is completed to ensure that the history data is erased. Thus, the erase operation can be completed as a necessary condition for the erase verification. The erase state completion is used to determine that the erase operation of the memory block is completed, and may refer to, for example, completion of one erase operation or completion of a plurality of cumulative (e.g., three) erase operations. By judging the erase verification requirement based on the erase state, the generation of the erase verification requirement can be accurately judged.
And the current erasing cycle counting result is used for counting the number of erasing cycles of the memory or the memory block.
Typically, one erase cycle includes at least one erase operation and at least one erase verify operation. Illustratively, one erase operation will be completed, along with an erase verify operation performed for that erase operation, as one erase cycle.
Optionally, the current erase cycle statistics include statistics of the number of times of completing one erase verification for the memory block. At this time, the number of times of erase verification may be counted as the current erase cycle counting result. By taking the number of times of erasure verification as a statistical result of the erasure cycle, the number of times of erasure can be accurately recorded.
Or, when the erase verification is passed, the associated at least one erase operation and at least one erase verification operation are taken as one erase cycle. In addition, an erase cycle may be in other forms, and the embodiments of the present invention are not limited in particular.
And S120, inquiring an erasing verification mode matched with the current erasing circulation statistical result to perform erasing verification on each storage unit in the storage block.
The erase verification mode is used to verify whether all the memory cells in the memory block are completely erased. Specifically, the erase verify mode may include word line simultaneous verify and word line alternate verify.
And when the threshold voltage of all the memory cells in one memory block is less than or equal to the erasing verification voltage, the erasing operation is stopped and the successful erasing is judged. The threshold voltage may refer to an input voltage corresponding to a midpoint of a transition region where an output voltage of a transfer characteristic curve sharply changes with a change of an input voltage, and in the mosfet, the threshold voltage is a gate voltage when the transistor is in a critical on state.
The word line alternate verification method divides the process of applying the erasing voltage once into two times, wherein a reading voltage higher than the erasing verification voltage is applied to an even word line for the first time, and the erasing verification voltage is applied to an odd word line for the first time. The reverse operation is performed a second time, i.e., an erase verify voltage is applied to the even word lines and a read voltage higher than the erase verify voltage is applied to the odd word lines. And recording as a complete erasing process after the two operations are finished, and when the threshold voltages of all the memory cells in one memory block are less than or equal to the erasing verification voltage, stopping the erasing operation and judging that the erasing is successful.
Optionally, the querying an erase verification mode matching the current erase cycle statistical result includes: comparing the current erasing circulation statistical result with at least one preset erasing circulation time threshold; and inquiring the erasing verification mode matched with the current erasing circulation statistical result from the preset corresponding relation between the comparison result and the erasing verification mode according to the comparison result.
Specifically, the threshold of the number of erase cycles is used to represent the degradation degree of the cyclic erasing capability of the memory block. Multiple erase cycle number thresholds can be configured in advance and respectively correspond to different cyclic erasing capabilities, so that the erase verification mode of the memory block is corresponded, generally, the cyclic erasing capabilities are worse and worse along with the service time of the memory block, and the erase verification mode needs to be adjusted accordingly. The reliability of the erasing verification mode is improved by configuring a plurality of erasing cycle times thresholds and determining the erasing verification mode currently applicable to the storage block according to the comparison result with the current erasing cycle statistical result, so that the erasing precision of the storage block is ensured, the interference of unclean erasing on subsequent written data is reduced, and the accuracy of the stored data of the storage block is improved.
Optionally, the querying, according to the comparison result, the erase verification manner matched with the current erase cycle statistic result from the preset correspondence between the comparison result and the erase verification manner includes: if the current erasing circulation statistical result is smaller than the first circulation time threshold, determining that the erasing verification mode is a word line simultaneous verification mode; and if the statistical result of the current erasing circulation is more than or equal to the threshold of the first circulation times, determining that the erasing verification mode is a word line alternate verification mode.
In fact, for the word line simultaneous verification method, if all the memory cells pass the erase verification, it is only necessary to ensure that the memory cell that is the hardest to erase passes the erase verification, that is, the memory cell with the largest threshold voltage is equal to or less than the erase verification voltage. That is, whether all the memory cells pass the erase verification is determined by the memory cell having the largest threshold voltage. It can be understood that the word line simultaneous verification method may cause over-deep erase in the memory block, which may cause a large amount of interface defects in the memory cells during the cyclic erase process, and further cause degradation of the cyclic erase capability. However, when the memory block is just erased, i.e. for a new memory block (fresh block), the erase depth can help reduce the coupling effect of the programmed cells on the erased cells, and reduce the read error condition.
For the word line alternate verification mode, a read voltage higher than the erase verification voltage is applied to two adjacent word lines of each word line to which the erase verification voltage is applied. After the memory cell is erased and written circularly for a certain number of times, the threshold voltage of the memory cell is increased due to the interface defect, so that the channel is difficult to open when an erasing voltage equal to an erasing verification voltage is applied, and at the moment, a reading voltage which is higher than the erasing verification voltage and is applied to two adjacent word lines can help the word lines to open the channel under the influence of a coupling effect, so that the erasing verification is passed, the situation of over-deep erasing is improved, the circular erasing and writing capability of the device can be enhanced, and the larger the reading voltage is, the more obvious the improvement is. However, when a new memory block is adopted, due to the shallow erase depth, the coupling effect of the programmed unit on the erased unit is easy to occur under the condition of programming some memory units, so that the error reading probability is increased, and the error reading probability is also increased when the read voltage is increased.
Therefore, when the memory block is just used, a word line simultaneous verification mode needs to be adopted, after the memory block is used for a period of time, namely after the memory block is circularly erased for a set number of times, a word line alternate verification mode needs to be adopted, the erasing depth is increased when the memory block is used for a small number of times, the erasing strength is increased, the error reading probability is reduced, and the circular erasing capability is improved after the memory block is used for a large number of times, so that the error reading probability is reduced.
The first cycle number threshold is used for representing the service life of the memory block or the memory and distinguishing the old memory block from the new memory block, namely for judging the fresh state of the memory block. Illustratively, the first threshold number of cycles is 200. In addition, the first threshold value of the number of cycles may also be other values, and the embodiment of the present invention is not particularly limited.
Optionally, the erasing verification method is a word line alternate verification method, and the querying for a matched erasing verification method from a preset corresponding relationship between the comparison result and the erasing verification method according to the comparison result includes: if the current erasing loop statistical result is more than or equal to the first loop time threshold and less than a preset second loop time threshold, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a first voltage; if the current erasing loop statistical result is larger than or equal to the second loop time threshold value, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a second voltage; the second cycle threshold is greater than the first cycle threshold, and the second voltage is greater than the first voltage.
Specifically, the applied voltage may be further adjusted for the word line alternate verify mode. The second cycle number threshold is used to characterize the life of the memory block or memory and to distinguish whether the memory block is approaching an end-of-life stage. And when the current erasing cycle statistical result is larger than or equal to the second cycle time threshold value, indicating that the storage block is close to the service life end period.
It should be noted that, when the current erase cycle statistical result is smaller than the first cycle threshold, it indicates that the memory is a new memory, the erase time of the memory is shortest, and the cyclic erase and write capability is strongest; when the current erasing cycle statistical result is more than or equal to the first cycle time threshold and less than the second cycle time threshold, indicating that the erasing time of the memory is medium and the cyclic erasing capability is medium; when the statistical result of the current erasing circulation is larger than or equal to the second circulation time threshold value, the erasing time of the memory is longest, and the circulation erasing capability is worst.
When the erasing frequency of the memory is increased, the reading voltage applied in the erasing verification is increased, so that the cyclic erasing capability is further improved, the erasing strength is further improved, the accuracy of data writing is ensured, and the error reading probability is reduced.
Optionally, on the basis of the foregoing embodiment, after performing erase verification, the method further includes: programming the memory block; erasing the memory block upon determining that the memory block requires reprogramming.
In particular, the memory block is programmed for storing data into the memory block. The memory block is reprogrammed for data update of the memory block. Generally, only when data update needs to be performed on the memory block, an erase operation needs to be performed on the memory block to erase the originally stored data of the memory cell to write the latest data. By programming in the memory block to write data after erase verification, the accuracy of data writing is ensured, and the memory performance of the memory block is improved.
According to the embodiment of the invention, the erasing verification mode is selected according to the erasing cycle statistical result, so that the erasing verification mode is selected according to the erasing times, the problem that the cycle erasing capability is degraded due to the fact that only a word line simultaneous verification mode is adopted or the error reading probability is increased due to the fact that only a word line alternate verification mode is adopted in the prior art is solved, the proper erasing verification method is selected according to the erasing times of the memory unit, the loss of the cycle erasing capability is reduced, and the error reading probability is reduced.
Example two
Fig. 2 is a flowchart of an erase verification method of a memory cell according to a second embodiment of the present invention, which is optimized based on the second embodiment, and the erase verification method that matches the query with the current erase cycle statistical result is embodied as: comparing the current erasing circulation statistical result with at least one preset erasing circulation time threshold; and inquiring the erasing verification mode matched with the current erasing circulation statistical result from the preset corresponding relation between the comparison result and the erasing verification mode according to the comparison result. Meanwhile, according to the comparison result, the erasing verification mode matched with the current erasing circulation statistic result is inquired from the corresponding relation between the preset comparison result and the erasing verification mode, and the method is characterized in that: if the current erasing circulation statistical result is smaller than the first circulation time threshold, determining that the erasing verification mode is a word line simultaneous verification mode; and if the statistical result of the current erasing circulation is more than or equal to the threshold of the first circulation times, determining that the erasing verification mode is a word line alternate verification mode. If the current erasing loop statistical result is larger than or equal to the first loop time threshold and smaller than a preset second loop time threshold, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a first voltage; if the current erasing loop statistical result is larger than or equal to the second loop time threshold value, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a second voltage; the second cycle threshold is greater than the first cycle threshold, and the second voltage is greater than the first voltage. As shown in fig. 2, the method of this embodiment specifically includes:
s210, when the requirement for the erasing verification of the storage block is determined to be generated, the current erasing circulation statistical result of the storage block is obtained.
The memory block, the erase verification requirement, the current erase cycle statistic result, the erase cycle number threshold, the word line simultaneous verification mode and the word line alternate verification mode of the present embodiment may refer to the description of the above embodiments.
S220, comparing the current erasing circulation statistical result with at least one preset erasing circulation time threshold value.
S230, if the statistical result of the current erasing circulation is smaller than the threshold value of the first circulation times, determining that the erasing verification mode is a word line simultaneous verification mode.
S240, if the statistical result of the current erasing circulation is more than or equal to the threshold value of the first circulation times, determining that the erasing verification mode is a word line alternate verification mode.
S250, if the current erase cycle statistic result is greater than or equal to the first cycle threshold and smaller than a preset second cycle threshold, determining that the erase verification mode is a word line alternate verification mode, and the read voltage applied in the word line alternate verification mode is a first voltage.
S260, if the current erase cycle statistic result is greater than or equal to the second cycle threshold, determining that the erase verification mode is a word line alternate verification mode, and the read voltage applied in the word line alternate verification mode is a second voltage, where the second cycle threshold is greater than the first cycle threshold, and the second voltage is greater than the first voltage.
According to the embodiment of the invention, the erasing verification mode is determined according to the comparison result of the current erasing cycle statistical result and the first cycle threshold, and the applied voltage of the word line alternate verification mode is determined according to the comparison result of the current erasing cycle statistical result and the second cycle threshold, so that the erasing strength is increased, the cyclic erasing capability is improved, the error reading probability is reduced, and the storage performance of the memory is improved.
EXAMPLE III
FIG. 3 is a diagram illustrating an apparatus for verifying erase of a memory cell according to a third embodiment of the present invention. The third embodiment is a corresponding apparatus for implementing the method for verifying the erasure of the memory cell provided by the above embodiments of the present invention, and the apparatus may be implemented in a software and/or hardware manner, and may be generally integrated into an electronic device, for example, a computer device.
Accordingly, the apparatus of the present embodiment may include:
a current erase cycle statistic result obtaining module 310, configured to obtain a current erase cycle statistic result of a storage block when it is determined that an erase verification requirement for the storage block is generated;
and the erasure verification module 320 is configured to query an erasure verification manner matched with the current erasure cycle statistical result to perform erasure verification on each memory cell in the memory block.
According to the embodiment of the invention, the erasing verification mode is selected according to the erasing cycle statistical result, so that the erasing verification mode is selected according to the erasing times, the problem that the cycle erasing capability is degraded due to the fact that only a word line simultaneous verification mode is adopted or the error reading probability is increased due to the fact that only a word line alternate verification mode is adopted in the prior art is solved, the proper erasing verification method is selected according to the erasing times of the memory unit, the loss of the cycle erasing capability is reduced, and the error reading probability is reduced.
Further, the erase verification module 320 includes: the comparison unit is used for comparing the current erasing circulation statistical result with at least one preset erasing circulation time threshold; and inquiring the erasing verification mode matched with the current erasing circulation statistical result from the preset corresponding relation between the comparison result and the erasing verification mode according to the comparison result.
Further, the comparison unit includes: a verification mode determining subunit, configured to determine that the erase verification mode is a word line simultaneous verification mode if the current erase cycle statistics result is smaller than the first cycle number threshold; and if the statistical result of the current erasing circulation is more than or equal to the threshold of the first circulation times, determining that the erasing verification mode is a word line alternate verification mode.
Further, the erase verification mode is a word line alternate verification mode, and the verification mode determines a subunit, which is specifically configured to: if the current erasing loop statistical result is more than or equal to the first loop time threshold and less than a preset second loop time threshold, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a first voltage; if the current erasing loop statistical result is larger than or equal to the second loop time threshold value, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a second voltage; the second cycle threshold is greater than the first cycle threshold, and the second voltage is greater than the first voltage.
Further, the current erase cycle statistics obtaining module 310 includes: and the erasing verification requirement judging unit is used for determining to generate the erasing verification requirement on the storage block after the erasing state of the storage block is finished.
Further, the current erase cycle statistics include statistics of the number of times of completing one erase verification for the memory block.
Further, the erase verification apparatus for a memory cell further includes: a program-erase module for programming the memory block after performing erase verification; erasing the memory block upon determining that the memory block requires reprogramming.
The device for verifying the erasure of the memory cell can execute the method for verifying the erasure of the memory cell provided by the embodiment of the invention, and has the corresponding functional modules and beneficial effects of the executed method for verifying the erasure of the memory cell.
Example four
Fig. 4 is a schematic structural diagram of a computer device according to a fourth embodiment of the present invention. FIG. 4 illustrates a block diagram of an exemplary computer device 12 suitable for use in implementing embodiments of the present invention. The computer device 12 shown in FIG. 4 is only one example and should not bring any limitations to the functionality or scope of use of embodiments of the present invention.
As shown in FIG. 4, computer device 12 is in the form of a general purpose computing device. The components of computer device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including the system memory 28 and the processing unit 16. The computer device 12 may be a server or a client.
Computer device 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer device 12 and includes both volatile and nonvolatile media, removable and non-removable media.
The system memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM)30 and/or cache memory 32. Computer device 12 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, storage system 34 may be used to read from and write to non-removable, nonvolatile magnetic media (not shown in FIG. 4, and commonly referred to as a "hard drive"). Although not shown in FIG. 4, a magnetic disk drive for reading from and writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk (e.g., a Compact disk Read-Only Memory (CD-ROM), Digital Video disk (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 18 by one or more data media interfaces. System memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the invention.
A program/utility 40 having a set (at least one) of program modules 42 may be stored, for example, in system memory 28, such program modules 42 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which examples or some combination thereof may comprise an implementation of a network environment. Program modules 42 generally carry out the functions and/or methodologies of the described embodiments of the invention.
Computer device 12 may also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), with one or more devices that enable a user to interact with computer device 12, and/or with any devices (e.g., network card, modem, etc.) that enable computer device 12 to communicate with one or more other computing devices. Such communication may be through an Input/Output (I/O) interface 22. Also, computer device 12 may communicate with one or more networks (e.g., Local Area Network (LAN), Wide Area Network (WAN)) via Network adapter 20. As shown, Network adapter 20 communicates with other modules of computer device 12 via bus 18. it should be understood that although not shown in FIG. 4, other hardware and/or software modules may be used in conjunction with computer device 12, including without limitation, microcode, device drivers, Redundant processing units, external disk drive Arrays, (Redundant Arrays of Inesponsive Disks, RAID) systems, tape drives, data backup storage systems, and the like.
The processing unit 16 executes various functional applications and data processing by running a program stored in the system memory 28, for example, to implement a method for verifying erasure of a memory cell provided in any of the embodiments of the present invention.
EXAMPLE five
An embodiment five of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for verifying the erasure of a memory cell according to the embodiments of the present invention:
that is, the program when executed by the processor implements: when the requirement for erasing verification of a storage block is determined to be generated, acquiring a current erasing circulation statistical result of the storage block; and inquiring an erasing verification mode matched with the current erasing circulation statistical result to perform erasing verification on each storage unit in the storage block.
Computer storage media for embodiments of the invention may employ any combination of one or more computer-readable media. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM), a flash Memory, an optical fiber, a portable CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, Radio Frequency (RF), etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a LAN or a WAN, or the connection may be made to an external computer (for example, through the Internet using an Internet service provider).
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. An erase verification method for a memory cell, comprising:
when the requirement for erasing verification of a storage block is determined to be generated, acquiring a current erasing circulation statistical result of the storage block;
and inquiring an erasing verification mode matched with the current erasing circulation statistical result to perform erasing verification on each storage unit in the storage block.
2. The method of claim 1, wherein querying for a way to verify that the current erase cycle statistics match comprises:
comparing the current erasing circulation statistical result with at least one preset erasing circulation time threshold;
and inquiring the erasing verification mode matched with the current erasing circulation statistical result from the preset corresponding relation between the comparison result and the erasing verification mode according to the comparison result.
3. The method of claim 2, wherein the querying the erasure verification pattern matching the current erasure loop statistical result from the preset correspondence between the comparison result and the erasure verification pattern according to the comparison result comprises:
if the current erasing circulation statistical result is smaller than the first circulation time threshold, determining that the erasing verification mode is a word line simultaneous verification mode;
and if the statistical result of the current erasing circulation is more than or equal to the threshold of the first circulation times, determining that the erasing verification mode is a word line alternate verification mode.
4. The method of claim 3, wherein the erase verify mode is a word line alternate verify mode,
the inquiring of the matched erasing verification mode from the preset corresponding relation between the comparison result and the erasing verification mode according to the comparison result comprises the following steps:
if the current erasing loop statistical result is more than or equal to the first loop time threshold and less than a preset second loop time threshold, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a first voltage;
if the current erasing loop statistical result is larger than or equal to the second loop time threshold value, determining that the erasing verification mode is a word line alternate verification mode, and the reading voltage applied in the word line alternate verification mode is a second voltage;
the second cycle threshold is greater than the first cycle threshold, and the second voltage is greater than the first voltage.
5. The method of claim 1, wherein the determining generates an erase verification requirement for the memory block, comprising:
and determining to generate an erase verification requirement for the memory block after the erase state of the memory block is completed.
6. The method of claim 1, wherein the current erase cycle statistics comprise statistics of a number of times an erase verify is completed for the memory block.
7. The method of claim 1, after performing erase verification, further comprising:
programming the memory block;
erasing the memory block upon determining that the memory block requires reprogramming.
8. An apparatus for verifying erasure of a memory cell, comprising:
the current erasing cycle statistical result obtaining module is used for obtaining the current erasing cycle statistical result of the storage block when the erasing verification requirement on the storage block is determined to be generated;
and the erasing verification module is used for inquiring an erasing verification mode matched with the current erasing circulation statistical result to carry out erasing verification on each storage unit in the storage block.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of erase verification of a memory cell according to any one of claims 1 to 7 when executing the program.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out a method of erase verification of a memory cell according to any one of claims 1 to 7.
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