CN113360421A - Flash memory erasing method and system and computer storage medium - Google Patents
Flash memory erasing method and system and computer storage medium Download PDFInfo
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- CN113360421A CN113360421A CN202110715752.6A CN202110715752A CN113360421A CN 113360421 A CN113360421 A CN 113360421A CN 202110715752 A CN202110715752 A CN 202110715752A CN 113360421 A CN113360421 A CN 113360421A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The invention provides an erasing method and system of a flash memory and a computer storage medium, when the flash memory is erased according to blocks and is erased to a certain block of the flash memory, after an erasing pulse with initial erasing bias voltage is applied to the certain block, first erasing verification is carried out on the certain block based on a first erasing verification threshold value, and only after all bits of at least one address in the certain block are not 0 or all bits of each address of the certain block are 1, the first erasing verification is completed and second erasing verification is carried out on the certain block based on a second erasing verification threshold value, so that the erasing pulse count used in the flash memory erasing verification can be reduced, the erasing time of the flash memory on the whole is greatly shortened, the erasing efficiency is improved, and the requirement of erasing the flash memory at a high speed can be met.
Description
Technical Field
The present invention relates to the field of flash memory technologies, and in particular, to a flash memory erasing method and system, and a computer storage medium.
Background
Flash memory, also known as flash memory, includes a memory array containing a large number of memory cells and typically grouped into blocks, flash memory is typically erased sequentially in the order of the addresses of the blocks, and erasing a block of flash memory sets all bits (bits) of the block to "1".
However, the existing flash memory erasing method is time-consuming in erasing the whole flash memory and low in erasing efficiency, and cannot meet the requirement of erasing the flash memory at a high speed.
Disclosure of Invention
The invention aims to provide a flash memory erasing method and system and a computer storage medium, which can greatly shorten the overall erasing time of the flash memory, improve the erasing efficiency and meet the requirement of erasing the flash memory at a high speed.
In order to solve the above technical problem, the present invention provides an erasing method of a flash memory, which erases the flash memory by blocks in an erase verification manner, and the method of erasing a certain block of the flash memory includes:
applying an erase pulse to said certain block;
performing first erase verification on the certain block based on a first erase verification threshold to judge whether all the readings of all the bits of at least one address in the certain block are not all 0 or judge whether all the readings of all the bits of all the addresses in the certain block are all 1;
if so, performing second erasure verification on the certain block based on a second erasure verification threshold value;
and if not, increasing the erasing bias voltage of the erasing pulse to add a new erasing pulse to the certain block, and further performing first erasing verification on the certain block based on the first erasing verification threshold value again.
Optionally, before performing the first erase verification for the certain block for the first time based on the first erase verification threshold, the address and erase pulse count of the certain block are reset, so that the first erase verification for the first time is sequentially performed for each address of the certain block based on the first erase verification threshold in the order of the address of the certain block from the first address of the certain block.
Optionally, each time the first erase verification and/or the second erase verification are performed, reading out a value of each address in order from a first address to a last address in an address order of the certain block, and comparing the value with 00 to determine whether all the bits of at least one address in the certain block have a reading of not all 0, or comparing the value with FF to determine whether all the bits of all the addresses in the certain block have a reading of all 1.
Optionally, when it is determined in the current first erase verification that the readings of all bits of any address in the certain block are not all 1, stopping the current first erase verification, increasing the erase bias of the erase pulse to add a new erase pulse to the certain block, and further performing the next first erase verification until all the readings of all bits of all addresses of the certain block are 1, determining that the certain block passes the first erase verification, and performing the second erase verification on the certain block based on a second erase verification threshold.
Optionally, the step of performing a second erase verification on the certain block based on the second erase verification threshold includes:
resetting the address of the certain block to a first address;
performing second erase verification on each address of the certain block according to the address sequence and based on the second erase verification threshold value to judge whether all the readings of all the bits of all the addresses in the certain block are all 1;
if so, finishing erasing the certain block;
and if not, increasing the erase pulse count and/or increasing the erase bias voltage of the erase pulse to apply a new erase pulse to the certain block, resetting the address of the certain block to the first address, and performing second erase verification on the certain block again based on the second erase verification threshold until the readings of all bits of all addresses in the certain block are all 1.
Optionally, when it is determined that the number of readings of all bits of any address in the certain block is not all 1, an erase pulse is newly added by keeping the erase bias of the erase pulse unchanged and increasing the erase pulse count, and it is determined whether the increased erase pulse count exceeds the maximum erase pulse count, if not, the newly added erase pulse is applied to all addresses of the certain block, so as to perform second erase verification on the certain block based on the second erase verification threshold again, and if so, the erase pulse is newly added and applied to all addresses of the certain block by increasing the erase bias of the erase pulse and resetting the erase pulse count, so as to perform second erase verification on the certain block based on the second erase verification threshold again.
Optionally, when the first erase verification is used to determine whether all bits of at least one address in the certain block have not been read as 0, the first erase verification threshold is lower or higher than the second erase verification threshold; when the first erase verification is used to determine whether all the readings of all the bits of each address in the certain block are all 1, the first erase verification threshold is higher than the second erase verification threshold.
Based on the same inventive concept, the present invention further provides an erasing system of a flash memory, which is used for erasing the flash memory by blocks in an erase verification manner, and the erasing system comprises:
an erasing pulse applying module for applying a corresponding erasing pulse to the certain block as required;
the first erasing verification module is used for performing first erasing verification on the certain block based on a first erasing verification threshold value after a corresponding erasing pulse is applied to the certain block so as to judge whether the readings of all bits of at least one address in the certain block are not all 0 or judge whether the readings of all bits of all addresses in the certain block are all 1;
a second erase verification module, configured to perform a second erase verification on the certain block based on a second erase verification threshold when the first erase verification module determines that all of the readings of all of the bits of at least one address in the certain block are not all 0 or all of the readings of all of the bits of all of the addresses in the certain block are all 1;
the erase pulse applying module is further configured to increase an erase bias of an erase pulse to add a new erase pulse to the block when the first erase verification module determines that all of the readings of all bits of all addresses in the block are all 0 or all of the readings of all bits of any address in the block are not all 1, so that the first erase verification module performs first erase verification on the block again based on the first erase verification threshold.
Optionally, the erasing system further includes a reset module configured to reset an address of the certain block before the first erase verification module performs first erase verification on the certain block based on the first erase verification threshold each time and before the second erase verification module performs second erase verification on the certain block based on the second erase verification threshold each time, and the number of reset erase pulses and an erase bias of the reset erase pulses are initial erase biases before the first erase verification module performs first erase verification on the certain block based on the first erase verification threshold;
and/or the erasing pulse applying module is further used for increasing the erasing pulse count and/or increasing the erasing bias voltage of the erasing pulse according to the judgment result of the second erasing verification module, and ensuring that the increased erasing pulse count does not exceed the maximum erasing pulse count so as to add a new erasing pulse to a certain block.
Optionally, when the first erase verification module is configured to determine whether all bits of at least one address in the certain block have readings that are not all 0, the first erase verification threshold is lower than or higher than the second erase verification threshold; when the first erase verification module is configured to determine that all the readings of all the bits of each address in the certain block are all 1, the first erase verification threshold is higher than the second erase verification threshold.
Based on the same inventive concept, the present invention also provides a computer storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the flash memory erasing method of the present invention.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
when the flash memory is erased according to blocks and a certain block of the flash memory is erased, after an erasing pulse with an initial erasing bias voltage is applied to the certain block, first erasing verification is carried out on the certain block on the basis of a first erasing verification threshold value, whether the reading of all bits of at least one address in the certain block is not all 0 is judged, if yes, second erasing verification is carried out on the certain block on the basis of a second erasing verification threshold value, or whether the reading of all bits of each address of the certain block is 1 (namely, whether all the addresses pass the first erasing verification is judged), and if yes, second erasing verification is carried out on the certain block on the basis of the second erasing verification threshold value; and under the condition that the judgment result of the first erase verification is negative, adding an erase pulse in a mode of increasing erase bias voltage to erase all the addresses of a certain block again, and performing the first erase verification on all the addresses of the certain block based on a first erase verification threshold value until the reading of all the bits of each address of the certain block is judged to be 1 or the reading of all the bits of at least one address is not 0 completely, and performing the second erase verification on the certain block based on a second erase verification threshold value, thereby reducing the erase pulse count used by the erase verification of the flash memory as a whole by using the first erase verification, particularly reducing the number of the pulses used in the re-erase after the flash memory passes through multiple (for example, more than 10 ten thousand) erase/write cycles, and greatly shortening the erase time of the flash memory as a whole, the erasing efficiency is improved, the requirement of erasing the flash memory at high speed can be met, and the erasing efficiency can be guaranteed along with the prolonging of the service life of the flash memory.
Drawings
Fig. 1 is a schematic flowchart of an erasing method of a flash memory in the prior art.
Fig. 2A is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased for the first time based on the flash memory erase method shown in fig. 1.
Fig. 2B is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased 100K times (i.e., 10 ten thousand times) based on the flash memory erase method shown in fig. 1.
Fig. 3 is a flowchart illustrating an erasing method of a flash memory according to an embodiment of the invention.
Fig. 4A is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased for the first time based on the flash memory erase method shown in fig. 3.
FIG. 4B is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased at 100K times based on the erase method of the flash memory shown in FIG. 3.
FIG. 5 is a flowchart illustrating a flash memory erasing method according to another embodiment of the present invention.
Fig. 6A is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased for the first time based on the flash memory erase method shown in fig. 3.
FIG. 6B is a schematic diagram of erase pulses and threshold voltage distributions of all addresses when the flash memory is erased at 100K times based on the erase method of the flash memory shown in FIG. 3.
FIG. 7 is a functional block diagram of an erase system for a flash memory according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It should also be noted that "block" herein is not limited to the meaning of a memory block as is conventional in the art, but may also be the meaning of a sector, page, etc., as is conventional in the art. The term "and/or" is used herein to mean either or both. An "address" herein is a byte address, each having, for example, 8 bits.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the conventional flash memory erasing method sequentially erases the flash memory blocks by using an erase verification method, and the step of erasing one of the flash memory blocks includes:
first, a block to be erased is selected, and an address of the block to be erased is reset (for example, a first address located to the block to be erased), an erase pulse count is reset (for example, the erase pulse count is set to 0), an erase bias of the erase pulse is reset (also referred to as a gate erase voltage) to an initial erase bias Vint (that is, a voltage difference between a gate and a source of a memory transistor of a memory cell is set to the initial erase bias Vint, which is generally a negative value);
then, an erase pulse having an initial erase bias Vint is applied to the block, the erase pulse being applied to all memory cells of the block (i.e., all addresses of the block);
then, starting from the first address of the block to be erased, performing erase verification (erase verify) in order to verify whether the threshold voltage VT of each bit of the address is lower than the target erase threshold EVT under the erase pulse (i.e. performing erase verification on the address based on the target erase threshold EVT), if so, the address passes the erase verification, the readings on all bits of the address are all "1", that is, the reading of the memory cell of the address is the number "FF" in 16 system, then increasing the address (for example, address +1) to perform erase verification on the next address, if not, first, under the condition of keeping the erase bias constant, adding an erase pulse to each address of the block to erase all addresses of the block again, and judging whether the current address is the maximum erase pulse count, if the maximum erase pulse count is not reached and any address in the block fails the erase verification, the erase pulse count continues to be incremented and the block is erased again and erase verification is performed based on the target erase threshold EVT until the erase pulse count reaches a maximum value or the block has passed erase verification if the maximum erase pulse count is not reached, if any address of the block has not passed erase verification yet when the maximum erase pulse count is reached, the erase bias of the erase pulse is further increased and the erase pulse count is reset to add an erase pulse to each address of the block again, to erase all addresses of the block again, and then erase verify is performed based on the target erase threshold EVT until all addresses of the block pass the erase verify when the erase pulse count is not higher than the maximum erase pulse count, the erasure of the block is thus considered to be effectively complete, i.e., the reading on each bit of each address of the block is "1". When the erase bias of the erase pulse is increased for multiple times, the amplitude of each increase is Vstep (which is a negative value), and the absolute value of the erase bias Vin + x Vstep of the erase pulse applied to the current block after the erase bias of the erase pulse is increased for the x-th time is larger than the absolute value of the erase bias Vin + (x-1) Vstep of the erase pulse applied to the current block at the previous time.
Obviously, the effective erase of each block depends on the erase time and erase bias voltage used, and the erase time depends on the number of erase pulses used (i.e. the sum of the erase pulse counts under all erase bias voltages), and it is general to set the time of one erase pulse to be 1ms and the maximum erase pulse count to be 8, and if in the prior art, a block is erased at the first erase of the flash memory, it is only necessary to use 6 erase pulses under the initial erase bias to successfully complete the erase of the block (i.e. the block is considered to be effectively erased by means of erase verification), but after 100K times of erasing the flash memory, even if the number of erase pulses reaches the maximum value of 8, the block cannot be successfully completed, and at this time, the erase bias voltage of 1 Vstep needs to be increased, and then the block is erased and verified, and when under the new erase bias, when the number of the erase pulses reaches the maximum value of 8, the erase of the block cannot be successfully completed, the erase bias voltage of 1 × Vstep is continuously increased, the block is erased and verified, and the process is repeated until the erase bias voltage is increased to a certain degree, and the erase of the block cannot be successfully completed until a corresponding number of erase pulses are applied under the final erase bias voltage.
As a specific example, referring to fig. 2A and 2B, if, in the prior art, when the flash memory is erased for the first time, all addresses (i.e., all memory cells) of the block are successfully erased, 7 erase pulses are required, and when the flash memory is erased for the 100K (i.e., 10 ten thousand) times, all addresses (i.e., all memory cells) of the block are successfully erased, 24 erase pulses are required, and the erase time of the block is relatively increased by 342%, it can be seen that the erase time of the whole flash memory is longer, and as the usage time of the flash memory is longer, the erase efficiency of the whole flash memory is more and more time-consuming, and the erase efficiency is more and more low, which cannot meet the requirement of erasing the flash memory at a high speed.
Based on this, the invention provides an erasing method of a flash memory, which can erase the flash memory in blocks and in sequence by adopting a first erasing verification mode and then adopting a second erasing verification mode, wherein the first erasing verification mode can enable the threshold voltage of each address of a corresponding block to be quickly close to the second erasing verification threshold used by the second erasing verification mode, so that the block can be effectively erased more quickly by less erasing pulse quantity, thereby effectively shortening the erasing time and improving the erasing efficiency. The specific process of erasing a certain block of the flash memory comprises the following steps:
applying an erase pulse to said certain block;
performing first erase verification on the certain block based on a first erase verification threshold to judge whether all the readings of all the bits of at least one address in the certain block are not all 0 or judge whether all the readings of all the bits of all the addresses in the certain block are all 1;
if so, performing second erasure verification on the certain block based on a second erasure verification threshold value;
and if not, increasing the erasing bias voltage of the erasing pulse to add a new erasing pulse to the certain block, and further performing first erasing verification on the certain block based on the first erasing verification threshold value again.
The erasing method of the flash memory according to the present invention will be described in detail with reference to the specific drawings and embodiments.
Referring to fig. 3, an embodiment of the present invention provides an erasing method for a flash memory, which can erase the flash memory by blocks and in sequence by using an erase verification method, wherein the flash memory has a memory array, the memory array is divided into a plurality of blocks, and each block includes a plurality of memory cells. All blocks and their internal memory locations are numbered sequentially, forming a corresponding block address and an address of the memory location within each block (i.e., the byte address each block contains).
In the erasing method of the flash memory of this embodiment, the method for erasing a certain block (i.e. a block to be erased, a current block) of the flash memory includes:
s1.1, resetting the address of the block to be erased (i.e. the current block) (e.g. the first address located to the block to be erased), resetting the erase pulse count (e.g. setting the erase pulse count to 0), and resetting the erase bias of the erase pulse to the initial erase bias;
s1.2, an erase pulse with a corresponding erase bias is applied to the block to be erased to erase bits (i.e. all memory cells) of all addresses in the block to be erased (i.e. the current block) and based on a first erase verify threshold EVT _1 in address order starting from the first address of the current blockstSequentially performing first erase verification on each address of the block to be erased (i.e., the current block), determining whether all bits of each address in the block to be erased (i.e., the current block) are all "0", if so, increasing an erase bias of an erase pulse to attach a new erase pulse to the certain block, and performing step S1.2 again, i.e., performing first erase verification on the certain block again based on the first erase verification threshold, otherwise, performing step S1.3.1, and resetting the address of the current block (e.g., to the first address of the current block) to perform step S1.3;
s1.3, based on being above the first erase verify threshold EVT _1stUntil all addresses of the block to be erased (i.e., the current block) are verified as erased, the second erase verification threshold EVT performs a second erase verification on the block to be erased (i.e., the current block).
In step S1.1, first, the block to be erased (i.e. the current block) may be pre-programmed to pre-program the threshold voltage of each memory cell to a predetermined level, for example, the threshold voltage of each memory cell is pre-programmed to above PVT, for example, when each address is a byte address having 8 bits, the step will set each bit of each address to "1", and the reading of the memory cell of each address is "FF" (converted to 8-bit binary number 11111111111); then, reset to the first address of the block to be erased, reset the erase pulse count to 0, reset the erase bias of the erase pulse to the initial erase voltage Vint (i.e., set the voltage difference between the gate and the source of the memory transistor of each memory cell to the initial erase bias Vint, and Vint is a negative value).
In step S1.2, when a block has 64K bytes, the addresses of the memory cells are 0x 0000-0 xFFFF, so after an erase pulse with an initial erase voltage Vint + x Vstep (where x ≧ 0) is applied to all the memory cells (i.e., all the addresses) of the block to be erased, the first erase verify threshold EVT _1 is usedstThe first erase verification is performed on this block, which is actually from 0x0000 to 0xFFFF in address order, the value of the memory cell of each address (which is actually an 8-bit binary number, but the read number is a 16-bit number) is read in sequence, and it is determined whether the value is "00" (i.e., whether the reading on each bit of the memory cell is 0), and if not, the second erase verification is entered. Wherein the specific process of step S1.2 is as follows:
s1.2.0, applying an erase pulse with initial erase voltage Vint + x Vstep (where x ≧ 0) to all memory cells (i.e., all addresses) of the block to be erased (i.e., the current block) to perform an erase operation on all addresses of the current block;
s1.2.1, starting from the first of the current blocks, based on a first erase verification threshold EVT _1 in address orderstThe first erase verification is performed for the current address, i.e. the first erase verification threshold EVT _1stComparing with the threshold voltage VT of each bit of the address, when the threshold voltage VT is not lower than EVT _1stWhen the bit corresponds to a reading of "0", when the threshold voltage VT is lower than EVT _1stThe corresponding reading at this bit is "1", i.e., based on the first erase verify threshold EVT _1stReading the memory of the current addressThe value of the cell;
s1.2.2, determining whether the readings on the bits of the current address are all "0", that is, determining whether the value read from the memory cell of the current address is "00" in 16-system, if not, performing step S1.3.1 to enter the second erase verification, if yes, performing step S1.2.3 to determine whether the current address is the last address of the current block to perform the first erase verification on the next address of the current block;
if the current address is not the last address of the current block, execute step S1.2.4, add the address (e.g., address +1), and loop through the above steps S1.2.1-S1.2.3 until the last address of the current block is also first erased and verified;
when the readings on the bits of the last address are all "0" (i.e. the readings of all the addresses of the current block are 16-ary numbers "00"), the following steps are performed in sequence: at step S1.2.5, the erase pulse count is incremented (i.e., incremented by 1); step S1.2.6, increasing the erase bias voltage of the erase pulse, i.e., V ═ Vint + x × Vstep, x plus 1; step S1.2.7, resetting the address to the first address of the current block, and returning to step S1.2.0 to add an erase pulse to all the addresses of the current block, wherein the erase bias of the added erase pulse is the increased erase bias, and further, the erase operation is performed again on all the addresses of the current block, and then step s1.2.1 and the subsequent steps are sequentially performed.
Therefore, through the cyclic process, the current block can be finally verified to be that the readings of all bits on at least one address are not all 0 after multiple rounds of first erase verification by increasing the erase bias of the erase pulse, so that the second erase verification can be entered, and the initial erase bias used by the second erase verification is the erase bias used by the end of the first erase verification, so that the number of erase pulses used for erasing the block of the flash memory as a whole can be reduced.
In step S1.3, performing at least one second erase verification on each address in the certain block until all addresses of the certain block pass the second erase verification (i.e., all addresses of the current block pass the second erase verification), which specifically includes the following steps:
s1.3.1, resetting the address to the first address of the current block (i.e., the block to be erased as described above);
s1.3.2, obtaining the threshold voltage VT of the memory cell of the current address to perform the second erase verification on the current address;
s1.3.3, determining whether the threshold voltage VT of each bit of the current address is lower than the second erase verify threshold value EVT, wherein the first erase verify threshold value EVT _1stThe second erase verify threshold value EVT and the second erase verify threshold value EVT are both voltage constants of the same order of magnitude as the threshold voltage of the memory transistor of the memory cell, and the second erase verify threshold value EVT of the present embodiment is the same as the erase verify threshold value in the related art and is higher (i.e., larger) than the first erase verify threshold value EVT _1stI.e. the first erase verify threshold EVT _1stLess than (i.e., below) the second erase verify threshold EVT.
If it is determined in step S1.3.3 that the threshold voltage VT of each bit of the current address is lower than the second erase verification threshold EVT, that is, it is determined that the reading of each bit of the current address is "1" (or, it is determined that the reading of the memory cell of the current address at this time is "FF", then it is determined that the current address passes the second erase verification, then step S1.3.4 is performed, it is determined whether the current address is the last address of the current block, if not, step S1.3.5 is performed, the address (for example, address +1) is added, and step S1.3.2 is returned, if it is the last address of the current block, the erase of the current block is completed, all the memory cells in the current block are verified as erased, that is, the current block is effectively erased;
if it is determined in the step S1.3.3 that the threshold voltage VT of any bit of the current address is higher than or equal to the second erase verification threshold EVT (i.e., the reading of any bit of the current address is not "1"), it is determined that the current address does not pass the second erase verification of the current time, and then steps S1.3.6-S1.3.10 are further performed to perform the erase operation and the second erase verification again on each address of the current block until all the addresses of the current block are determined to pass the second erase verification. In step S1.3.6, the erase pulse count is increased, that is, one new erase pulse is added while the erase bias of the erase pulse is kept unchanged, and the initial erase bias of the second erase verification is the final erase bias at the end of the first erase verification; s1.3.7, determining whether the current erase pulse count reaches the maximum erase pulse count, if not (i.e. not), executing S1.3.8, applying a new erase pulse to the current block to erase the current block, and returning to S1.3.2; if so (i.e., the maximum erase pulse count has been reached), steps S1.3.9-S1.3.10 are performed to increase the erase bias voltage of the erase pulse and reset the erase pulse count, e.g., reset the erase pulse count to 0, to apply a new erase pulse with a larger erase bias voltage to all addresses of the current block, and then return to step S1.3.2. Therefore, through the above loop process, the readings of all bits of all addresses of the current block are verified as "1", that is, all addresses of the current block pass the second erase verification, and the readings of all addresses of the current block are "FF", so that the current block is effectively erased.
Optionally, after step S1.3 is executed, when all addresses of the current block pass the second erase verification, further performing over-erase correction on all addresses of the current block to prevent a problem that a memory cell of a certain address is coupled to a bit line due to over-erase. And finishing the erasure of the current block after all the addresses of the current block are verified as effectively erased and the over-erased addresses are corrected.
It should be noted that the first erase verify threshold EVT _1 is selected in this embodimentstBelow the second erase verify threshold EVT, the verify window for making all the readings of all the bits of the respective addresses in the block to be erased "0" can be relaxed, so that the block to be erased can more easily end the first erase verify and enter the second erase verify after applying the erase pulse with the initial erase bias, and even the first erase verify of the block can be completed by only one erase pulse, the erase time of the flash memory is greatly reduced, and the erase efficiency is improved.
Referring to fig. 4A and 4B, if the flash memory erase method of the present embodiment is applied, during the first erase verification, 1 erase pulse is needed under Vint's initial erase bias and 1 erase bias is further added, and after applying the erase pulse with Vint +1 Vstep erase bias (i.e. the number of erase pulses is equal to 2) to the address N, the second erase verification can be entered, which keeps Vint +1 Vstep unchanged and further adds 2 erase pulses, so that during the first erase verification, all the addresses (i.e. all the memory cells) of the block are verified as erased (i.e. all the memory cells are effectively erased) by the first erase verification and the second erase verification, and only 4 erase pulses are needed, as shown in fig. 4A; whereas in the case of erasing the flash memory at the 100K (i.e., 10 ten thousand) times, the erase bias is increased by 5 times in total during the first erase verify, and 1 erase pulse is used at each erase bias, and after applying the erase pulse with Vint +5 Vstep erase bias (i.e., the number of erase pulses is equal to 6) to the address N, the second erase verify can be entered, and the entire process of the second erase verify is maintained with Vint +5 Vstep being further increased by 3 erase pulses, so that at the 100K (i.e., 10 ten thousand) erasing of the flash memory, all the addresses (i.e., all the memory cells) of the block are verified as erased (i.e., effective erasing of the block is completed) by the first erase verify and the second erase verify, only 9 erase pulses are needed, and the overall erasing time of the flash memory is not significantly increased compared to the first erase shown in fig. 4A, whereas the erase time is only increased by 128% compared to the prior art shown in fig. 2B. Therefore, after the flash memory erasing method of the embodiment is applied, the erasing time required for effectively erasing the flash memory in the whole process is greatly reduced, and after the flash memory erasing method of the embodiment is applied, along with the prolonging of the using time of the flash memory, the time consumption of the flash memory in the whole process is not obviously increased greatly compared with the time consumption for erasing the flash memory for the first time, the erasing efficiency is greatly improved, and therefore the requirement for erasing the flash memory at a high speed can be met.
In addition, it should be noted that although the first erase verification threshold EVT _1 is described in the above embodimentstThe first erase verify threshold value EVT _1 is set to be lower than the second erase verify threshold value EVT, but the technical solution of the present invention is not limited to the implementation of the above-described embodiment, and in other embodiments of the present invention, the first erase verify threshold value EVT _1stIt is also possible to go above (i.e. above) the second erase verification threshold EVT and to end the first erase verification and enter the second erase verification for the block if all bits of any address in the block to be erased at the time of the first erase verification do not read all 0's, in such a way that the second erase verification can be entered earlier than in the prior art, although this scheme is relative to the first erase verification threshold EVT _1stSet below the second erase verify threshold EVT and when the first erase verify reads all bits of any address in the block to be erased are not 0, the scheme of second erase verify "for that block uses a longer erase time but still has a shorter erase time than the prior art scheme. In addition, in other embodiments of the present invention, a second erase verification may be performed after all memory cells in a block to be erased pass the first erase verification, in this way, an erase pulse is newly added only by increasing an erase bias in the first erase verification stage, and an erase bias initial value of the erase pulse of the second erase verification is an erase bias set when all addresses of the block pass the first erase verification, so that a problem that the second erase verification uses a large number of erase pulses when the erase bias is small can be avoided, thereby shortening the number of erase pulses used by the flash memory as a whole when erasing a certain block, shortening the erase time, and further improving the erase efficiency.
The following is a "first erase verify threshold EVT _1stThe second erase verification is performed after all the memory cells in the block to be erased pass the first erase verification, which is higher than the second erase verification threshold EVT, and the erase method of the flash memory according to another embodiment of the present invention is described in detail with reference to fig. 5 and fig. 6A to 6B.
Referring to fig. 5, another embodiment of the present invention provides an erasing method for a flash memory, which can erase the flash memory in blocks and in sequence, wherein the flash memory has a memory array, and the memory array is divided into a plurality of blocks, and each block includes a plurality of memory cells. All blocks and their internal memory locations are numbered sequentially, forming a corresponding block address and an address of the memory location within each block (i.e., the byte address each block contains).
In the erasing method of the flash memory of this embodiment, the method for erasing a certain block (i.e. a block to be erased, also referred to as a current block) of the flash memory includes:
s2.1, resetting the address, counting the erasing pulse, and resetting the erasing bias voltage of the erasing pulse as an initial erasing bias voltage;
s2.2, applying an erase pulse with a corresponding erase bias to the block to be erased to erase all addresses (i.e. all memory cells) in the block to be erased (i.e. the current block) and based on the first erase verify threshold EVT _1 in the order of addressesstPerforming first erase verification on each address of the block to be erased (i.e. the current block), and performing step S2.3 when all addresses in the block to be erased (i.e. the current block) pass the first erase verification;
s2.3, based on being below the first erase verify threshold EVT _1stUntil all addresses of the block to be erased (i.e., the current block) are verified as erased, the second erase verification threshold EVT performs a second erase verification on the block to be erased (i.e., the current block).
In this embodiment, the specific implementation manner of step S2.1 is the same as step S1.1 in the previous embodiment, and the specific implementation manner of step S2.3 is substantially the same as step S1.3 in the previous embodiment, which can be referred to the content of the previous embodiment, and therefore, details are not described here. Wherein the initial erase bias of the erase pulse used in step S2.3 of this embodiment is the erase bias when all addresses of the current block pass the first erase verify in step S2.2.
Compared with the previous embodiment, the difference between the erasing method of the flash memory of this embodiment and the previous embodiment is mainly in step S2.2. In step S2.2, the first erase verification is performed only at least once on each address by increasing the erase bias voltage, so that all addresses of the current block can finally pass the first erase verification, which includes the following specific steps:
s2.2.0, applying an erase pulse with corresponding erase bias voltage to all addresses of the current block to perform erase operation on the current block;
s2.2.1, obtaining the threshold voltage VT of each bit of the current address to perform the first erasing verification on the current address;
s2.2.2, it is determined whether the threshold voltage VT of each bit of the current address is lower than the first erase verify threshold EVT _1stThat is, it is determined whether the reading on each bit of the current address is "1" (i.e., it is determined whether the reading of the memory cell of the current address is "FF" in 16-ary), if yes, the current address passes the first erase verification, and step S2.2.3 is executed, if no, an erase pulse is added and applied to all addresses of the current block again, so as to perform the first erase verification on the current address again, for example, sequentially execute step S2.2.5: an erase pulse is added (i.e., a new erase pulse is added), and step S2.2.6: increasing the erase bias of the newly added erase pulse to increase Vstep from the previous erase pulse and applying it to all addresses of the current block, and further returning to steps S2.2.0 and S2.2.1 to perform the erase operation and the first erase verification again for all addresses of the current block until all addresses of the current block pass the first erase verification;
s2.2.3, determining whether the current address is the last address of the current block, if not (i.e. not), executing step S2.2.4, increasing the address (e.g. address +1), and returning to step S2.2.1 to perform the first erase verification on the next address of the current block, if so, the last address also passes the first erase verification, and at this time, all the addresses of the current block pass the first erase verification;
after determining in step S2.2.2 that the current address does not pass the current first erase verification, the current first erase verification process is stopped, and then the process of "step S2.2.5 → step S2.2.6 → step S2.2.0 → step S2.2.1 → step S2.2.2" is executed in a loop until all the addresses of the current block are determined to pass the subsequent first erase verification, thereby ending the first erase verification of the current block and proceeding to the second erase verification of step S2.3.
Referring to fig. 6A and 6B, if the flash memory erase method of the present embodiment is applied, during the first erase verification, 1 erase pulse is needed under Vint's initial erase bias and 1 erase bias is further added in the whole process of the first erase verification, and after applying the erase pulse with Vint +1 Vstep erase bias (i.e. the number of erase pulses is equal to 2) to the address N, the second erase verification can be entered, and the whole process of the second erase verification keeps Vint +1 Vstep unchanged and further 1 erase pulse is added, so that during the first erase verification, all addresses (i.e. all memory cells) of the block are verified as erased (i.e. the current block is effectively erased) by the first erase verification and the second erase verification, only 3 erase pulses are needed; whereas in erasing the flash memory for the 100K (i.e., 10 ten thousand) times, 1 erase pulse is required under Vint's initial erase bias and 5 further erase biases are added, and after applying erase pulses with Vint +5 Vstep erase bias (i.e., the number of erase pulses is equal to 6) to the address N, a second erase verify can be entered, which is performed while keeping Vint +5 Vstep unchanged and further adding 3 erase pulses, so that in erasing the flash memory for the first time, when all the addresses (i.e., all the memory cells) of the block are verified as erased (i.e., the current block is effectively erased) through the first erase verify and the second erase verify, only 9 erase pulses are required, and the overall erase time of the flash memory is not significantly increased compared to the first erase shown in fig. 6A, whereas the erase time is only increased by 128% compared to the prior art shown in fig. 2B. Therefore, after the flash memory erasing method of the embodiment is applied, the erasing time required for erasing the flash memory in each time is greatly reduced, and after the flash memory erasing method of the embodiment is applied, along with the prolonging of the using time of the flash memory, the time consumption of the whole erasing time of the flash memory compared with the time consumption of erasing the flash memory for the first time is not greatly increased, the erasing efficiency is greatly improved, and therefore the requirement of erasing the flash memory at a high speed can be met.
Referring to fig. 7, based on the same inventive concept, an embodiment of the present invention further provides an erasing system for a flash memory, which is configured to erase the flash memory by blocks in an erase verification manner, that is, the erasing method for the flash memory of the present invention can be implemented. The erase system includes a reset module 10, a first erase verify module 11, a second erase verify module 12, and an erase pulse applying module 13.
The erase pulse applying module 13 is configured to apply corresponding erase pulses to all addresses of the certain block as needed.
The reset module 10 is configured to reset the address of the certain block to the first address before the first erase verification module 11 performs the first erase verification on the certain block based on the first erase verification threshold each time, and before the second erase verification module 12 performs the second erase verification on the certain block based on the second erase verification threshold each time, and the number of reset erase pulses is 0 and the erase bias of the reset erase pulses is the initial erase bias Vint before the first erase verification module 11 performs the first erase verification on the certain block based on the first erase verification threshold. That is, the reset module 10 is configured to implement the reset operation related to the steps S1.1 to S1.3 or the steps S2.1 to S2.3, that is, for the specific working principle of the reset module 10, reference is made to the description related to the steps S1.1 to S1.3 or the steps S2.1 to S2.3, which is not described herein again.
The first erase verification module 11 is configured to perform a first erase verification on the certain block based on a first erase verification threshold after the erase pulse applying module 13 applies an erase pulse having a corresponding erase bias to the certain block, so as to determine whether all the bits of at least one address in the certain block have a reading of not all 0, or whether all the bits of all the addresses in the certain block have a reading of 1. When the first erase verification module 11 determines that all the readings of all the bits of each address in the certain block are all 0 or determines that all the readings of all the bits of at least one address in the certain block are not all 1, the erase pulse applying module 13 is enabled to increase the erase pulseAnd dividing the pulsed erase bias voltage to add a new erase pulse to the certain block, and further performing the erase operation and the first erase verification on the certain block again until the readings of all the bits of any address in the certain block are not all 0 or the readings of all the bits of all the addresses are all 1. That is, the first erase verify module 11 is used to implement the related operations in step S1.2 or step S2.2 under the cooperation of the reset module 10 and the erase pulse applying module 13, and completes the operations based on the first erase verify threshold EVT _1stFor the first erase verification of each block in the flash memory, that is, the specific working principle of the first erase verification module 11, please refer to the above description in step S1.2 or step S2.2, which is not described herein again.
The second erase verification module 12 is configured to perform second erase verification on the certain block based on a second erase verification threshold when the first erase verification module 11 determines that all the readings of all the bits of the certain address in the certain block are not all 0, or perform second erase verification on the certain block based on the second erase verification threshold after the first erase verification module 11 determines that all the readings of all the bits of all the addresses in the certain block are all 1 (that is, all the addresses pass the first erase verification). That is, the second erase verify module 12 is used to implement the related operations in step S1.3 or step S2.3 in the foregoing under the cooperation of the reset module 10 and the erase pulse applying module 13, that is, the specific working principle of the second erase verify module 12 refers to the related description in step S1.3 or step S2.3 in the foregoing, and is not described herein again.
The erase pulse applying module 13 is configured to apply an erase pulse having the initial erase bias to a certain block of the flash memory after the reset module 10 completes the related reset operation before the first erase verify module 11 applies the erase pulse to the certain block, and then increase the count of the erase pulse and/or the erase bias according to the verify result of the first erase verify module 11 and/or the verify result of the second erase verify module 12 to add a new erase pulse to the certain block. That is, the erase pulse applying module 13 is used to implement the related operations of increasing the erase pulse count and increasing the erase bias voltage in the above steps S1.1 to S1.3 or steps S2.1 to S2.3, that is, the specific working principle of the erase pulse applying module 13 please refer to the related description in the above steps S1.1 to S1.3 or steps S2.1 to S2.3, and the detailed description thereof is omitted here.
It is understood that the reset module 10, the first erase verify module 11, the second erase verify module 12 and the erase pulse applying module 13 may be combined in one device, or any one of them may be split into a plurality of devices, or at least part of the functions of one or more of these devices may be combined with at least part of the functions of the other devices and implemented in one device. According to an embodiment of the present invention, at least one of the reset module 10, the first erase verify module 11, the second erase verify module 12 and the erase pulse applying module 13 may be implemented at least in part as a hardware circuit, such as a Field Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a system on a chip, a system on a substrate, a system on a package, an Application Specific Integrated Circuit (ASIC), or may be implemented in hardware or firmware in any other reasonable manner of integrating or packaging a circuit, or in a suitable combination of software, hardware and firmware implementations. Alternatively, at least one of the reset module 10, the first erase verify module 11, the second erase verify module 12 and the erase pulse applying module 13 may be at least partially implemented as a computer program module, which when executed by a computer, may perform the functions of the respective modules.
Based on the same inventive concept, an embodiment of the present invention further provides a computer storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the erasing method and the variations of the flash memory according to the present invention. The computer storage medium may be any medium that can contain, store, communicate, propagate, or transport the instructions. For example, the computer storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the computer storage medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); memory, such as Random Access Memory (RAM), U disk, etc.; and/or wired/wireless communication links.
In summary, according to the technical solution of the present invention, when erasing the flash memory by blocks and erasing a certain block of the flash memory, after applying an erase pulse with an initial erase bias voltage to the certain block, first performing first erase verification on the certain block based on a first erase verification threshold, and determining whether readings of all bits of at least one address in the certain block are not all 0, if so, performing second erase verification on the certain block based on a second erase verification threshold, or determining whether readings of all bits of each address of the certain block are 1 (i.e., whether all addresses pass the first erase verification), if so, performing second erase verification on the certain block based on the second erase verification threshold; and under the condition that the judgment result of the first erase verification is negative, adding an erase pulse in a mode of increasing erase bias voltage to erase all the addresses of a certain block again, and performing the first erase verification on all the addresses of the certain block based on a first erase verification threshold value until the reading of all the bits of each address of the certain block is judged to be 1 or the reading of all the bits of at least one address is not 0 completely, and performing the second erase verification on the certain block based on a second erase verification threshold value, thereby reducing the erase pulse count used by the erase verification of the flash memory as a whole by using the first erase verification, particularly reducing the number of the pulses used in the re-erase after the flash memory passes through multiple (for example, more than 10 ten thousand) erase/write cycles, and greatly shortening the erase time of the flash memory as a whole, the erasing efficiency is improved, the requirement of erasing the flash memory at high speed can be met, and the erasing efficiency can be guaranteed along with the prolonging of the service life of the flash memory.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (11)
1. An erasing method of a flash memory is characterized in that the flash memory is erased by blocks in an erasing verification mode, and the method for erasing a certain block of the flash memory comprises the following steps:
applying an erase pulse to said certain block;
performing first erase verification on the certain block based on a first erase verification threshold to judge whether all the readings of all the bits of at least one address in the certain block are not all 0 or judge whether all the readings of all the bits of all the addresses in the certain block are all 1;
if so, performing second erasure verification on the certain block based on a second erasure verification threshold value;
and if not, increasing the erasing bias voltage of the erasing pulse to add a new erasing pulse to the certain block, and further performing first erasing verification on the certain block based on the first erasing verification threshold value again.
2. The erasing method of a flash memory according to claim 1, wherein before performing a first erase verification for a first time on said certain block based on a first erase verification threshold, an address of said certain block and an erase pulse count are reset to perform the first erase verification for respective addresses of said certain block in order of the addresses of said certain block from the first address of said certain block for the first time in order of the addresses of said certain block based on said first erase verification threshold.
3. The erasing method of a flash memory according to claim 1, wherein at each time of the first erase verification and/or the second erase verification, a value of each address is read out in order from a first address to a last address in an address order of the certain block, and the value is compared with 00 to determine whether all bits of at least one address in the certain block have not read all 0 or is compared with FF to determine whether all bits of all addresses in the certain block have read all 1.
4. The method of claim 2, wherein when it is determined that all the bits of any address in the certain block are not read as 1 in the first erase verification of the current time, the first erase verification of the current time is stopped, and the erase bias of the erase pulse is increased to add a new erase pulse to the certain block, and further, the first erase verification of the next time is performed until all the bits of all the addresses of the certain block are read as 1, it is determined that the certain block passes the first erase verification, and the certain block is subjected to the second erase verification based on the second erase verification threshold.
5. An erasing method of a flash memory according to any one of claims 1 to 4, wherein the step of performing the second erase verification on the certain block based on the second erase verification threshold includes:
resetting the address of the certain block to a first address;
performing second erase verification on each address of the certain block according to the address sequence and based on the second erase verification threshold value to judge whether all the readings of all the bits of all the addresses in the certain block are all 1;
if so, finishing erasing the certain block;
and if not, increasing the erase pulse count and/or increasing the erase bias voltage of the erase pulse to apply a new erase pulse to the certain block, resetting the address of the certain block to the first address, and performing second erase verification on the certain block again based on the second erase verification threshold until the readings of all bits of all addresses in the certain block are all 1.
6. An erasing method of a flash memory according to claim 5, wherein when it is judged that all bits of any one address in said certain block do not have a reading of 1, an erase pulse is newly added by keeping the erase bias of the erase pulse constant and increasing the erase pulse count, and it is determined whether the increased erase pulse count exceeds the maximum erase pulse count, if not, a new one of the erase pulses is applied to all addresses of the certain block to perform a second erase verification again for the certain block based on the second erase verification threshold, and if so, one erase pulse is newly added and applied to all addresses of the certain block by increasing the erase bias of the erase pulse and resetting the erase pulse count, to perform a second erase verification on the block based again on the second erase verification threshold.
7. The method of any of claims 1-4, wherein the first erase verify threshold is lower or higher than the second erase verify threshold when the first erase verify is used to determine whether all bits of at least one address in the block do not have a reading of 0 at all; when the first erase verification is used to determine whether all the readings of all the bits of each address in the certain block are all 1, the first erase verification threshold is higher than the second erase verification threshold.
8. An erase system for a flash memory, the erase system configured to erase the flash memory in blocks using erase verification, the erase system comprising:
an erasing pulse applying module for applying a corresponding erasing pulse to the certain block as required;
the first erasing verification module is used for performing first erasing verification on the certain block based on a first erasing verification threshold value after a corresponding erasing pulse is applied to the certain block so as to judge whether the readings of all bits of at least one address in the certain block are not all 0 or judge whether the readings of all bits of all addresses in the certain block are all 1;
a second erase verification module, configured to perform a second erase verification on the certain block based on a second erase verification threshold when the first erase verification module determines that all of the readings of all of the bits of at least one address in the certain block are not all 0 or all of the readings of all of the bits of all of the addresses in the certain block are all 1;
the erase pulse applying module is further configured to increase an erase bias of an erase pulse to add a new erase pulse to the block when the first erase verification module determines that all of the readings of all bits of all addresses in the block are all 0 or all of the readings of all bits of any address in the block are not all 1, so that the first erase verification module performs first erase verification on the block again based on the first erase verification threshold.
9. The erase system of claim 8, further comprising a reset module for resetting an address of the certain block before the first erase verification module performs first erase verification on the certain block based on the first erase verification threshold each time and before the second erase verification module performs second erase verification on the certain block based on the second erase verification threshold each time, and resetting a number of the erase pulses and an erase bias of the reset erase pulses to an initial erase bias before the first erase verification module performs first erase verification on the certain block based on the first erase verification threshold;
and/or the erasing pulse applying module is further used for increasing the erasing pulse count and/or increasing the erasing bias voltage of the erasing pulse according to the judgment result of the second erasing verification module, and ensuring that the increased erasing pulse count does not exceed the maximum erasing pulse count so as to add a new erasing pulse to a certain block.
10. The erase system of claim 8, wherein the first erase verify threshold is lower or higher than the second erase verify threshold when the first erase verify module is configured to determine whether all bits of at least one address in the block do not have all readings of 0; when the first erase verification module is configured to determine that all the readings of all the bits of each address in the certain block are all 1, the first erase verification threshold is higher than the second erase verification threshold.
11. A computer storage medium on which a computer program is stored, the computer program, when executed by a processor, implementing the method of erasing a flash memory of any one of claims 1 to 7.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010020814A (en) * | 2008-07-08 | 2010-01-28 | Toshiba Corp | Nonvolatile semiconductor storage device and method of erase verifying the same |
| US20110267886A1 (en) * | 1997-05-14 | 2011-11-03 | Kabushiki Kaisha Toshiba | Nonvolatile Semiconductor Memory Device |
| CN103377707A (en) * | 2012-04-30 | 2013-10-30 | 飞思卡尔半导体公司 | Erasing a non-volatile memory (nvm) system having error correction code (ecc) |
| CN103426474A (en) * | 2012-05-16 | 2013-12-04 | 北京兆易创新科技股份有限公司 | Nonvolatile memory erase method and device |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN105575427A (en) * | 2014-10-11 | 2016-05-11 | 北京兆易创新科技股份有限公司 | Erasing method of nonvolatile memory |
| CN111863093A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Erasing method and device of nonvolatile memory |
| CN112927743A (en) * | 2019-12-05 | 2021-06-08 | 北京兆易创新科技股份有限公司 | Erasing verification method and device for storage unit, computer equipment and storage medium |
-
2021
- 2021-06-23 CN CN202110715752.6A patent/CN113360421B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110267886A1 (en) * | 1997-05-14 | 2011-11-03 | Kabushiki Kaisha Toshiba | Nonvolatile Semiconductor Memory Device |
| JP2010020814A (en) * | 2008-07-08 | 2010-01-28 | Toshiba Corp | Nonvolatile semiconductor storage device and method of erase verifying the same |
| CN103377707A (en) * | 2012-04-30 | 2013-10-30 | 飞思卡尔半导体公司 | Erasing a non-volatile memory (nvm) system having error correction code (ecc) |
| CN103426474A (en) * | 2012-05-16 | 2013-12-04 | 北京兆易创新科技股份有限公司 | Nonvolatile memory erase method and device |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN105575427A (en) * | 2014-10-11 | 2016-05-11 | 北京兆易创新科技股份有限公司 | Erasing method of nonvolatile memory |
| CN111863093A (en) * | 2019-04-29 | 2020-10-30 | 北京兆易创新科技股份有限公司 | Erasing method and device of nonvolatile memory |
| CN112927743A (en) * | 2019-12-05 | 2021-06-08 | 北京兆易创新科技股份有限公司 | Erasing verification method and device for storage unit, computer equipment and storage medium |
Non-Patent Citations (1)
| Title |
|---|
| 车明康: "可在系统内重新编程的非易失存储器——闪烁EPROM", 《微电子学与计算机》 * |
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