WO2024032560A1

WO2024032560A1 - Method for over-erase repair, and storage apparatus

Info

Publication number: WO2024032560A1
Application number: PCT/CN2023/111518
Authority: WO
Inventors: 陈纬荣
Original assignee: 东芯半导体股份有限公司
Priority date: 2022-08-11
Filing date: 2023-08-07
Publication date: 2024-02-15
Also published as: CN115295056A

Abstract

Provided in the present application are a method for over-erase repair of a non-volatile memory, a storage apparatus that can execute the method, and a computer-readable medium storing an instruction for executing the method, wherein the non-volatile memory comprises a plurality of storage blocks. The method comprises: a. executing local over-erase repair on a first storage block among a plurality of storage blocks, wherein the local over-erase repair is executed in a word-line-by-word-line manner; b. performing full word-line over-erase verification on storage cells in the plurality of storage blocks; and c, in response to it being determined that an over-erased storage cell is present among storage cells on all word lines, executing local over-erase repair on one of storage blocks on which local over-erase repair has not yet been executed among the plurality of storage blocks.

Description

Method and storage device for over-erasure recovery

Technical field

The present application relates to the field of semiconductor storage technology, and in particular, to a programming method and a storage device for performing erasure repair on a non-volatile memory.

Background technique

As we enter the information age, the requirements for information storage are getting higher and higher, and the requirements for storage devices such as computers are also getting higher and higher. Non-volatile memory, as a storage medium that can be rewritten during use, is widely used in various storage devices. Non-volatile memories such as flash memory, Erasable Programmable Read Only Memory (EPROM: Erasable Programmable Read Only Memory), and Electronically Erasable Programmable Read Only Memory (EEPROM: Electrically Erasable Programmable Read Only Memory) can be The memory cell is erased and then programmed, thereby deleting the previously stored information and recording new information.

However, during the erasing process, over-erasing may occur, causing programming to be affected, directly affecting the normal operation of the memory, and even causing functional errors. Therefore, how to accurately and quickly detect the over-erased phenomenon, thereby preventing the adverse effects caused by the over-erased state and ensuring the normal operation of the memory, has become one of the problems that those skilled in the art need to solve urgently.

In the conventional over-erasure repair process, since it is impossible to determine the number and location of memory cells (cells) that have experienced erasure problems on the same bit line (BL: Bit Line), the size of the leakage cannot be well controlled. . The problem this brings is that if the leakage is too large, it is very likely to exceed the load capacity of the BL's charge pump. Once this happens, the efficiency of over-erasure repair will be affected. In extreme cases, the effect of over-erasure repair will not even be achieved, resulting in functional failure.

In addition, conventional over-erase verification and repair require a relatively low voltage source to bias all word lines, requiring a larger load, which is usually implemented through a voltage regulator, which consumes considerable energy. Consider the chip area.

Contents of the invention

The technical problem to be solved by the invention

The present application was completed in view of the above-mentioned existing problems, and its purpose is to provide a method and a storage device for repairing an erased memory of a non-volatile memory, which can accurately and efficiently repair the erased memory. Unit (ZQ: unified change below).

Technical solutions to technical problems

In one embodiment of the present application that solves the above problem, a method for over-erasure repair of a non-volatile memory is provided. The non-volatile memory includes a plurality of storage blocks. The method include:

a. Perform partial over-erasure repair on the first storage block among the plurality of storage blocks. The partial over-erasure repair is performed in a word line (WL: Word Line) manner and includes: converting the current word line biasing to a first voltage to perform erase verification on the memory cells on the current word line, the first voltage being higher than the voltages of other word lines in the first memory block; and in response to determining that the current word line There are over-erased memory cells on the current word line, and a repair operation is performed on the over-erased memory cells on the current word line;

b. Perform full word line over-erasure verification on the memory cells in the plurality of memory blocks, including: simultaneously biasing all word lines in the plurality of memory blocks to a second voltage to The memory cells on all word lines are erase verified; and

c. In response to determining that there are over-erased memory cells in the memory cells on all word lines, one of the memory blocks in the plurality of memory blocks that has not performed the local over-erasure repair is block performs the local over-erasure repair.

In an embodiment of the present application, steps b and c are repeated until there are no over-erased memory cells in the plurality of memory blocks.

In an embodiment of the present application, the local over-erasure repair further includes: determining the number and location of over-erased memory cells existing on the current word line.

In an embodiment of the present application, the over-erasure check includes: determining whether the threshold voltage of the memory cell on the current word line is lower than a bottom voltage, the bottom voltage being the threshold voltage of the erased memory cell. The minimum value of the expected threshold voltage distribution.

In an embodiment of the present application, during the execution of local over-erasure repair, the voltage of the other word lines is biased to a negative voltage.

In an embodiment of the present application, the second voltage is 0V.

In one embodiment of the present application to solve the above problem, a memory device is provided, including: a plurality of memory blocks, each memory block including an array of memory cells and a plurality of word lines, the plurality of word lines Each of them is coupled to a row of memory cells in the array of memory cells; a controller configured to perform the method as described in any one of the above embodiments to control the plurality of memory cells. The storage block has been erased and repaired.

In one embodiment of the present application that solves the above problem, a non-transitory computer-readable storage medium is provided, with instructions stored thereon. When executed by a processor, the instructions cause the processor to execute the above-mentioned steps. The method described in any of the embodiments.

Invention effect

According to the present application, erased memory cells can be repaired accurately and efficiently.

Description of drawings

In order that the present application may be understood in detail, a more particular description of the application briefly summarized above may be derived by reference to the embodiments, some of which are illustrated in the accompanying drawings, and to facilitate understanding the same reference numerals have been used wherever possible. to indicate the same elements common to each diagram. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this application and are therefore not to be considered limiting of its scope, for the application may admit to other equally effective embodiments, in which:

FIG. 1 is a schematic diagram illustrating the voltage distribution of erased and programmed memory cells under normal conditions related to the present application.

2 is a schematic diagram illustrating the voltage distribution of erased and programmed memory cells in the presence of an over-erasing phenomenon involved in the present application.

FIG. 3 is a schematic diagram showing a memory cell in a case where an over-erasure phenomenon occurs in a nonvolatile memory.

Figure 4 is a diagram illustrating over-erasure repair of a non-volatile memory according to an embodiment of the present application. A flowchart of an example of the method.

FIG. 5 is a flowchart illustrating another example of a method for over-erasure repairing a non-volatile memory according to an embodiment of the present application.

FIG. 6 is a schematic block diagram illustrating a storage device according to an embodiment of the present application.

It is contemplated that elements of one embodiment of the present application may be advantageously applied to other embodiments without redundancy.

Detailed ways

Specific examples are described below, and those skilled in the art can clearly understand other advantages and technical effects of the present application from the content disclosed in this specification. In addition, the present application is not limited to the following specific embodiments, and can also be implemented or applied through other different embodiments. Moreover, for each specific content in this specification, various modifications can be made without departing from the spirit of the present application. Modifications and Changes.

This application uses specific words to describe embodiments of the application. For example, "one embodiment", "other embodiments", and/or "some embodiments" means a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that “one embodiment” or “other embodiments” or “some embodiments” mentioned two or more times at different places in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of the present application may be appropriately combined.

It should be noted that, in order to simplify the presentation of the disclosure of the present application and thereby facilitate the understanding of one or more embodiments, in the following description of the embodiments of the present application, various features are sometimes combined into one embodiment, drawing or in its description. However, this method of disclosure does not imply that the subject matter of the application requires more features than are mentioned in the claims. Indeed, embodiments may have less than all features of a single embodiment disclosed below.

Below, specific embodiments of the present application will be described in detail based on the accompanying drawings. The enumerated drawings are for simple illustration only and are not drawn according to actual dimensions. They do not reflect the actual dimensions of the relevant structures, and are explained in advance. To facilitate understanding, the same reference numbers are used in the various drawings to indicate the same elements common to the drawings. The drawings are not to scale and may be simplified for clarity. one Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

Hereinafter, with reference to FIGS. 1 to 3 , the formation principle and influence of the over-erasing phenomenon involved in the present application will be briefly described.

For non-volatile memories such as NOR flash memory, when the erase operation and write operation of the non-volatile memory are completed, the threshold voltage of the erased memory cell of the non-volatile memory is usually ( VT (Threshold Voltage) is generally distributed between 1V and 4V, while memory cells undergoing write operations are generally distributed between 7V and 9V, as shown in Figure 1. Under normal circumstances, the minimum value of VT of an erased memory cell is 1V. When these memory cells are unselected (when the word line voltage is 0), the gate-source voltage (VGS) of the memory cell of the non-volatile memory: The difference between Gate-Source Voltage) and VT is -1V, that is, VGS-VT=-1V, so the memory cell will not leak electricity. It should be noted that the voltage V1 in Figure 1 (corresponding to the maximum value of the threshold voltage distribution of the erased memory cell, such as 1V) can be used as the bottom voltage (that is, the minimum value of the expected threshold voltage distribution of the erased memory cell). ) is used for over-erasure verification (also called bottom voltage verification). The voltage V2 in Figure 1 (corresponding to the maximum value of the threshold voltage distribution of the erased memory cell, such as 4V) can be used to verify storage Whether the cell has completed erasing, as will be explained further below.

However, due to the influence of various factors such as inconsistency of the memory cells of the non-volatile memory, erasure and write operation cycles, and erase operation control, the voltage of the memory cells after the erase operation is less than 0V. Erasing occurs frequently, not only on the currently erased memory cell, but may also affect memory cells in other areas of the shared substrate, causing VT to drop to near 0V. As shown in Figure 2, when the over-erasing phenomenon is serious and the VT is lower or there are more memory cells with over-erasing, there is a large leakage on the leaked bit lines, even if these memory cells are unselected. , will also have a negative impact on the storage unit selected to perform normal operations, and even functional errors may occur.

As shown in Figure 3, for example, WL1/BL0 is a memory cell that is being operated. Due to power outage or other uncontrollable factors during the erasing process, the memory cell on WL1/BL0 may leak electricity. If the VT of other unselected memory cells (WL=0) located on BL0 at this time is <0 and the number is large, these memory cells will also produce large leakage on BL0 and will have the following serious effects:

1. Due to the influence of leakage on BL during read/verify operation, the VT of the read operation or verify operation will be lower than the VT of the actually selected memory cell; and/or

2. The write operation will cause the writing efficiency of the current generated by the charge pump to seriously decrease due to these leakages (assuming that the charge pump output BL current is constant), and may even fail.

An example of the method for performing over-erasure repair on a non-volatile memory involved in this application is shown in FIG. 4 .

Example method 400 may begin at step 401 . At step 401, a local over-erasure repair may be performed on a first memory block among a plurality of memory blocks included in the non-volatile memory. This local over-erasure repair may be performed on a word line-by-word line basis and may include: 1) biasing the current word line to a first voltage to perform over-erase verification on the memory cells on the current word line, where the first voltage may Higher than the voltage of other word lines in the first memory block (as a non-limiting example, the first voltage may be 3V, 5V, 10V, etc., while the voltages of other word lines may be 0V, -1V, -3V, etc.); and 2) in response to determining that an over-erased memory cell exists on the current word line, performing a repair operation on the over-erased memory cell on the current word line. The first memory block may be a non-volatile memory

Optionally, local over-erasure repair may also include: determining the number and location of over-erased memory cells present on the current word line. Thereby, information about the number and location of over-erased units can be provided to an internal processor or an external processor, and in turn provided to a user (for example, by transmitting the information to the user via a transmission device or displaying the information to the user via a display device). the information, etc.) or the computer device (for example, sending the information to the computer device wiredly or wirelessly for the computer device to respond based on the information, etc.).

As a non-limiting example of over-erase verification, over-erase verification may include determining whether the threshold voltage of the memory cell on the current word line is lower than a floor voltage that is the expected threshold of the erased memory cell. The minimum value of the voltage distribution. If it is determined that the threshold voltage of the memory cell on the current word line is lower than the bottom voltage, it can be determined that the memory cell is in an over-erased state.

As an example of a specific operation, for example, since the memory cell can be regarded as equivalent to NMOS (N-Metal-Oxide-Semiconductor; N-type metal-oxide-semiconductor), a certain voltage is applied to the word line, that is, the gate electrode In the case of voltage (VG: Gate Voltage), this voltage and the VT of the memory cell can generate a certain amount of current (for example, when VG>VT, the voltage The following current may be generated: I _{memory cell} = K × (VG-VT) ^2. From this equation, it can be seen that the current value of the memory cell is directly determined by the value of VG-VT, and K is a relatively large value. , so it can be roughly understood that if VG is slightly larger than VT, there will be current, then VG can be equivalent to VT of the memory cell). The current of the memory cell can be compared with the reference current (the reference current can be a preset constant current). When the I _{memory cell} is greater than this specific value, it means that the VT is too small, otherwise it means that the VT is too large. Therefore, the word line voltage can be used to control the I _{memory cell} and then compared with the reference current to determine the size of the VT of the memory cell. As a more specific example, for example, in the case where the memory cell defined as having an over-erasure phenomenon is a memory cell with VT<0V, if the selected word line is biased to 0V (VG=0), then the I _{memory cell} =K(0-VT) ² , which must be greater than 0, and if the I _{_memory cell} is greater than the set reference current, the memory cell can be considered to be in an over-erased state.

Optionally, the voltages of other word lines (ie, unselected word lines) may be biased to a negative voltage during execution of local over-erase repair. As a result, VGS<<0 can be achieved and the impact of leakage caused by over-erasing can be avoided.

At step 402, a full word line over-erase check may be performed on memory cells in a plurality of memory blocks of the non-volatile memory. The full word line over-erasure verification may include: simultaneously biasing all word lines in the plurality of memory blocks to the second voltage to perform over-erasure verification on the memory cells on all word lines. Through full word line over-erasure verification, it can be checked whether there are other memory cells besides the first memory block (for example, in other memory blocks sharing the same substrate as the first memory block) that are affected by this erasure operation. Enter the over-erased state (at this time, there are no over-erased memory cells in the first memory block). As an example of a preferred embodiment, the second voltage may be 0V. However, it is not limited thereto, and the second voltage may also be other values, such as a value lower than the bottom voltage value of the erased memory cell.

At step 403, in response to determining that there are over-erased memory cells in the memory cells on all word lines, performing local over-erasure repair on one of the memory blocks in the plurality of memory blocks that has not been performed. Partial over erasure repair.

Optionally, steps 402 and 403 may be repeated until there are no over-erased storage units in the multiple storage blocks. As a result, the memory can be repaired accurately and efficiently through erasure.

Another specific non-limiting example of a method for over-erasure repair of a non-volatile memory including a plurality of memory blocks is shown in FIG. 5 .

Method 500 may begin at step 501 . At step 501, block erasure verification may be performed on a first storage block among a plurality of storage blocks. As an example, referring back to FIG. 1 , the block erase check may be to check whether there is a certain margin between the maximum value of the voltage distribution of the erased memory cell (eg, voltage V2 in FIG. 1 ) and the read voltage (eg, , the erase margin (erase margin) shown in Figure 1) to ensure that the read operation will not be error-free. As a specific example, for example, when an erasure operation is completed, there is a memory cell A on a word line whose VT is slightly smaller than 4V, and there is another memory cell B whose VT is slightly larger than 4V. At this time, when this Applying 4V to the word line for verification, then the I _{memory cell} of memory cell A is greater than the reference current. It can be seen that the VT of memory cell A has been lower than 4V and has reached the specified voltage range area. There is no need to erase it, and the memory cell The I _{memory cell} of B is less than the reference current. It can be seen that the VT of memory cell B is greater than 4V and needs to continue to be erased. When the block erasure verification is successful (ie passes the verification), the method 500 may proceed to step 505 described below. When the block erasure check fails (ie fails the check), the method 500 may proceed to step 502.

At step 502, a block erase operation may be performed to erase the first storage block.

At step 503, erasure verification may be performed on the memory cells on each word line in the first memory block in a word line by word line manner. Specifically, the current word line (eg, the selected word line) may be biased to a first voltage (eg, 5V) higher than the voltages of other word lines in the first memory block to energize the memory cells on the current word line. Erase verification performed. As an example, referring back to Figure 1, the over-erasure check can be to compare the VT minimum value of the memory cell in the first memory block with the bottom voltage (such as the voltage V1 in Figure 1). If the VT minimum value is lower than If the bottom voltage is low, it can be judged that this memory cell has an over-erasure phenomenon. As another example, it may be determined whether there is a certain margin between the VT minimum value of the erased memory cells in the first memory block and 0V. If there is not a certain margin (such as the VT minimum value is less than 0V), It can be determined that this memory unit has been over-erased. When the over-erasure verification is successful (that is, passes the verification) and no over-erased memory cells are detected, the method 500 can return to the aforementioned step 501. When the over-erasure check fails (ie fails the check) and an over-erased memory cell is detected, the method 500 may proceed to step 504 .

At step 504, in response to determining that an over-erased memory cell exists on the selected word line in the first memory block, a repair operation may be performed on the over-erased memory cell on the selected word line to eliminate the error of the word line. Over-erasing of memory cells. When step 504 is completed, method 500 may return Go to the aforementioned step 503 to continue to perform erasure verification on the memory cells on the selected word line or other word lines in the first memory block.

At step 505, a full word line over-erase check may be performed on the memory cells in the plurality of memory blocks. All word lines in multiple memory blocks can be biased to a second voltage (eg, 0V) at the same time to perform erasure verification on memory cells on all word lines in multiple memory blocks. When the full word line over-erasure verification is successful (that is, it passes the verification) and no erased memory cells are detected, it can be shown that the memory cells in the multiple memory blocks being checked are not over-erased. Method 500 Finish. When the full word line erase check fails (ie fails the check) and an over-erased memory cell is detected, the method 500 may proceed to step 506 .

At step 506, in response to determining that there are erased memory cells in the memory cells on all word lines, the memory blocks that have not performed erasure verification in the plurality of memory blocks can be processed in a word line by word line manner. The memory cells on each word line have performed erasure verification. This over-erasure verification process may be similar or identical to the over-erasure verification process as performed in step 503 for the memory cells on each word line within the first memory block. When the over-erasure verification is successful (that is, passes the verification) and no over-erased memory cells are detected, it means that the memory cells in the multiple memory blocks being checked are not over-erased, and the method 500 is completed. When the over-erasure check fails (ie fails the check) and an over-erased memory cell is detected, the method 500 may proceed to step 507 .

At step 507, in response to the presence of an over-erased memory cell on the selected word line of the memory block on which erasure verification was performed at step 506, a repair operation may be performed on the over-erased memory cell on the selected word line. , to eliminate the over-erasing problem of the memory cells of this word line. When step 507 is completed, the method 500 can return to the aforementioned step 506 and continue to perform erasure verification on the selected word line or the memory cells on other word lines.

In some embodiments, the operations included in the methods in the above embodiments may occur simultaneously, substantially simultaneously, or in an order different from that shown in the drawings.

In some embodiments, all or part of the operations included in the methods in the above embodiments can optionally be automatically performed by a program. In one example, the present application may be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program(s) of the program product include the functionality of the embodiments (including the methods described herein). illustrate Computer-readable storage media include, but are not limited to: (i) non-writable storage media (e.g., read-only memory devices within a computer, such as CD-ROM disks, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory) on which information is permanently stored on a non-writable storage medium; and (ii) a writable storage medium (e.g., disk storage or hard drive or any type of solid-state random access semiconductor memory ), storing variable information on the writable storage medium. Such computer-readable storage media, when implementing computer-readable instructions that direct the functionality of the methods described herein, are embodiments of the present application.

An example of a storage device related to this application is shown in FIG. 6 . The exemplary storage device 600 may include a plurality of storage blocks 610-1 to 610-n (n is a natural number greater than or equal to 2) and a controller 620. Each of memory blocks 610-1 through 610-n may include an array of memory cells and a plurality of word lines, each of the plurality of word lines may be coupled to a row of memory cells in the array of memory cells. It should be noted that “a row” does not necessarily refer to a row in the physical sense, but may refer to a collection of memory cells allocated to the same word line address in an array of memory cells. The controller 620 may be configured to perform over-erasure repair on the plurality of storage blocks, for example, through the methods described in the above embodiments and other methods.

According to the present application, by performing over-erasure verification and repair on each word line in the storage block, even if there is an over-erasure phenomenon in the memory cell, it will not be affected because the unselected word line has a negative voltage. , so the number of memory cells that need to be repaired is easy to determine, ensuring the efficiency of repair and preventing charge pump overload.

According to the present application, since the over-erasure verification performed on the first storage block and the over-erasure verification performed on other storage blocks other than the first storage block may be the same or similar operations, only the address The scope is different. Therefore, for control devices (such as state machines), the method is relatively simple, which can make the chip occupy a smaller area.

According to the present application, by biasing all word lines of the plurality of memory blocks to the second voltage, since only the second voltage is required to detect over-erasure, there is no need to use a voltage regulator as in the conventional technology. All word lines are offset to save chip area.

Optional embodiments of the present application are described in detail above. However, it should be understood that without departing from this application Various embodiments and modifications may be adopted within the broad spirit and scope of the invention. Those of ordinary skill in the art can make many modifications and changes based on the concept of the present application without creative efforts. As a non-limiting example, those skilled in the art can omit one or more of the various parts in the above-mentioned system or structure, add one or more parts to the above-mentioned system or structure, or use other ones with the same or Parts with similar functions replace part or all of the various structures or systems involved in this embodiment. Therefore, any technical solutions that can be obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the prior art based on the concepts of this application shall fall within the protection scope determined by the claims of this application.

It should be noted that while the present disclosure includes several embodiments, these embodiments are non-limiting (whether or not they have been marked as exemplary), and there are changes, substitutions and equivalents which fall within the scope of this disclosure. within the scope of the application. Furthermore, the described embodiments should not be construed as mutually exclusive, and rather should be understood as potentially combinable if such combinations are permitted. It should also be noted that there are many alternative ways of implementing embodiments of the disclosure. It is therefore intended that the appended claims be construed to include all such changes, permutations, and equivalents as fall within the true spirit and scope of the disclosure.

Claims

A method for over-erasure repair of a non-volatile memory, the non-volatile memory includes a plurality of storage blocks, the method includes:

a. Perform local over-erasure repair on the first memory block among the plurality of memory blocks, the local over-erasure repair is performed in a word-line manner and includes:

biasing the current word line to a first voltage to perform erase verification on the memory cells on the current word line, the first voltage being higher than the voltages of other word lines in the first memory block; and

In response to determining that an over-erased memory cell exists on the current word line, perform a repair operation on the over-erased memory cell on the current word line;

b. Perform full word line over-erasure verification on the memory cells in the plurality of memory blocks, including: simultaneously biasing all word lines in the plurality of memory blocks to a second voltage to The memory cells on all word lines are erase verified; and

c. In response to determining that there are over-erased memory cells in the memory cells on all word lines, one of the memory blocks in the plurality of memory blocks that has not performed the local over-erasure repair is block performs the local over-erasure repair.
The method of claim 1, wherein steps b and c are repeated until there are no over-erased memory cells in the plurality of memory blocks.
The method of claim 1, wherein the local over-erasure repair further includes: determining the number and location of over-erased memory cells present on the current word line.
The method of claim 1, wherein the over-erasure check includes: determining whether a threshold voltage of a memory cell on the current word line is lower than a bottom voltage, the bottom voltage being an erased memory The minimum value of the cell's expected threshold voltage distribution.
1. The method of claim 1, wherein the voltage of the other word lines is biased to a negative voltage during execution of local over-erase repair.
The method of claim 1, wherein the second voltage is 0V.
A storage device including:

a plurality of memory blocks, each memory block including an array of memory cells and a plurality of word lines, each of the plurality of word lines coupled to a row of memory cells in the array of memory cells;

A controller configured to perform the method according to any one of claims 1 to 6 to perform over-erasure repair on the plurality of storage blocks.
A non-transitory computer-readable storage medium having instructions stored thereon that, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 6.