CN115295058B - Method, device, equipment and medium for erasing whole chip of nor flash - Google Patents
Method, device, equipment and medium for erasing whole chip of nor flash Download PDFInfo
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- CN115295058B CN115295058B CN202211229126.7A CN202211229126A CN115295058B CN 115295058 B CN115295058 B CN 115295058B CN 202211229126 A CN202211229126 A CN 202211229126A CN 115295058 B CN115295058 B CN 115295058B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to the technical field of memories, and particularly discloses a method, a device, equipment and a medium for erasing a whole nor flash, wherein the method for erasing the whole nor flash comprises the following steps: s1, pre-programming a whole area to be erased; s2, carrying out coarse erasing operation on the whole area by using an array erasing mode; s3, performing fine erasing operation on the whole area based on a block erasing mode or a sector erasing mode; the method for erasing the whole chip of the nor flash integrates the advantages of high coarse erasing efficiency of an array erasing mode, good fine erasing convergence effect and high convergence speed of a block erasing mode or a sector erasing mode to erase the whole chip area of the nor flash, thereby saving the time required by erasing the whole chip area, improving the erasing success rate, and being particularly suitable for the nor flash with larger erasing performance difference caused by the use degree or the process of different storage areas.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, an apparatus, a device, and a medium for erasing a non flash.
Background
The chip erase adopted by the nor flash is generally divided into two types, one is to adopt array erase in the whole erase process, and the other is to adopt Block by Block erase to gradually erase the whole area.
For a large-capacity nor flash, if a gradual block erase mode is used for erasing, thousands of blocks (e.g., 2048 64-kbyte blocks in a 1G-bit-capacity nor flash) in the nor flash need to be erased one by one, and the erase time is the cumulative time for all blocks to complete erasing, which results in a large time consumption for the whole full-slice erase.
In addition, the existing array erasing mode is a process of erasing the threshold voltages of all the memory cells in the whole array from high to low, and the whole column is erased simultaneously, so that the array erasing method has the advantage of short erasing time in general; however, as the use times of the nor flash are increased, the difference of the memory cells in the memory array is gradually increased, which mainly shows that the threshold voltages of the memory cells in the whole area are widely distributed, and the array erase needs to repeatedly perform voltage trimming for many times to adjust the threshold voltages of all the memory cells to the voltage range corresponding to the preset erase state, so that the advantage of short erase time is lost, and even the phenomenon of erase failure caused by the fact that the threshold voltages of all the memory cells cannot be adjusted to the voltage range corresponding to the preset erase state is avoided.
In view of the above problems, no effective technical solution exists at present.
Disclosure of Invention
The application aims to provide a method, a device, equipment and a medium for erasing a whole nor flash so as to save the time required by erasing the whole flash area and improve the success rate of erasing.
In a first aspect, the present application provides a full-slice erasing method for a nor flash, which is used for erasing all stored data in the nor flash, and the method includes the following steps:
s1, pre-programming a whole area to be erased;
s2, carrying out coarse erasing operation on the whole area by using an array erasing mode;
and S3, performing fine erasing operation on the whole area based on a block erasing mode or a sector erasing mode.
The method for erasing the whole chip of the nor flash integrates the advantages of high coarse erasing efficiency of an array erasing mode, good fine erasing convergence effect and high convergence speed of a block erasing mode or a sector erasing mode to erase the whole chip area of the nor flash, so that the time required by erasing the whole chip area is saved, the erasing success rate can be improved, and the method is particularly suitable for the nor flash with large erasing performance difference caused by the use degree or the process of different storage areas.
The method for erasing a whole flash of a nor flash includes the following steps:
and performing a coarse erasing operation in the array erasing on the whole area by using the array erasing mode until all the memory cells in the whole area are converted into a non-programming state.
In this example, this step simultaneously applies the operation voltages corresponding to the rough erase operation to all the memory cells in the entire area in the unit of operation of the memory array to simultaneously lower the threshold voltages of all the memory cells until the threshold voltages of all the memory cells are lowered to read "1" based on the read voltage, which is considered that all the memory cells in the entire area are transitioned to the non-programmed state.
In the method for erasing a nor flash memory, the memory cell is determined whether to be in a non-programmed state based on a read voltage of 7V.
The full-slice erasing method of the nor flash, wherein the fine erasing operation comprises one or more of an over-erasing repairing operation, a weak programming operation and a fine erasing operation.
The method for erasing the whole nor flash comprises the step of selectively enabling the over-erasing repair operation, the weak programming operation and the refined erasing operation based on a verification result, wherein the verification result is generated according to an operation unit corresponding to a verification voltage verification block erasing mode or a sector erasing mode.
The method for erasing a whole flash of a nor flash includes the following steps:
and performing the fine erasing operation on the whole area step by step based on the block erasing mode or the sector erasing mode until the threshold voltages of all the storage units in the whole area are within 2V-5.5V.
The method for erasing the whole flash of the nor flash comprises the following steps that when the using times of the nor flash are larger than the preset times, the sector erasing mode is selected in the step S3 to carry out the fine erasing operation on the whole area; and when the using times of the nor flash is less than or equal to the preset times, the step S3 selects the block erasing mode to perform the fine erasing operation on the whole area.
In a second aspect, the present application further provides a full-slice erasing apparatus for a nor flash, configured to erase all storage data in the nor flash, where the apparatus includes:
the pre-programming module is used for pre-programming the whole area to be erased;
the rough erasing operation module is used for carrying out rough erasing operation on the whole area by utilizing an array erasing mode;
and the fine erasing operation module is used for performing fine erasing operation on the whole area based on a block erasing mode or a sector erasing mode.
The device integrates the advantages of high coarse erasing efficiency of the array erasing mode, good convergence effect of fine erasing of the block erasing mode or the sector erasing mode and high convergence speed to erase the whole area of the nor flash, thereby saving the time required by erasing the whole area, improving the erasing success rate, and being particularly suitable for the nor flash with larger erasing performance difference caused by the use degree or the process of different storage areas.
In a third aspect, the present application further provides an electronic device, comprising a processor and a memory, where the memory stores computer readable instructions, and the computer readable instructions, when executed by the processor, perform the steps of the method as provided in the first aspect.
In a fourth aspect, the present application also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method as provided in the first aspect.
From the above, the present application provides a method, an apparatus, a device, and a medium for erasing a whole slice of a nor flash, where the method integrates the advantages of a coarse erase efficiency in an array erase mode, a good convergence effect and a fast convergence speed in a fine erase in a block erase mode or a sector erase mode to erase a whole slice region of the nor flash, so as to save the time required for erasing the whole slice region and improve the success rate of erase, and is particularly suitable for a nor flash with a large difference in erase performance due to the use degree or the process of different storage regions.
Drawings
Fig. 1 is a flowchart of a full-slice erase method for a nor flash according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a full-chip erasing apparatus for nor flash according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 201. a pre-programmed module; 202. a rough erasing operation module; 203. a fine erase operation module; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
In a first aspect, referring to fig. 1, some embodiments of the present application provide a method for erasing all stored data in a nor flash, where the method includes the following steps:
s1, pre-programming a whole area to be erased;
s2, carrying out coarse erasing operation on the whole area by using an array erasing mode;
and S3, performing fine erasing operation on the whole area based on the block erasing mode or the sector erasing mode.
Specifically, in order to avoid generating a large number of over-erased units in an erased object after performing the erasing operation, the method for erasing a whole flash in the whole area of the application adjusts all the memory cells in the whole area to be in a programmed state by using step S1 before performing the erasing operation, that is, the stored data of all the memory cells is "0"; it should be understood that if the storage data of all the memory cells in the full slice area is "0" (which would not normally occur), step S1 may be skipped.
More specifically, the nor flash is built in with a plurality of erase modes, and as the name implies, the array erase mode is used to enable an array erase operation, that is, to perform an erase process with a memory array as an operation unit; the block erase mode is used to enable a block erase operation, i.e., an erase process is performed with a block as an operation unit; the sector erase mode is for enabling a sector erase operation, i.e., an erase process with a sector as an operation unit.
More specifically, in the embodiment of the present application, the erase operation is a multi-instruction operation that adjusts the threshold voltages of all memory cells in the corresponding memory region to the target range, and is not limited to the operation behavior of applying the erase voltage to lower the threshold voltages of the memory cells, such as including the rough erase operation and the fine erase operation.
More specifically, the rough erase operation is an operation of simultaneously erasing all memory cells in the storage region based on a set erase voltage, and is used for rapidly adjusting the threshold voltages of all memory cells in the storage region to be below the set voltage, such as erasing to a non-programmed state (all shown as "1" in general), regardless of whether the threshold voltages of the memory cells are converged in a voltage range corresponding to a preset erase state; therefore, step S2 can rapidly erase and lower the threshold voltages of all the memory cells in the entire area to be below the set voltage, i.e. in the vicinity of the voltage range corresponding to the preset erase state.
More specifically, after the step S2 is finished, the distribution of the threshold voltages of the memory cells in different sectors or different blocks in the whole area are different, and for the nor flash with a long service time, the distribution of the threshold voltages of the memory cells in different sectors or different blocks is more different, if the array erase mode is continuously adopted to perform the fine erase on all the memory cells in the whole area just after the rough erase so as to adjust the threshold voltages of the memory cells to converge to the voltage range corresponding to the preset erase state, the threshold voltages of all the memory cells need to be adjusted repeatedly, when the memory cells with low threshold voltages are adjusted upwards, the threshold voltages of the memory cells with high threshold voltages are adjusted to be higher, multiple times of loop operation are needed to complete the whole fine erase process, and the time of the whole erase operation is prolonged seriously; furthermore, if the threshold voltage distribution of the memory cells in different sectors or different blocks is too different, the precise erase in the array erase cannot adjust the threshold voltages of all the memory cells in the entire area to the voltage range corresponding to the preset erase state, which may cause erase failure. Therefore, in the method for erasing a full flash memory according to the embodiment of the present application, the process of performing the precise erasing on the full area is executed in the block erasing mode or the sector erasing mode, so that the influence of the distribution condition difference of the threshold voltages of the memory cells of different sectors or different blocks on the precise erasing can be effectively avoided, and for the same sector or the same block, the threshold voltages of all the memory cells in the same sector or the same block can be rapidly adjusted to the voltage range corresponding to the preset erasing state by using the precise erasing in the corresponding erasing mode.
The method for erasing the whole flash of the nor flash in the embodiment of the application combines two erasing modes (combination of an array erasing mode and a block erasing mode or combination of the array erasing mode and a sector erasing mode) to erase the whole area, wherein the step S2 is equivalent to shielding a fine erasing process in the original array erasing mode, and the step S3 is equivalent to shielding a coarse erasing process in the original block erasing mode or the sector erasing mode; the method for erasing the whole chip of the nor flash integrates the advantages of high rough erasing efficiency of an array erasing mode, good fine erasing convergence effect and high convergence speed of a block erasing mode or a sector erasing mode to erase the whole chip area of the nor flash, so that the time required by erasing the whole chip area is saved, the erasing success rate can be improved, and the method is particularly suitable for the nor flash with large erasing performance difference caused by the use degree or the process of different storage areas.
In some preferred embodiments, the step of performing a rough erase operation on the full sector using the array erase mode includes:
and S21, performing coarse erasing operation in array erasing on the whole area by using the array erasing mode until all the memory cells in the whole area are converted into a non-programming state.
Specifically, for a general nor flash, a programming operation is performed to program the threshold voltage of the memory cell to about 9V or more, where the data of the memory cell read based on the read voltage is "0", i.e., the programmed state, and step S21 is performed to simultaneously apply the operation voltage corresponding to the rough erase operation to all the memory cells in the entire area by using the memory array as the operation unit to simultaneously lower the threshold voltages of all the memory cells until the threshold voltages of all the memory cells are lowered to "1" read based on the read voltage, which means that all the memory cells in the entire area are converted into the non-programmed state.
In some preferred embodiments, the memory cell determines whether it is transitioned to the non-programmed state based on a read voltage of 6V-8V.
Specifically, as can be seen from the foregoing, the storage data of the memory cell is determined based on the read voltage and its own threshold voltage, and therefore, the magnitude of the read voltage determines the timing of ending the rough erase operation; for the nor flash, the threshold voltage of the memory cell in the programmed state is generally around 9V, and the threshold voltage of the memory cell in the erased state is generally below 5V, so the whole-slice erase method of the nor flash in the embodiment of the present application preferably sets the read voltage to be within 6V-8V between 5V and 9V to ensure that all the memory cells in the whole-slice region can be out of the programmed state after performing step S2.
In some preferred embodiments, the memory cell determines whether it is transitioned to a non-programmed state based on a read voltage of 7V.
Specifically, the read voltage with the intermediate boundary of 7V and 9V is generally set between 5.5V and 7V, so that the application preferably adopts the read voltage of 7V to judge whether the memory cell is converted into a non-programming state, and meets the use requirement of the nor flash.
More specifically, in actual operation, the read voltage may be set closer to 5V, that is, the threshold voltages of more memory cells fall below the upper boundary of the voltage range corresponding to the preset erase state, but as the difference of the memory cells in the full slice region is larger, the lower the read voltage is set, the threshold voltages of more memory cells fall below the lower boundary of the voltage range corresponding to the preset erase state, and more memory cells may also generate an over-erase phenomenon, so that more time is consumed to perform over-erase repair on the memory cells in the fine erase operation process, and the time duration of the whole full slice erase is increased, so the read voltage of the full slice erase method of nor flash in the embodiment of the present application is preferably 7V.
In some preferred embodiments, the fine erase operation includes one or more of an over-erase repair operation, a weak program operation, and a fine erase operation.
Specifically, the over-erase repair operation, the weak program operation, and the fine erase operation are commonly used operation commands for fine erase, and can be selectively activated according to the specific conditions of the memory cells in the corresponding block or sector.
More specifically, the over-erase repair operation, the weak programming operation and the refined erase operation are generally performed in sequence and cyclically to gradually adjust the threshold voltages of all the memory cells in the corresponding block or sector until the threshold voltages of all the memory cells in the corresponding block or sector converge to the voltage range corresponding to the preset erase state.
In some preferred embodiments, the over-erase repair operation, the weak program operation and the fine erase operation are selectively enabled based on a verification result generated according to an operation unit corresponding to the verification voltage verification block erase mode or the verification voltage verification sector erase mode.
Specifically, in the process of performing the fine erase operation, the method for full-chip erase of nor flash according to the embodiment of the present application performs data verification on the corresponding block or sector based on the verification voltage after performing the operation command in the fine erase operation on the corresponding block or sector, so as to obtain the verification result, and obtain the threshold voltages of the memory cells in the corresponding block or sector based on the verification result, so as to determine whether the operation command in the next fine erase operation needs to be performed, so as to ensure that the threshold voltages of all the memory cells in the corresponding block or sector are adjusted to converge to the voltage range corresponding to the preset erase state, so that the threshold voltages of all the memory cells in the full-chip region are adjusted to converge to the voltage range corresponding to the preset erase state.
In some preferred embodiments, the step of performing a fine erase operation on the full sector based on the block erase mode or the sector erase mode includes:
and performing fine erasing operation on the whole area step by step based on the block erasing mode or the sector erasing mode until the threshold voltage of all the memory cells in the whole area is within 2V-5.5V.
Specifically, compared with the conventional full-slice erase method, the full-slice erase method of the nor flash in the embodiment of the present application performs the fine erase operation by using the block erase mode or the sector storage mode, and can adjust the threshold voltage of each part of the memory cells in the full-slice region to a better erase state range, and 2V to 5.5V can be considered as an ideal erase condition, so that the full-slice erase method of the nor flash in the embodiment of the present application sets 2V to 5.5V as an index of the threshold voltage of the final erase success, thereby achieving a good full-slice erase effect.
More specifically, the voltage range of 2V-5.5V is the voltage range corresponding to the predetermined erase state.
In some preferred embodiments, when the number of times of use of the nor flash is greater than a preset number of times, the step S3 selects a sector erase mode to perform a fine erase operation on the entire area; and when the using times of the nor flash are less than or equal to the preset times, the step S3 selects a block erasing mode to perform fine erasing operation on the whole area.
Specifically, for a nor flash, the longer the number of times of use or the time of use, the greater the difference between the memory cells therein (which means that the memory cells with the greater number of times of erase are harder to erase and easier to program), and the greater the difference between the memory cells in different regions (mainly because multiple programming and erasing operations are performed on a part of blocks or sectors intensively), so as to increase the number of times of use of the nor flash, the greater the difference between the memory cells at different positions in the whole block region, which is also reflected on different levels, for example, as the number of times of use increases, the difference between the memory cells in different sectors in the same block also gradually increases, and when the difference between blocks is too large, the fine erasing operation performed only in the block mode in step S3 may also cause an erasing failure, and therefore, the whole-block erasing mode of the whole-flash erasing method of the embodiment of the present application is adopted to perform the fine erasing operation on the whole block region, thereby further ensuring that the nor flash can complete the entire-flash in the whole life cycle smoothly and efficiently.
More specifically, the preset number may be set based on a user setting or based on a percentage of a lifecycle (total number of rewritable operations) of the nor flash, and in the embodiment of the present application, since the lifecycle of the nor flash is generally more than one hundred thousand times, the preset number is preferably 80000 times representing the end of the lifecycle.
In other embodiments, in step S3, after step S2 is completed, whether the block erase mode or the sector erase mode is enabled for the fine erase operation is selected based on the number or ratio of over-erased memory cells in the full sector area.
Specifically, after the step S2 is completed under the same condition, the larger the number of over-erased memory cells is, the larger the difference between the memory cells in different regions in the full-slice region is, so that the full-slice erasing method of the nor flash in the embodiment of the present application can start the sector erasing mode to perform the fine erasing operation when the number or the ratio of the over-erased memory cells is larger than the preset number or ratio, so as to ensure that the nor flash can smoothly and efficiently complete the full-slice erasing operation.
In a second aspect, referring to fig. 2, some embodiments of the present application further provide a full-slice erasing apparatus for a nor flash, configured to erase all stored data in the nor flash, where the apparatus includes:
a pre-programming module 201, configured to pre-program a whole area to be erased;
a rough erase operation module 202, configured to perform a rough erase operation on a full area by using an array erase mode;
and the fine erasing operation module 203 is used for performing fine erasing operation on the whole area based on the block erasing mode or the sector erasing mode.
The device of the embodiment of the application integrates the advantages of high coarse erasing efficiency of the array erasing mode, good fine erasing convergence effect and high convergence speed of the block erasing mode or the sector erasing mode to erase the whole area of the nor flash, thereby saving the time required by erasing the whole area, improving the erasing success rate, and being particularly suitable for the nor flash with larger erasing performance difference caused by the use degree or the process of different storage areas.
In some preferred embodiments, the full-slice erase device for a nor flash according to the embodiments of the present application is configured to perform the full-slice erase method for a nor flash provided in the first aspect.
In a third aspect, referring to fig. 3, some embodiments of the present application further provide a schematic structural diagram of an electronic device, where the present application provides an electronic device, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the electronic device is running to perform the method in any of the alternative implementations of the embodiments described above.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the method in any optional implementation manner of the foregoing embodiments. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, the embodiments of the present application provide a method, an apparatus, a device, and a medium for erasing a whole slice of a nor flash, where the method for erasing a whole slice of a nor flash in the embodiments of the present application integrates advantages of a coarse erase efficiency of an array erase mode, a good convergence effect of a fine erase of a block erase mode or a sector erase mode, and a fast convergence speed to erase a whole slice region of a nor flash, so as to save time required for erasing a whole slice region, and improve an erase success rate, and is particularly suitable for a nor flash with a large difference in erase performance due to a use degree or a process in different storage regions.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. A full-slice erasing method of a nor flash is used for erasing all stored data in the nor flash, and is characterized by comprising the following steps:
s1, pre-programming a whole area to be erased;
s2, carrying out coarse erasing operation on the whole area by using an array erasing mode, wherein the coarse erasing operation is an operation of simultaneously erasing all memory cells in the memory area based on a set erasing voltage and is used for quickly reducing the threshold voltage of all the memory cells in the memory area to be below the set voltage;
s3, performing fine erasing operation on the whole area based on a block erasing mode or a sector erasing mode; the fine erase operation includes one or more of an over-erase repair operation, a weak program operation, and a refined erase operation.
2. The method of claim 1, wherein the step of performing the rough erase operation on the full slice region by using the array erase mode comprises:
and performing a coarse erasing operation in the array erasing on the whole area by using the array erasing mode until all the memory cells in the whole area are converted into a non-programming state.
3. The full slice erase method of a nor flash of claim 2, wherein the memory cell determines whether it is transited to a non-programmed state based on a read voltage of 7V.
4. The method of claim 1, wherein the over-erase repair operation, the weak program operation, and the fine erase operation are selectively enabled based on a verification result generated according to an operation unit corresponding to a verify voltage verify block erase mode or a sector erase mode.
5. The method of claim 1, wherein the step of performing the fine erase operation on the full slice area based on the block erase mode or the sector erase mode comprises:
and gradually performing the fine erasing operation on the whole area based on the block erasing mode or the sector erasing mode until the threshold voltages of all the storage units in the whole area are within 2V-5.5V.
6. The method for erasing a whole of a nor flash of claim 1, wherein when the number of times of using the nor flash is greater than a preset number of times, the step S3 selects the sector erase mode to perform the fine erase operation on the whole area; and when the using times of the nor flash is less than or equal to the preset times, the step S3 selects the block erasing mode to perform the fine erasing operation on the whole area.
7. A full-slice erasing apparatus for a nor flash, which is used for erasing all stored data in the nor flash, the apparatus comprising:
the pre-programming module is used for pre-programming the whole area to be erased;
the rough erasing operation module is used for carrying out rough erasing operation on the whole area by utilizing an array erasing mode, wherein the rough erasing operation is an operation of simultaneously erasing all memory cells in the memory area based on a set erasing voltage and is used for quickly reducing the threshold voltage of all the memory cells in the memory area to be below the set voltage;
the fine erasing operation module is used for performing fine erasing operation on the whole area based on a block erasing mode or a sector erasing mode; the fine erase operation includes one or more of an over-erase repair operation, a weak program operation, and a refined erase operation.
8. An electronic device comprising a processor and a memory, said memory storing computer readable instructions which, when executed by said processor, perform the steps of the method according to any one of claims 1 to 6.
9. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the method according to any of claims 1-6.
Priority Applications (1)
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| US5424991A (en) * | 1993-04-01 | 1995-06-13 | Cypress Semiconductor Corporation | Floating gate nonvolatile memory with uniformly erased threshold voltage |
| US6967873B2 (en) * | 2003-10-02 | 2005-11-22 | Advanced Micro Devices, Inc. | Memory device and method using positive gate stress to recover overerased cell |
| US8797802B2 (en) * | 2012-03-15 | 2014-08-05 | Macronix International Co., Ltd. | Method and apparatus for shortened erase operation |
| US8891312B2 (en) * | 2012-04-23 | 2014-11-18 | Macronix International Co., Ltd. | Method and apparatus for reducing erase time of memory by using partial pre-programming |
| CN111785315B (en) * | 2020-06-29 | 2021-03-23 | 深圳市芯天下技术有限公司 | Method, system, storage medium and terminal for reducing erasing interference and erasing time |
| CN112000290B (en) * | 2020-08-21 | 2023-11-24 | 珠海创飞芯科技有限公司 | Nor flash erasure interference correction method and device |
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