CN113409853B - Method, device, storage medium and terminal for reducing probability of reading error after power failure - Google Patents
Method, device, storage medium and terminal for reducing probability of reading error after power failure Download PDFInfo
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- CN113409853B CN113409853B CN202110558998.7A CN202110558998A CN113409853B CN 113409853 B CN113409853 B CN 113409853B CN 202110558998 A CN202110558998 A CN 202110558998A CN 113409853 B CN113409853 B CN 113409853B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
- G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method, a device, a storage medium and a terminal for reducing the probability of error reading after power failure, wherein during the execution of erasing operation of a chip, if abnormal power failure occurs, the power failure interruption protection is automatically started in the chip, the erasing operation of the chip is ended, and over-erasing repair is executed on a storage unit in the chip according to the erasing instruction information; if the power is quickly lost, the over-erasure repair may be performed on a part of memory cells which need to perform the over-erasure repair, and when the power is re-applied, although the problem that the read data is wrong due to over-erasure still exists, because the over-erasure repair is performed on a part of memory cells, the probability of the read data error due to over-erasure is reduced; if the power is slowly turned off, the over-erasure repairing can be performed on all the memory cells in the chip, which need to be performed with the over-erasure repairing, and the problem of data reading errors caused by over-erasure can be avoided when the power is turned on again.
Description
Technical Field
The application relates to the technical field of FLASH, in particular to a method, a device, a storage medium and a terminal for reducing the probability of error reading after power failure.
Background
After the existing NOR FLASH is powered down, the circuit internally judges whether the voltage reaches a low-voltage threshold value, if so, a power-down protection module is started, and an interrupt is sent to an algorithm state machine, and the algorithm state machine responds to the interrupt to discharge a voltage pump and then exits the algorithm. The disadvantage of this is:
during the process of erasing sector a (sector a) in Array a (Array a), if the internal algorithm flow is in the process of erasing (as shown in fig. 1) and is suspended (i.e., branch 2) without the process of repairing the "over-erase" cells, then errors may occur when reading the data of another sector B (sector B) in the same Array a (Array a) after the voltage is restored, the read data is a random value (depending on the number and distribution of the "over-erase" cells in sector a, because the threshold voltage of the "over-erase" cells is generally negative, and when reading the data of sector B, if there is an "over-erase" cell in sector a, 0v cannot turn off the "over-erase" cell, the "over-erase" cell will generate a current, resulting in the error of the read data, as shown in fig. 2).
Accordingly, the prior art is still in need of improvement and development.
Disclosure of Invention
The application aims to provide a method, a device, a storage medium and a terminal for reducing the probability of reading errors after power failure, and aims to solve one or more problems in the prior art.
The technical scheme of the application is as follows: the technical scheme provides a method for reducing the probability of error reading after power failure, which specifically comprises the following steps:
receiving erasure instruction information;
executing erasing operation on a memory unit in the chip according to the erasing instruction information;
judging whether the chip is abnormally powered down or not,
if not, the current operation state of the chip is not changed;
if yes, the power-off interrupt protection is started,
and ending the erasing operation of the chip according to the power-off interrupt protection, and executing over-erasing repair on the memory unit in the chip according to the erasing instruction information.
Further, the specific process of judging whether the chip is abnormally powered down is as follows: it is determined whether a voltage applied to a memory cell within the chip drops to a preset threshold.
Further, the abnormal power down includes a fast power down and a slow power down.
Further, when the abnormal power failure is slow power failure, the erasing operation of the chip is finished according to the power-off interruption protection, and the over-erasing repair is executed on the memory cells in the chip according to the erasing instruction information, and the following process is further included:
s7: judging whether all the memory units which need to execute the over-erasure repairing in the chip have executed the over-erasure repairing, if so, jumping to S8, otherwise jumping to S9;
s8: reducing the voltage applied to the memory cells in the chip to 0 and exiting the over-erase repair process;
s9: and executing over-erasure repairing on the memory unit in the chip according to the erasure instruction information and jumping to S7.
Further, the erase command information includes an erase command and an address of a storage unit in the chip where an erase operation is required.
The technical scheme also provides a device for reducing the probability of error reading after power failure, which comprises:
the receiving module receives the erasure instruction information;
the erasing module is used for executing erasing operation on the memory cells in the chip according to the erasing instruction information;
the judging module judges whether the chip has abnormal power failure,
the state maintaining module does not change the current operation state of the chip;
an interrupt starting module for starting the power-off interrupt protection,
and the over-erasure repairing module is used for ending the erasure operation of the chip according to the power-off interrupt protection and executing over-erasure repairing on the memory cells in the chip according to the erasure instruction information.
Further, the judging module is realized by a voltage detecting module.
Further, the erasing module and the over-erasing repair module are realized through an algorithm module inside the chip.
The present technical solution also provides a storage medium having a computer program stored therein, which when run on a computer causes the computer to perform the method of any one of the above.
The technical scheme also provides a terminal which comprises a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.
According to the above, during the process of executing the erasing operation by the chip, if abnormal power failure occurs, the power-off interrupt protection is automatically started in the chip to end the erasing operation of the chip, and the over-erasing repair is executed on the memory unit in the chip according to the erasing instruction information; if the power is quickly turned off, the over-erase repair may be performed on a part of memory cells needing to perform the over-erase repair, but the over-erase repair cannot be performed on all memory cells needing to perform the over-erase repair in the chip, and when the power is turned on again, although the problem of error of read data caused by over-erase still exists, the probability of error of read data caused by over-erase is reduced because the over-erase repair is performed on a part of memory cells; if the power is slowly turned off, the over-erasure repairing can be performed on all the memory cells in the chip, which need to be performed with the over-erasure repairing, and the problem of data reading errors caused by over-erasure can be avoided when the power is turned on again.
Drawings
FIG. 1 is a schematic flow chart of an erasure algorithm in the prior art.
Fig. 2 is a schematic block diagram of a prior art.
FIG. 3 is a flow chart of steps of a method for reducing the probability of a read error after a power failure in accordance with the present application.
FIG. 4 is a schematic diagram of an apparatus for reducing the probability of a read error after a power failure in accordance with the present application.
Fig. 5 is a schematic diagram of a terminal in the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in FIG. 3, a method for reducing the probability of error reading after power failure is suitable for an NOR FLASH chip, and specifically comprises the following steps:
s1: and receiving erasure instruction information.
The erasing instruction information comprises an erasing instruction and an address of a storage unit which needs to be subjected to erasing operation in the chip.
S2: and executing erasing operation on the memory cells in the chip according to the erasing instruction information.
S3: and judging whether the voltage applied to the memory cell in the chip is reduced to a preset threshold value, if so, jumping to S5, otherwise jumping to S4.
During the process of executing erasing operation by the chip (at this time, the internal algorithm flow is in the step of erasing, and the step of repairing the over-erased unit is not reached yet), the inside of the chip detects whether the erasing voltage applied to the memory unit in the chip drops to a preset threshold value in real time, if so, abnormal power failure occurs by default, otherwise, abnormal power failure does not occur.
S4: the current operating state of the chip is not changed.
Wherein, the current operation state of the chip is not changed, which means that the erasing operation is continuously executed on the memory unit in the chip according to the erasing instruction information and the normal flow.
S5: and starting power-off interrupt protection.
When abnormal power failure occurs, the power failure interruption protection is automatically started in the chip, the erasing operation of the chip is ended, and over-erasing repair is performed on the memory cells in the chip according to the erasing instruction information.
S6: and ending the erasing operation of the chip according to the power-off interrupt protection, and executing over-erasing repair on the memory unit in the chip according to the erasing instruction information.
The specific operation process of S6 is as follows: when receiving an instruction of erasing a certain sector in a chip sent by a user, the internal algorithm module executes an erasing step, and if abnormal power failure occurs, the power failure protection module sends power failure protection interruption to the internal algorithm module of the chip, and the NOR Flash immediately responds to the interruption to end erasing and enter an over-erasing repair stage.
Since the voltage applied to the memory cell in the chip when the over-erase repair is performed is lower than the voltage applied to the memory cell in the chip when the erase operation is performed, the over-erase repair can be performed although the erase operation cannot be continuously performed when the abnormal power failure occurs.
When abnormal power failure occurs, quick power failure is likely to occur (the power failure speed is high, namely, the duration of the process from a preset threshold value to the voltage required to be applied to the memory cells when the chip executes over-erase repair is short, the chip cannot be supported to execute the whole over-erase repair process), at this time, the over-erase repair may already be executed on part of the memory cells which need to execute the over-erase repair (according to the power failure speed), but the over-erase repair cannot be executed on all the memory cells which need to execute the over-erase repair in the chip, at this time, when the power is re-applied, although the problem that the over-erase results in error of the read data exists, because the over-erase repair is already executed on part of the memory cells, the probability of error of the read data is reduced because of over-erase; when abnormal power failure occurs, slow power failure (the power failure speed is slower, that is, the duration of the process from the preset threshold value to the voltage required to be applied to the memory cell when the chip executes over-erase repair is long enough (about several ms), the chip can be supported to execute the whole over-erase repair process), at this time, over-erase repair can be executed on all the memory cells in the chip, and the problem of data reading error caused by over-erase can be avoided when the power is turned on again.
In order to reduce the power consumption when slow power failure occurs, the method further comprises the following steps after S6:
s7: judging whether all the memory units which need to execute the over-erasure repairing in the chip have executed the over-erasure repairing, if so, jumping to S8, otherwise jumping to S9;
s8: reducing the voltage applied to the memory cells in the chip to 0 and exiting the over-erase repair process;
s9: and executing over-erasure repairing on the memory unit in the chip according to the erasure instruction information and jumping to S7.
During the execution of the erasing operation by the chip, detecting whether the erasing voltage applied to the memory cell in the chip is reduced to a preset threshold value or not in real time, for example, the erasing voltage requirement of the memory cell in the chip is 1.8v, when detecting whether the voltage applied to the memory cell in the chip is reduced to 1.5v or not, namely, the abnormal power-down condition occurs by default, automatically starting the power-down interruption protection in the chip, ending the erasing operation of the chip, and executing over-erasing repair on the memory cell in the chip according to the erasing instruction information; if the duration of the process from 1.5v to 1.2v is short (less than a few ms), the power-down occurs quickly, and at this time, the over-erase repair may have been performed on some memory cells that need to perform the over-erase repair, but the over-erase repair cannot be performed on all memory cells in the chip that need to perform the over-erase repair; if the process of dropping from 1.5v to 1.2v is relatively slow (can last for a few ms), slow power-down occurs, at this time, over-erase repair can be performed on all memory cells in the chip, and after over-erase repair is performed on all memory cells in the chip, the voltage pump is controlled to discharge to 0v, and the algorithm is exited.
Compared with the scheme that after the chip is powered up again, the over-erasure repairing is executed before the data reading (although the scheme can solve the problem of data reading errors caused by over-erasure after power failure), the over-erasure repairing method has the advantages of being shorter in operation time and higher in efficiency, because after the chip is powered up again, under the condition that the over-erasure repairing is executed before the data reading, the system does not know which storage units in the chip execute the over-erasure operation after the chip is powered down again, over-erasure units in the chip cannot be found quickly (whether all the storage units in the chip need to be judged or not is judged, and the over-erasure repairing can be executed after the over-erasure units are found, so that the time consumption is longer; in the technical scheme, the over-erasure repairing is executed while the erasure is responded, and although the erasure operation is interrupted, the inside of the chip knows which memory cells execute the erasure operation, so the over-erasure cell can be found out quickly (all memory cells in the chip are not needed to be judged, and only the memory cells which execute the erasure are needed to be judged), so the time consumption is shorter and the efficiency is higher.
As shown in fig. 4, an apparatus for reducing the probability of a read error after power failure includes:
a receiving module 101 that receives erasure instruction information;
an erasing module 102, which executes erasing operation to the memory cells in the chip according to the erasing instruction information;
a judging module 103 for judging whether the chip is abnormally powered down,
the state holding module 104 does not change the current operation state of the chip;
an interrupt initiation module 105, initiates power-off interrupt protection,
and the over-erasure repairing module 106 is used for ending the erasure operation of the chip according to the power-off interrupt protection and executing over-erasure repairing on the memory cells in the chip according to the erasure instruction information.
In some embodiments, the determination module 103 is implemented using a voltage detection module.
In some embodiments, the erase module 102 and the over-erase repair module 106 are implemented by an algorithm module within the chip.
When receiving an instruction of erasing a certain sector in a chip sent by a user, the internal algorithm module executes an erasing step, and if abnormal power failure occurs, the power failure protection module sends power failure protection interruption to the internal algorithm module of the chip, and the NOR Flash immediately responds to the interruption to end erasing and enter an over-erasing repair stage; discharging the voltage pump to 0V after finishing over-erasure repairing if the power failure is slow (even if the voltage applied to the memory cell in the chip is reduced to 0), and exiting the over-erasure repairing algorithm flow; when the NOR FLASH power supply is restored, the correctness of the data reading of the selected unit cannot be affected because the over-erased unit is restored.
Referring to fig. 5, the embodiment of the application further provides a terminal. As shown, terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling computer programs stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.
In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to the processes of one or more computer programs into the memory 302 according to the following steps, and the processor 301 executes the computer programs stored in the memory 302, so as to implement various functions: receiving erasure instruction information; executing erasing operation on a memory unit in the chip according to the erasing instruction information; judging whether the chip is abnormally powered down, if not, not changing the current operation state of the chip; if yes, starting power-off interrupt protection, ending the erasing operation of the chip according to the power-off interrupt protection, and executing over-erasing repair on the memory unit in the chip according to the erasing instruction information.
Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs that include instructions that are executable in a processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.
An embodiment of the present application provides a storage medium, which when executed by a processor, performs a method in any of the alternative implementations of the above embodiments to implement the following functions: receiving erasure instruction information; executing erasing operation on a memory unit in the chip according to the erasing instruction information; judging whether the chip is abnormally powered down, if not, not changing the current operation state of the chip; if yes, starting power-off interrupt protection, ending the erasing operation of the chip according to the power-off interrupt protection, and executing over-erasing repair on the memory unit in the chip according to the erasing instruction information. The storage medium may be implemented by any type of volatile or nonvolatile Memory device or combination thereof, such as static random access Memory (Static Random Access Memory, SRAM), electrically erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), erasable Programmable Read-Only Memory (Erasable Programmable Read Only Memory, EPROM), programmable Read-Only Memory (PROM), read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic disk, or optical disk.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. The method for reducing the probability of the reading error after power failure is characterized by comprising the following steps of:
receiving erasure instruction information;
executing erasing operation on a memory unit in the chip according to the erasing instruction information;
judging whether the chip is abnormally powered down, wherein the abnormal power down comprises fast power down and slow power down,
if not, the current operation state of the chip is not changed;
if yes, the power-off interrupt protection is started,
ending the erasing operation of the chip according to the power-off interrupt protection, and executing over-erasing repair on the memory unit in the chip according to the erasing instruction information;
when the abnormal power failure is slow power failure, the erasing operation of the chip is finished according to the power-off interrupt protection, and the over-erasing repair is executed on the memory unit in the chip according to the erasing instruction information, and the method further comprises the following steps:
s7: judging whether all the memory units which need to execute the over-erasure repairing in the chip have executed the over-erasure repairing, if so, jumping to S8, otherwise jumping to S9;
s8: reducing the voltage applied to the memory cells in the chip to 0 and exiting the over-erase repair process;
s9: and executing over-erasure repairing on the memory unit in the chip according to the erasure instruction information and jumping to S7.
2. The method for reducing the probability of a read error after power failure according to claim 1, wherein the specific process of determining whether the chip has abnormal power failure is as follows: it is determined whether a voltage applied to a memory cell within the chip drops to a preset threshold.
3. The method of claim 1, wherein the erase command information includes an erase command and addresses of memory cells in the chip that need to be erased.
4. An apparatus for reducing the probability of a read error after a power failure, comprising:
the receiving module receives the erasure instruction information;
the erasing module is used for executing erasing operation on the memory cells in the chip according to the erasing instruction information;
the judging module is used for judging whether abnormal power failure occurs to the chip or not, wherein the abnormal power failure comprises fast power failure and slow power failure;
the state maintaining module does not change the current operation state of the chip;
an interrupt starting module for starting the power-off interrupt protection,
the over-erasure repairing module is used for finishing the erasure operation of the chip according to the power-off interruption protection, executing over-erasure repairing to the memory cells in the chip according to the erasure instruction information, and executing the following processes after executing the over-erasure repairing to the memory cells in the chip according to the erasure instruction information when the abnormal power-off is slow power-off:
s7: judging whether all the memory units which need to execute the over-erasure repairing in the chip have executed the over-erasure repairing, if so, jumping to S8, otherwise jumping to S9;
s8: reducing the voltage applied to the memory cells in the chip to 0 and exiting the over-erase repair process;
s9: and executing over-erasure repairing on the memory unit in the chip according to the erasure instruction information and jumping to S7.
5. The apparatus for reducing the probability of a read error after a power failure of claim 4, wherein the determining module is implemented with a voltage detection module.
6. The apparatus of claim 4, wherein the erase module and the over-erase repair module are implemented by an algorithm module within the chip.
7. A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform the method of any of claims 1 to 3.
8. A terminal comprising a processor and a memory, said memory having stored therein a computer program, said processor being adapted to perform the method of any of claims 1 to 3 by invoking said computer program stored in said memory.
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| CN111261213A (en) * | 2020-04-30 | 2020-06-09 | 深圳市芯天下技术有限公司 | Erasing method of NOR Flash |
| CN112466375A (en) * | 2020-10-29 | 2021-03-09 | 普冉半导体(上海)股份有限公司 | Method for detecting over-erasing phenomenon of nonvolatile memory |
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