CN105761754A

CN105761754A - Memory cell programming method, memory control circuit unit and memory apparatus

Info

Publication number: CN105761754A
Application number: CN201410799120.2A
Authority: CN
Inventors: 林纬; 许祐诚
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2014-12-19
Filing date: 2014-12-19
Publication date: 2016-07-13
Anticipated expiration: 2034-12-19
Also published as: CN105761754B

Abstract

The invention provides a memory cell programming method, a memory control circuit unit and a memory apparatus. The memory cell programming method comprises the following steps: dividing the entity erasing unit of a rewritable nonvolatile memory module into a first region and a second region, wherein a first group of programming parameters is preset to be used for writing first type data into a lower entity programming unit belonging to the entity erasing unit of the first region, and the upper entity programming unit of the entity erasing unit of the first region is not used to store data; adjusting the first group of programming parameters to obtain a second group of programming parameters; and writing second type data into the lower entity programming unit belonging to the entity erasing unit of the second region by using the second group of programming parameters, wherein the upper entity programming parameters of the entity erasing unit of the second region is not used to store the data.

Description

Memory cell programming method, memorizer control circuit unit and storage device

Technical field

The invention relates to a kind of memory cell programming method, and in particular to a kind of for the memory cell programming method of reproducible nonvolatile memorizer module, memorizer control circuit unit and storage device.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years so that the demand of storage media is also increased by consumer rapidly.Due to type nonvolatile (rewritablenon-volatilememory) there is data non-volatile, power saving, the characteristic such as volume is little, mechanical structure, read or write speed are fast, be most suitable for portable type electronic product, for instance notebook.Solid state hard disc is exactly a kind of memory storage apparatus using flash memory as storage media.Therefore, flash memory industry becomes a ring quite popular in electronic industry in recent years.

Along with the progress of manufacture of semiconductor, current technology has been developed in the flash memory module with the memory element that can store multiple Bit data.Specifically, flash memory module data write (or being called programming) be utilize bestow voltage to flash memory component specific endpoints (such as, control gate voltage one of changes in grid electric charge and mends the amount of electrons catching layer), thus change the conducting state of the passage of memory element, to present different storage states.Such as, with multi-level cell memory (Multi-LevelCell, it being called for short MLC) NAND type flash memory is example, instantly page data is 1 and upper page data when being 1, control circuit can not change the grid voltage in memory element by control character line control circuit, and the storage state of memory element is remained " 11 "；Instantly page data is 1 and upper page data when being 0, and word-line control circuit can change the grid voltage in memory element under the control of control circuit, and the storage state of memory element is changed into " 10 "；Instantly page data is 0 and upper page data when being 0, and word-line control circuit can change the grid voltage in memory element under the control of control circuit, and the storage state of memory element is changed into " 00 "；Further, page data is 0 and upper page data when being 1 instantly, and word-line control circuit can change the grid voltage in memory element under the control of control circuit, and the storage state of memory element is changed into " 01 ".It is to say, when reading the data, control circuit can identify the storage state of this memory element according to the grid voltage in current memory element.

In programming process, memory element can cause aging along with the injection repeatedly of electronics with removing, and causes electronics writing speed to increase and causes critical voltage distribution to broaden.Therefore, after repeatedly programming, memory element possibly cannot be correctly identified its storage state, and produces error bit.In addition; when the stored data of same memory element are repeatedly read; the such as reading times between 10 ten thousand to million times, it is more likely that it is the situation of mistake that the data read can occur, even this is repeatedly read stored data in entity erased cell and can occur abnormal or lose.And this type of phenomenon has with field of the present invention, and usually intellectual is used is called " reading interference " (read-disturb).Particularly, system data (the such as firmware code (FirmwareCode), file allocation table (FileAllocationTable of meeting storage flash memory storage system in flash memory module, it is called for short FAT), and this system data can the reading on altofrequency ground during flash memory storage system operates.

Base this, suitable program parameters how is used to carry out memory cells, to avoid memory element rapid degradation, simultaneously again can preferably one of in control gate electric charge mend the amount of electrons of catching layer and occur to prevent from reading interference, be the targets endeavoured of these those skilled in the art.

Summary of the invention

The present invention provides a kind of memory cell programming method, memorizer control circuit unit and storage device, and it can extend the life-span of memory element, and avoids reading the generation of interference.

One example of the present invention embodiment proposes a kind of memory cell programming method for reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple entity erased cell, and each entity erased cell has multiple entity programming unit.This memory cell programming method includes: use first group of program parameters that primary sources write one of them the entity programming unit among these a little entity programming units；And use second group of program parameters by one of them the entity programming unit among secondary sources write so far a little entity programming units, wherein in first group of program parameters, at least part of parameter differs in second group of program parameters, and is same as the data bit number of the memory element of the entity programming unit writing secondary sources with second group of program parameters with the data bit number of the memory element of the entity programming unit of first group of program parameters write primary sources.

In one example of the present invention embodiment, the entity programming unit writing secondary sources among these a little entity programming units maps corresponding logical address, and the entity programming unit of write primary sources is without mapping corresponding logical address.

In one example of the present invention embodiment, the data bit number that the data bit number wherein writing the memory element of the entity programming unit of primary sources with first group of program parameters is 1 bit and the memory element of the entity programming unit writing secondary sources with second group of program parameters is for 1 bit.

In one example of the present invention embodiment, said memory cells programmed method also includes: entity erased cell is at least grouped into the firstth district and the secondth district.And, the step that primary sources are write among these a little entity programming units by first group of program parameters of above-mentioned use includes: use first group of program parameters by primary sources write to the entity erased cell belonging to the firstth district, and secondary sources are write the step of these a little entity programming units and include by second group of program parameters of above-mentioned use: use second group of program parameters by secondary sources write to the entity erased cell belonging to the secondth district.

In one example of the present invention embodiment, those entity programming units of each entity erased cell include multiple lower entity programming unit and multiple upper entity programming units.This first group of program parameters is preset the entity erased cell for belonging to this firstth district, and the upper entity programming unit of the entity erased cell in this firstth district will not be used to storage data.This second group of program parameters is for belonging to the entity erased cell in this secondth district, and the upper entity programming unit of the entity erased cell in this secondth district will not be used to storage data.

In one example of the present invention embodiment, said memory cells programmed method also includes: adjust first group of program parameters to obtain second group of program parameters.

In one example of the present invention embodiment, said memory cells programmed method also includes: receive data；Judge whether these data belong to secondary sources；If these data are not belonging to secondary sources, first group of program parameters is used to write data at least one first instance erased cell to the entity erased cell in the firstth district；And if when these data belong to secondary sources, using second group of program parameters by least one second instance erased cell among these data write to the entity erased cell in the secondth district.

In one example of the present invention embodiment, said memory cells programmed method also includes: identify at least one logical block being intended to store these data；Judge whether this at least one logical block maps to the entity erased cell in the secondth district；And if when this at least one logical block is the entity erased cell mapping to the secondth district, identifying that these data are belonging to secondary sources.

In one example of the present invention embodiment, said memory cells programmed method also includes: use the instruction of erasing of monolayer memory element mode to perform to erase operation to above-mentioned first instance erased cell；And use the instruction of erasing of multilayered memory unit mode to perform to erase operation to above-mentioned second instance erased cell.

In one example of the present invention embodiment, above-mentioned first group of program parameters includes the first incremental step pulse program adjusted value, first is originally written into voltage, the first verifying voltage, the first read voltage, the first conducting voltage are erased at least one of voltage with first.

In one example of the present invention embodiment, the data retention of the entity programming unit programmed with first group of program parameters among above-mentioned entity programming unit or anti-reading interference performance are better than the data retention of the entity programming unit with second group of program parameters programming or anti-reading interference performance.

In one example of the present invention embodiment, among above-mentioned entity programming unit, it is better than the life-span of the entity programming unit programmed with this first group of program parameters with the life-span of the entity programming unit of this second group of program parameters programming.

In one example of the present invention embodiment, with the voltage spacing between the first state more than the threshold voltage statistical Butut of the memory element of the entity programming unit with this second group of program parameters programming of the voltage spacing between the first state of the threshold voltage statistical Butut of the memory element of the entity programming unit of this first group of program parameters programming and the second state and the second state among above-mentioned entity programming unit.

In one example of the present invention embodiment, first group of program parameters of above-mentioned adjustment includes with the step obtaining second group of program parameters: the first verifying voltage adjusting first group of program parameter is used as the second verifying voltage of second group of program parameter to obtain voltage, and wherein the first verifying voltage of first group of program parameter is more than the second verifying voltage of second group of program parameter.

In one example of the present invention embodiment, first group of program parameters of above-mentioned adjustment includes with the step obtaining second group of program parameters: the first incremental step pulse program adjusted value adjusting first group of program parameter is used as the second incremental step pulse program adjusted value of second group of program parameter to obtain a value.

In one example of the present invention embodiment, above-mentioned primary sources are firmware code and above-mentioned firstth district is independently in order to store the system area of firmware code, and above-mentioned secondary sources are user data and transient area that the secondth district is temporary user data.

In one example of the present invention embodiment, said memory cells programmed method also includes: use first group of parameter that storage has the entity programming unit of primary sources perform to erase operation；And use second group of parameter to have the entity programming unit of secondary sources to perform this operation of erasing storage.

One example of the present invention embodiment proposes a kind of memorizer control circuit unit, is used for accessing reproducible nonvolatile memorizer module, and above-mentioned memorizer control circuit unit includes: HPI, memory interface and memory management circuitry.HPI is electrically connected to host computer system.Memory interface is electrically connected to reproducible nonvolatile memorizer module, and wherein reproducible nonvolatile memorizer module has multiple entity erased cell, and each entity erased cell has multiple entity programming unit.Memory management circuitry is electrically connected to HPI and memory interface.This memory management circuitry uses first group of program parameters that primary sources write one of them the entity programming unit among these a little entity programming units；And use second group of program parameters by one of them the entity programming unit among secondary sources write so far a little entity programming units, wherein in first group of program parameters, at least part of parameter differs in second group of program parameters, and is same as the data bit number of the memory element of the entity programming unit writing secondary sources with second group of program parameters with the data bit number of the memory element of the entity programming unit of first group of program parameters write primary sources.

One example of the present invention embodiment proposes a kind of memory storage apparatus, comprising: connect interface unit, reproducible nonvolatile memorizer module and memorizer control circuit unit.Connect interface unit and be electrically connected to host computer system.Reproducible nonvolatile memorizer module has multiple entity erased cell, and each entity erased cell has multiple entity programming unit.Memorizer control circuit unit is electrically connected to connection interface unit and reproducible nonvolatile memorizer module.This memorizer control circuit unit uses first group of program parameters that primary sources write one of them the entity programming unit among these a little entity programming units；And use second group of program parameters by one of them the entity programming unit among secondary sources write so far a little entity programming units, wherein in first group of program parameters, at least part of parameter differs in second group of program parameters, and is same as the data bit number of the memory element of the entity programming unit writing secondary sources with second group of program parameters with the data bit number of the memory element of the entity programming unit of first group of program parameters write primary sources.

In one example of the present invention embodiment, entity erased cell is at least grouped into the firstth district and the secondth district by above-mentioned memorizer control circuit unit.And, in the operation that primary sources are write among these a little entity programming units by first group of program parameters of above-mentioned use, above-mentioned memorizer control circuit unit uses first group of program parameters by primary sources write to the entity erased cell belonging to the firstth district, and secondary sources being write in the operation of these a little entity programming units in second group of program parameters of above-mentioned use, above-mentioned memorizer control circuit unit uses second group of program parameters by secondary sources write to the entity erased cell belonging to the secondth district.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit adjusts first group of program parameters to obtain second group of program parameters.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit receives data, and judges whether these data belong to secondary sources.If data are not belonging to secondary sources, memorizer control circuit unit uses first group of program parameters by least one first instance erased cell among these data write to those entity erased cell in the firstth district.If these data belong to secondary sources, memorizer control circuit unit uses second group of program parameters by least one second instance erased cell among these data write to the entity erased cell in the secondth district.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit identification is intended to store at least one logical block of these data, and judges whether this at least one logical block maps to the entity erased cell in the secondth district.If this at least one logical block is the entity erased cell mapping to the secondth district, memorizer control circuit these data of unit identification are belonging to secondary sources.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit uses the instruction of erasing of monolayer memory element mode to perform to erase operation to above-mentioned first instance erased cell, and uses the instruction of erasing of multilayered memory unit mode the execution of above-mentioned second instance erased cell to be erased operation.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit adjusts the first verifying voltage of first group of program parameter and is used as the second verifying voltage of second group of program parameter to obtain a voltage, and wherein the first verifying voltage of first group of program parameter is more than the second verifying voltage of second group of program parameter.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit adjusts the first incremental step pulse program adjusted value of first group of program parameter and is used as the second incremental step pulse program adjusted value of second group of program parameter to obtain a value, and wherein the first incremental step pulse program adjusted value of first group of program parameter is less than the second incremental step pulse program adjusted value of second group of program parameter.

In one example of the present invention embodiment, above-mentioned memorizer control circuit unit uses first group of parameter that storage has the entity programming unit of primary sources perform to erase operation, and uses second group of parameter to have the entity programming unit of secondary sources to perform this operation of erasing to storing.

Based on above-mentioned, the memory cell programming method of exemplary embodiment of the present invention, memorizer control circuit unit can carry out write data according to the program parameters that the regional choice of the data being intended to storage is different from storage device, thus can extend the life-span of memory element, take into account the preservation of important system data simultaneously.

For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.

Accompanying drawing explanation

Fig. 1 is the structural representation of the host computer system shown by an exemplary embodiment and memory storage apparatus；

Fig. 2 is the schematic diagram of the computer shown by an exemplary embodiment, input/output device and memory storage apparatus；

Fig. 3 is the schematic diagram of the host computer system shown by an exemplary embodiment and memory storage apparatus；

Fig. 4 is the structural representation illustrating the memory storage apparatus shown by an exemplary embodiment；

Fig. 5 is the structural representation of the reproducible nonvolatile memorizer module shown by an exemplary embodiment；

Fig. 6 is the schematic diagram of the memory cell array shown by an exemplary embodiment；

Fig. 7 is the schematic diagram of the memory cells shown by an exemplary embodiment；

Fig. 8 is the schematic diagram reading data from memory element shown by an exemplary embodiment；

Fig. 9, Figure 10, Figure 11 and Figure 12 are the example schematic of the management entity erased cell shown by an exemplary embodiment；

Figure 13 is the structural representation of the memorizer control circuit unit shown by an exemplary embodiment；

Figure 14 is the schematic diagram that the data shown by an example are temporary；

Figure 15 is the schematic diagram of the data consolidation procedure shown by an example；

Figure 16 is the statistical figure of memory element in using the example of entity erased cell in first group of program parameters programing system district shown by an exemplary embodiment；

Figure 17 is the statistical figure of memory element in using the example of entity erased cell in second group of program parameters programming transient area shown by an exemplary embodiment；

Figure 18 is the statistical figure of memory element in using the example of entity erased cell in first group of program parameters programing system district shown by another exemplary embodiment；

Figure 19 is the statistical figure of memory element in using the example of entity erased cell in second group of program parameters programming transient area shown by another exemplary embodiment；

Figure 20 is the flow chart of the memory cell programming method shown by an exemplary embodiment.

Description of reference numerals:

1000: host computer system；

1100: computer；

1102: microprocessor；

1104: random access memory (RAM)；

1106: input/output (I/O) device；

1108: system bus；

1110: data transmission interface；

1202: mouse；

1204: keyboard；

1206: display；

1208: printer；

1212: Portable disk；

1214: memory card；

1216: solid state hard disc；

1310: digital camera；

1312:SD card；

1314:MMC card；

1316: memory stick；

1318:CF card；

1320: embedded storage device；

100: memory storage apparatus；

102: connect interface unit；

104: memorizer control circuit unit；

106: reproducible nonvolatile memorizer module；

2202: memory cell array；

2204: word-line control circuit；

2206: bit line control circuit；

2208: line decoder；

2210: data input/output buffer storage；

2212: control circuit；

702: memory element；

704: bit line；

706: word-line；

708: source electrode line；

712: select grid leak gated transistors；

714: select grid source transistor；

VA: the first presets read voltage；

VB: the second presets read voltage；

VC: the three presets read voltage；

VD: the four presets read voltage；

VE: the five presets read voltage；

VF: the six presets read voltage；

VG: the seven presets read voltage；

202: memory management circuitry；

410 (0)～410 (N): entity erased cell；

502: data field；

504: idle district；

506: system area；

508: transient area；

510: replace district；

LBA (0)～LBA (H): logical block；

204: HPI；

206: memory interface；

208: error checking and correcting circuit；

210: buffer storage；

212: electric power management circuit；

VV1: the first verifying voltage；

VV2: the second verifying voltage；

S2001, S2003, S2005, S2007: step.

Detailed description of the invention

Reproducible nonvolatile memorizer module and controller (also referred to as, control circuit) is included it is said that in general, memory storage apparatus (also referred to as, storage system).Being commonly stored device storage device is use together with host computer system, so that host computer system can write data into memory storage apparatus or read data from memory storage apparatus.

Fig. 1 is the structural representation of the host computer system shown by an exemplary embodiment and memory storage apparatus.

Refer to Fig. 1, host computer system 1000 generally comprises computer 1100 and input/output (input/output, I/O) device 1106.Computer 1100 includes microprocessor 1102, random access memory (randomaccessmemory is called for short RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 includes such as the mouse 1202 of Fig. 2 schematic diagram of the computer shown by an exemplary embodiment, input/output device and memory storage apparatus (Fig. 2 be), keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device 1106 of device shown in Fig. 2, input/output device 1106 can also include other devices.

In embodiments of the present invention, memory storage apparatus 100 is to be electrically connected by other elements of data transmission interface 1110 with host computer system 1000.Can be write data into memory storage apparatus 100 by the operation of microprocessor 1102, random access memory 1104 and input/output device 1106 or from memory storage apparatus 100, read data.Such as, memory storage apparatus 100 can be the type nonvolatile storage device of Portable disk 1212 as shown in Figure 2, memory card 1214 or solid state hard disc (SolidStateDrive is called for short SSD) 1216 grades.

It is said that in general, host computer system 1000 is any system that can coordinate to store data substantially with memory storage apparatus 100.Although in this exemplary embodiment, host computer system 1000 is to explain with computer system, but, in another exemplary embodiment of the present invention, host computer system 1000 can be the systems such as digital camera, video camera, communicator, audio player or video player.Such as, when host computer system is digital camera (video camera) 1310, type nonvolatile storage device is then for its SD card 1312 used, mmc card 1314, memory stick (memorystick) 1316, CF card 1318 or embedded storage device 1320 (as it is shown on figure 3, Fig. 3 is the schematic diagram of the host computer system shown by an exemplary embodiment and memory storage apparatus).Embedded storage device 1320 includes embedded multi-media card (EmbeddedMMC is called for short eMMC).It is noted that embedded multi-media card is directly to be electrically connected on the substrate of host computer system.

Fig. 4 is the structural representation illustrating the memory storage apparatus shown by an exemplary embodiment.

Refer to Fig. 4, memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104 and reproducible nonvolatile memorizer module 106.

In this exemplary embodiment, connect interface unit 102 and be compatible with USB (universal serial bus) (UniversalSerialBus is called for short USB) standard.nullBut，It must be appreciated，The invention is not restricted to this，Connect interface unit 102 and can also be consistent with parallel advanced adnexa (ParallelAdvancedTechnologyAttachment,It is called for short PATA) standard、Institute of Electrical and Electric Engineers (InstituteofElectricalandElectronicEngineers,It is called for short IEEE) 1394 standards、High-speed peripheral component connecting interface (PeripheralComponentInterconnectExpress,It is called for short PCIExpress) standard、Safety digit (SecureDigital,It is called for short SD) interface standard、Serial Advanced Technology Attachment (SerialAdvancedTechnologyAttachment,It is called for short SATA) standard、A ultrahigh speed generation (UltraHighSpeed-I,It is called for short UHS-I) interface standard、Secondary (the UltraHighSpeed-II of ultrahigh speed,It is called for short UHS-II) interface standard、Memory stick (MemoryStick,It is called for short MS) interface standard、Multimedia storage card (MultiMediaCard,It is called for short MMC) interface standard、Built-in multimedia storage card (EmbeddedMultimediaCard,It is called for short eMMC) interface standard、General flash memory (UniversalFlashStorage,It is called for short UFS) interface standard、Compact flash (CompactFlash,It is called for short CF) interface standard、Integrated form drives electrical interface (IntegratedDeviceElectronics,Be called for short IDE) standard or other be suitable for standard.

Memorizer control circuit unit 104 is in order to perform the multiple logic gates with hardware pattern or firmware pattern implementation or control instruction, and carries out the write of data in reproducible nonvolatile memorizer module 106 according to the instruction of host computer system 1000, read and the operation such as erase.

Reproducible nonvolatile memorizer module 106 is electrically connected to memorizer control circuit unit 104, and in order to data that host system 1000 writes.Specifically, the memory element of reproducible nonvolatile memorizer module 106 constitutes multiple entity programming units to store data.In this exemplary embodiment, reproducible nonvolatile memorizer module 106 is three rank memory element (TrinaryLevelCell, it is called for short TLC) NAND type flash memory module (that is, the flash memory module of 3 Bit datas can be stored in a memory element).But, the invention is not restricted to this, reproducible nonvolatile memorizer module 106 may also be multi-level cell memory (MultiLevelCell, be called for short MLC) NAND type flash memory module (that is, the flash memory module of 2 Bit datas can be stored in a memory element), other flash memory module or other there is the memory module of identical characteristics.

Fig. 5 is the structural representation of the reproducible nonvolatile memorizer module shown by an exemplary embodiment.

Refer to Fig. 5, reproducible nonvolatile memorizer module 106 includes memory cell array 2202, word-line control circuit 2204, bit line control circuit 2206, line decoder (columndecoder) 2208, data input/output buffer storage 2210 and control circuit 2212.

Fig. 6 is the schematic diagram of the memory cell array shown by an exemplary embodiment.

Refer to Fig. 5 and Fig. 6, memory cell array 2202 includes storing multiple memory element 702 of data, multiple selection grid leak pole (selectgatedrain, it is called for short SGD) transistor 712 and multiple selection grid source electrodes (selectgatesource is called for short SGS) transistor 714 and connect a plurality of bit line 704 of these a little memory element, a plurality of word-line 706 and common source line 708 (as shown in Figure 6).Memory element 702 is to be arranged on the bit line 704 cross point with word-line 706 with array way.When receiving write instruction from memorizer control circuit unit 104 or read instruction, control circuit 2212 meeting control character line control circuit 2204, bit line control circuit 2206, line decoder 2208, data input/output buffer storage 2210 writes data to memory cell array 2202 or reads data from memory cell array 2202, wherein word-line control circuit 2204 is in order to control the voltage bestowed to word-line 706, bit line control circuit 2206 is in order to control the voltage bestowed to bit line 704, line decoder 2208 according to the column address in instruction with select correspondence bit line, and data input/output buffer storage 2210 is configured to temporarily store data.

Memory element in reproducible nonvolatile memorizer module 106 is to represent the data of many bits (bits) with multiple grid voltage.Data write (or being called programming) of the memory element of memory cell array 2202 are the voltage utilizing and bestowing a specific endpoints, being such as control gate voltage mends the amount of electrons catching layer one of changing in grid electric charge, thus change the conducting state of the passage of memory element, to present different storage states.

Fig. 7 is the schematic diagram of the memory cells shown by an exemplary embodiment.

Refer to Fig. 7, in this exemplary embodiment, the programming of memory element is to write/verify critical voltage method by pulse to complete.Specifically, when being intended to write data into memory element, memorizer control circuit unit 104 can set and be originally written into voltage and write voltage pulse time, and the control circuit 2212 indicating reproducible nonvolatile memorizer module 106 uses and set is originally written into voltage and write voltage pulse time carrys out memory cells, to carry out the write of data.Afterwards, memorizer control circuit unit 104 can use verifying voltage that memory element is verified, to judge whether memory element has been in correct storage state.If memory element is not programmed to correct storage state, memorizer control circuit unit 104 indicates control circuit 2212 again to carry out memory cells as new write voltage (also referred to as being repeatedly written voltage) and according to new write voltage with write voltage pulse time plus an incremental step pulse program (Incremental-step-pulseprogramming, abbreviation ISPP) adjusted value with the write voltage bestowed at present.Otherwise, if during programmed to the correct storage state of memory element, then it represents that data have been correctly written to memory element.Such as, being originally written into voltage and can be set to 16 volts (Voltage is called for short V), write voltage pulse time can be set to 18 microsecond (microseconds, it is called for short μ s) and incremental step pulse program adjusted value is set to 0.6V, but the invention is not restricted to this.

The read operation of the memory element of memory cell array 2202 is by bestowing read voltage in control gate (controlgate), by the passage of memory element, (memory element is in order to electrically connect the path of bit line and source electrode line, such as cell source to the path between drain electrode) conducting state, carry out the data of recognition memory cell storage.

Fig. 8 is the schematic diagram reading data from memory element shown by an exemplary embodiment, and it is for TLCNAND type flash memory.

Refer to Fig. 8, the storage state of the memory element of reproducible nonvolatile memorizer module 106 includes the minimum effective bit (LeastSignificantBit of the 1st bit that left side is counted, be called for short LSB), the middle significant bit (CenterSignificantBit of the 2nd bit counted from left side, it is called for short CSB) and the highest significant bit (MostSignificantBit of the 3rd bit counted from left side, it is called for short MSB), wherein entity programming unit under LSB correspondence, entity programming unit in CSB correspondence, entity programming unit in MSB correspondence.In this example, grid voltage in each memory element can according to first preset read voltage VA, second preset read voltage VB, the 3rd preset read voltage VC, the 4th preset read voltage VD, the 5th preset read voltage VE, the 6th preset read voltage VF and the seven preset read voltage VG and divide into 8 kinds of storage states (that is, " 111 ", " 110 ", " 100 ", " 101 ", " 001 ", " 000 ", " 010 " and " 011 ").Particularly, the several memory element being arranged on same word-line can form 3 entity programming units, the entity programming unit that wherein thus the LSB of a little memory element forms is called lower entity programming unit, the entity programming unit that thus CSB of a little memory element forms is called middle entity programming unit, and the entity programming unit that thus MSB of memory element forms a bit is called entity programming unit.

Fig. 9, Figure 10, Figure 11 and Figure 12 are the example schematic of the management entity erased cell shown by an exemplary embodiment.

Refer to Fig. 9, the memory element 702 of reproducible nonvolatile memorizer module 106 can be read operation and operation of in units of entity erased cell, the memory element 702 of reproducible nonvolatile memorizer module 106 being erased by memorizer control circuit unit 104 (or memory management circuitry 202) in units of entity programming unit.Specifically, the memory element 702 of reproducible nonvolatile memorizer module 106 can constitute multiple entity programming unit, and these a little entity programming units can constitute multiple entity erased cell 400 (0)～400 (N).Entity erased cell is the least unit erased.That is, each entity erased cell contains the memory element being erased in the lump of minimal amount.Entity programming unit is the minimum unit of programming.That is, an entity programming unit is the minimum unit of write data.Each entity programming unit generally includes data bit district and redundancy ratio special zone.Data bit district comprises multiple entity access address in order to store the data of user, and redundancy ratio special zone is in order to store the data (such as, controlling information and error correcting code) of system.Such as, for the reproducible nonvolatile memorizer module 106 belonging to TLCNAND flash memory, the LSB of the memory element being positioned on same word-line can constitute a lower entity programming unit；The CSB of the memory element being arranged on same word-line can constitute an entity programming unit；And the MSB of the memory element being positioned on same word-line can constitute a upper entity programming unit.It is to say, the entity programming unit in the entity erased cell of reproducible nonvolatile memorizer module 106 can divide into lower entity programming unit, middle entity programming unit and upper entity programming unit (as shown in Figure 10).

Refer to Figure 11, in this exemplary embodiment, entity erased cell 410 (0)～410 (N) can be logically grouped into data field 502, idle district 504, system area 506, transient area 508 and replace district 510 by memorizer control circuit unit 104 (or memory management circuitry 202).

The entity erased cell logically belonging to data field 502 and idle district 504 is the data storing and coming from host computer system 1000.Specifically, the entity erased cell of data field 502 is regarded as storing the entity erased cell of data, and the entity erased cell in idle district 504 is the entity erased cell in order to replacement data district 502.That is, when receiving write instruction with the data being intended to write from host computer system 1000, memorizer control circuit unit 104 (or memory management circuitry 202) can extract entity erased cell from idle district 504, and write data into the entity erased cell extracted, with the entity erased cell in replacement data district 502.

The entity erased cell logically belonging to system area 506 is to record system data.Such as, system data includes the firmware code etc. of the manufacturer about reproducible nonvolatile memorizer module and model, the entity erased cell number of reproducible nonvolatile memorizer module, the entity programming unit number of each entity erased cell, memory storage apparatus 100.

The entity erased cell logically belonging to transient area 508 is used as in the temporary entity erased cell group of counterlogic unit to keep in entity erased cell, with the data that temporary host computer system 1000 writes.The method of detailed temporal data and step, will coordinate accompanying drawing illustrate as after.

Logically belonging to the entity erased cell replaced in district 510 is replace program for bad entity erased cell, with replacing damaged entity erased cell.Specifically, if replace the entity erased cell damage still having normal entity erased cell and data field 502 in district 510, memory management circuitry 202 can extract normal entity erased cell to change the entity erased cell of damage from replacement district 510.

Particularly, data field 502, idle district 504, system area 506 and the entity erased cell in replacement district 510 quantity can be different according to different memorizer specifications.Further, it is necessary to be appreciated that, in the operation of memory storage apparatus 100, entity erased cell closes the packet relation being coupled to data field 502, idle district 504, system area 506 and replacement district 510 and can dynamically change.Such as, when the entity erased cell in idle district 504 damages and is replaced the entity erased cell replacement in district 510, then the entity erased cell originally replacing district 510 can be associated to idle district 504.

Refer to Figure 12, memorizer control circuit unit 104 (or memory management circuitry 202) meeting configuration logic unit LBA (0)～LBA (H) is to map the entity erased cell of data field 502, and each of which logical block has the entity programming unit of the entity erased cell that multiple logical subunit is answered with mapping pair.And, when the data that host computer system 1000 is intended to write data to logical block or renewal is stored in logical block, memorizer control circuit unit 104 (or memory management circuitry 202) can extract an entity erased cell from idle district 504 and carry out write data, with the entity erased cell of data field 502 of rotating.In this exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.

Data in order to identify each logical block are stored in that entity erased cell, and in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can record the mapping between logical block and entity erased cell.And, when host computer system 1000 be intended in logical subunit access data time, memorizer control circuit unit 104 (or memory management circuitry 202) can confirm the logical block belonging to this logical subunit, and reproducible nonvolatile memorizer module 106 is assigned corresponding job sequence to access data in the entity erased cell mapped in this logical block.Such as, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can store logic in reproducible nonvolatile memorizer module 106 turn physical address mapping table to record the entity erased cell that each logical block is mapped, and logic can be turned physical address mapping table and is loaded into buffer storage 208 and safeguards by memorizer control circuit unit 104 (or memory management circuitry 202) when being intended to access data.

Figure 13 is the structural representation of the memorizer control circuit unit shown by an exemplary embodiment.It will be appreciated that the structure of the memorizer control circuit unit shown in Figure 13 is only an example, the present invention is not limited.

Refer to Figure 13, memorizer control circuit unit 104 includes memory management circuitry 202, HPI 204, memory interface 206 and error checking and correcting circuit 208.

Memory management circuitry 202 is in order to control the integrated operation of memorizer control circuit unit 104.Specifically, memory management circuitry 202 has multiple control instruction, and when memory storage apparatus 100 operates, and these a little control instructions can be performed to carry out the write of data, read and the operation such as erase.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with firmware pattern.Such as, memory management circuitry 202 has microprocessor unit (not shown) and a read only memory (not shown), and these a little control instructions are to be programmed so far in read only memory.When memory storage apparatus 100 operates, these a little control instructions can be performed to carry out the write of data by microprocessor unit, read and the operation such as erase.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code pattern be stored in the specific region (such as, being exclusively used in the system area of storage system data in memory module) of reproducible nonvolatile memorizer module 106.Additionally, memory management circuitry 202 has microprocessor unit (not shown), read only memory (not shown) and random access memory (not shown).Particularly, this read only memory has driving code, and when memorizer control circuit unit 104 is enabled, microprocessor unit can first carry out this and drive code section will be stored in the random access memory that the control instruction in reproducible nonvolatile memorizer module 106 is loaded into memory management circuitry 202.Afterwards, microprocessor unit can run these a little control instructions to carry out the write of data, to read and the operation such as erase.

Additionally, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 a hardware pattern can also carry out implementation.Such as, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memorizer write circuit, memory reading circuitry, memorizer erase circuit and data processing circuit.Erase circuit and data processing circuit of Storage Unit Management circuit, memorizer write circuit, memory reading circuitry, memorizer is electrically connected to microcontroller.Wherein, Storage Unit Management circuit is in order to manage the entity erased cell of reproducible nonvolatile memorizer module 106；Memorizer write circuit in order to assign write instruction to write data into reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106；Memory reading circuitry in order to assign reading instruction to read data from reproducible nonvolatile memorizer module 106 to reproducible nonvolatile memorizer module 106；Memorizer erases circuit in order to reproducible nonvolatile memorizer module 106 to be assigned instruction of erasing data to be erased from reproducible nonvolatile memorizer module 106；And data processing circuit in order to process be intended to write to the data of reproducible nonvolatile memorizer module 106 and from reproducible nonvolatile memorizer module 106 read data.

HPI 204 is electrically connected to memory management circuitry 202 and instruction and data in order to receive with identify that host computer system 1000 transmits.It is to say, the instruction that host computer system 1000 transmits can be sent to memory management circuitry 202 by HPI 204 with data.In this exemplary embodiment, HPI 204 is compatible with USB standard.But, it must be appreciated and the invention is not restricted to this, HPI 204 can also be compatible with PATA standard, IEEE1394 standard, PCIExpress standard, SD standard, SATA standard, UHS-I interface standard, UHS-II interface standard, MS standard, MMC standard, eMMC interface standard, UFS interface standard, CF standard, IDE standard or other data transmission standards being suitable for.

Memory interface 206 is electrically connected to memory management circuitry 202 and in order to access reproducible nonvolatile memorizer module 106.It is to say, the data being intended to write to reproducible nonvolatile memorizer module 106 can be converted to the receptible form of reproducible nonvolatile memorizer module 106 by memory interface 206.

Error checking and correcting circuit 208 are electrically connected to memory management circuitry 202 and in order to perform an error-correcting routine to guarantee the correctness of data.Specifically, when memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, the data read can be performed error-correcting routine with correcting circuit 208 by error checking.Such as, in this exemplary embodiment, error checking corrects (LowDensityParityCheck is called for short LDPC) circuit with correcting circuit 208 for low-density parity, and record log-likelihood ratio (LogLikelihoodRatio is called for short LLR) value inquiry table can be stored.When memory management circuitry 202 reads data from reproducible nonvolatile memorizer module 106, error checking can according to LLR value corresponding in the data read and inquiry table to perform error-correcting routine with correcting circuit 208.Wherein, what deserves to be explained is in another exemplary embodiment, error checking and correcting circuit 208 are alternatively turbine code (TurboCode) circuit.

In the present invention one exemplary embodiment, memorizer control circuit unit 104 also includes buffer storage 210 and electric power management circuit 212.

Buffer storage 210 is electrically connected to memory management circuitry 202 and is configured to temporarily store the data and instruction or the data coming from reproducible nonvolatile memorizer module 106 that come from host computer system 1000.

Electric power management circuit 212 is electrically connected to memory management circuitry 202 and in order to control the power supply of memory storage apparatus 100.

In the exemplary embodiment of the present invention, when host computer system 1000 is intended to storage data to the logical block that data field 502 is mapped, memorizer control circuit unit 104 (or memory management circuitry 202) first can keep in this data with the entity erased cell in transient area 508.Specifically, when receiving, from host computer system 1000, the write instruction that data are stored to logical block by instruction, memorizer control circuit unit 104 (or memory management circuitry 202) can extract several entity erased cell temporary entity erased cell as this logical block corresponding from transient area 508, and uses cut-forms mode first by temporary for the data lower entity programming unit so far keeping in entity erased cell a bit.Afterwards, memorizer control circuit unit 104 (or memory management circuitry 202) just uses many page modes the data in temporary entity erased cell to be write to corresponding entity erased cell and by entity erased cell so far corresponding for this logical unit mappings.At this, it is intended to the data being stored to the logical block mapping to data field 502 also referred to as secondary sources or user data.

At this, so-called cut-forms mode refers to, only stores 1 Bit data in the memory unit.It is to say, for the memory element that can store multiple bit, in cut-forms mode, lower entity programming unit only can be carried out the write operation of data by memorizer control circuit unit 104 (or memory management circuitry 202).Owing to temporary entity erased cell is operated by cut-forms mode, therefore, in this exemplary embodiment, temporary entity erased cell only has the capacity of 1/3rd and can be used and the temporary entity erased cell group of a corresponding logical block can comprise the data that 3 temporary entity erased cell store a logical block to provide enough spaces.In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) is to use cut-forms mode to operate the entity erased cell in transient area 508.

So-called many page modes refer to that the lower entity programming unit of use, middle entity programming unit and upper entity programming unit are to store data.That is, for the memory element of multiple bit can be stored, when using many page modes to carry out write data, the lower entity programming unit of an entity programming unit group, middle entity programming unit can be performed programming with upper entity programming unit by memorizer control circuit unit 104 (or memory management circuitry 202).Being worth mentioning, in an exemplary embodiment, when using many page modes to carry out application entity erased cell, the entity programming unit of same entity programming unit group can simultaneously or periodically be programmed.Furthermore, compared to the entity erased cell operated with cut-forms mode, the service life of the entity erased cell operated with many page modes is shorter.Specifically, the number of times that each entity erased cell can be written into or erase is limited, when an entity erased cell is written of number of times more than one marginal value, this entity erased cell possibility will be damaged and cannot be written into data again, wherein the marginal value of the entity erased cell that the marginal value of the entity erased cell that correspondence operates with many page modes can operate with cut-forms mode lower than correspondence.In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) is to use many page modes to operate to close the entity erased cell being coupled to data field 502.

In this exemplary embodiment, after an entity erased cell is divided to transient area 508, this entity erased cell will be simply possible to use in transient area 508, without mixed with the entity erased cell of data field 502 with idle district 504.It is to say, memorizer control circuit unit 104 (or memory management circuitry 202) can be operating independently the entity erased cell in transient area 508 and idle district 504.Such as, after an entity erased cell is divided to transient area 508, memorizer control circuit unit 104 (or memory management circuitry 202) can operate this entity erased cell with cut-forms mode in transient area 508, until this entity erased cell damages.

Figure 14 is the schematic diagram that the data shown by an example are temporary.

nullRefer to Figure 14，When memory storage apparatus 100 receives instruction by when more new data stores to the write instruction of the 0th～257 logical subunit of logical block LBA (0) from host computer system 1000，Assume in this exemplary embodiment，Memorizer control circuit unit 104 (or memory management circuitry 202) can extract 3 entity erased cell 410 (T+1) from transient area 508、410(T+2)、410 (T+3) are as the temporary entity erased cell of counterlogic unit LBA (0)，Memorizer control circuit unit 104 (or memory management circuitry 202) can use the temporary entity erased cell 410 (T+1) of this counterlogic unit LBA (0)、Temporary entity erased cell 410 (T+2) writes, with temporary entity erased cell 410 (T+3), the more new data belonging to logical block LBA (0).

Such as, memorizer control circuit unit 104 (or memory management circuitry 202) can be intended to store the more new data of the 172nd～257 logical subunit that the more new data of the 0th～85 logical subunit to logical block LBA (0) in turn writes the lower entity programming unit to temporary entity erased cell 410 (T+1), the lower entity programming unit and being intended to that is intended to store the more new data of the 86th～171 logical subunit to logical block LBA (0) and in turn writes to temporary entity erased cell 410 (T+2) stores to logical block LBA (0) (in turn write is to the lower entity programming unit of temporary entity erased cell 410 (T+3).

In this exemplary embodiment, after the more new data that host computer system 1000 is intended to storage writes the temporary entity erased cell 410 (T+1) to counterlogic unit LBA (0), temporary entity erased cell 410 (T+2) and temporary entity erased cell 410 (T+3), memorizer control circuit unit 104 (or memory management circuitry 202) will transmit notice and complete the reply (Response) of instruction to host computer system 1000.And, afterwards, when memory storage apparatus 100 belongs to idle state a period of time (such as, within 30 seconds, from host computer system 1000, do not receive any instruction) or the number of entity erased cell of transient area 508 and idle district 504 sky less than predetermined threshold level time, the valid data belonging to this logical block just can be incorporated into an empty entity erased cell and by this logical unit mappings so far entity erased cell by memorizer control circuit unit 104 (or memory management circuitry 202) from the temporary entity erased cell of counterlogic unit.Such as, predetermined threshold level can be set to 3.However, it is necessary to be appreciated that, the invention is not restricted to this, predetermined threshold level can also be the numerical value that other are suitable.At this, the operation of the entity erased cell that the valid data belonging to this logical block are copied to this logical block of correspondence of data field 502 from the temporary entity erased cell group of a corresponding logical block is called data union operation.

Figure 15 is the schematic diagram of the data consolidation procedure shown by an example.

Assume that valid data (as shown in Figure 7) and the memory management circuitry 202 of all logical subunit of the temporary entity erased cell 410 (T+1) of counterlogic unit LBA (0), temporary entity erased cell 410 (T+2) and temporary entity erased cell 410 (T+3) storage logical units LBA (0) select logical block LBA (0) is carried out data union operation.

First, as shown by Figure 15, memorizer control circuit unit 104 (or memory management circuitry 202) can extract an entity erased cell as when acting on the entity erased cell 410 (F+1) rotated from idle district 504.Specifically, memorizer control circuit unit 104 (or memory management circuitry 202) can select an empty entity erased cell or entity erased cell that stored data are invalid data from idle district 504.Particularly, if the entity erased cell extracted is the entity erased cell of storage invalid data, memorizer control circuit unit 104 (or memory management circuitry 202) understands the operation that first performs erase to this entity erased cell.It is to say, the invalid data on entity erased cell must first be erased.

Afterwards, refer to Figure 15, the valid data belonging to the 0th～85 logical subunit of logical block LBA (0) can be copied to the corresponding page (such as, the 0th～85 entity programming unit) of entity erased cell 410 (F+1) by memorizer control circuit unit 104 (or memory management circuitry 202) from the lower entity programming unit of temporary entity erased cell 410 (T+1).Then, the valid data belonging to the 86th～171 logical subunit of logical block LBA (0) can be copied to the corresponding page (such as, the 86th～171 entity programming unit) of entity erased cell 410 (F+1) by memorizer control circuit unit 104 (or memory management circuitry 202) from the lower entity programming unit of temporary entity erased cell 410 (T+2).Then, the valid data belonging to the 172nd～257 logical subunit of logical block LBA (0) can be copied to the corresponding page (such as, the 172nd～257 entity programming unit) of first instance erased cell 410 (F+1) by memorizer control circuit unit 104 (or memory management circuitry 202) from the lower entity programming unit of temporary entity erased cell 410 (T+3).

It is noted that as it has been described above, the entity erased cell being intended to be associated to data field 502 is to operate with many page modes, therefore, writing to entity erased cell 410 (F+1) is come simultaneously in units of entity programming unit group or periodically program.Specifically, in an exemplary embodiment, the 0th, 1,2 entity programming units of entity erased cell 410 (F+1) can simultaneously be programmed to the data that write belongs to the 0th, 1,2 logical subunit of logical block LBA (0)；3rd, 4,5 entity programming units of entity erased cell 410 (F+1) can simultaneously be programmed to the data that write belongs to the 3rd, 4,5 logical subunit of logical block LBA (0)；And the data of other logical subunit are all be written into first instance erased cell 410 (F+1) in units of entity programming unit group by that analogy.

Finally, memorizer control circuit unit 104 (or memory management circuitry 202) can turn in logic logical block LBA (0) maps in physical address mapping table entity erased cell 410 (F+1) and the operation that performs to erase by the temporary entity erased cell 410 (T+1)～410 (T+3) of counterlogic unit.It is to say, when performing next write instruction, the temporary entity erased cell 410 (T+1)～410 (T+3) being erased just can be selected as the temporary entity erased cell of the logical block being intended to write again.

Except transient area 508, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) also can use cut-forms mode to operate the entity erased cell belonging to system area 506.Specifically, if the stored data of system area 506 are (such as, firmware code) lose and will result in memory storage apparatus 100 and cannot operate, therefore, memorizer control circuit unit 104 (or memory management circuitry 202) can be designed to write data into the lower entity programming unit of the entity erased cell to system area 506.Such as, when this example in embodiment, including incremental step pulse program adjusted value (hereinafter referred to as the first incremental step pulse program adjusted value), it is originally written into voltage (being originally written into voltage hereinafter referred to as first), verifying voltage (hereinafter referred to as the first verifying voltage), read voltage (hereinafter referred to as the first read voltage), one group of program parameters (hereinafter referred to as first group of program parameters) that conducting voltage (hereinafter referred to as the first conducting voltage) and voltage of erasing (are erased voltage hereinafter referred to as first) can be preset the lower entity programming unit for the entity erased cell that data are programmed to system area 506.At this, the data being intended to be stored to the logical block of the entity programming unit in mapped system district 506 are called primary sources or system data.

As mentioned above, when (namely memory storage apparatus 100 receives the data that are intended to store the logical block to the entity erased cell mapping data field 502 from host computer system 1000, received write data belongs to secondary sources) time, memorizer control circuit unit 104 (or memory management circuitry 202) can use the entity erased cell in the transient area 508 with cut-forms mode operation to keep in this data.Such as, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can adjust the first group of program parameters presetting the entity erased cell for system area 506 and produce another group program parameters (hereinafter referred to as second group of program parameters) of the entity erased cell for transient area 508.

That is, in this exemplary embodiment, for being each memory element system area 506 and transient area 508 of only storing 1 Bit data equally, memorizer control circuit unit 104 (or memory management circuitry 202) can use first group of program parameters, with second group of program parameters, with secondary sources, primary sources are write extremely corresponding entity programming unit respectively.

Such as, in an exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) understands the acquired voltage of the first verifying voltage by reducing by first group of program parameters the second verifying voltage as second group of program parameters.

Figure 16 is the statistical figure of memory element in using the example of entity erased cell in first group of program parameters programing system district shown by an exemplary embodiment, and Figure 17 is the statistical figure of memory element in using the example of entity erased cell in second group of program parameters programming transient area shown by an exemplary embodiment.

Refer to Figure 16, the entity erased cell of system area 506 is to operate with cut-forms mode, and therefore, the grid voltage of memory element only needs to be divided into two kinds of storage states.Owing to the first verifying voltage VV1 of first group of program parameters can be set at higher voltage, therefore, when memorizer control circuit unit 104 (or memory management circuitry 202) uses first group of program parameters to write/verify, by pulse, the entity erased cell that critical voltage method writes data into system area 506, programming more repeatedly need to be performed.Particularly, owing to the entity erased cell of system area 506 is to store data that are important and that be frequently read (such as, firmware code), therefore, first verifying voltage VV1 of first group of program parameters can be set at higher voltage, to be distinguished as the storage state (also referred to as the first state) being identified as ' 1 ' significantly and to be identified as the storage state (storing state also referred to as second) of ' 0 ', thus relatively can avoid identifying mistake when reading.It is to say, can more than the voltage spacing between the first state of the threshold voltage statistical Butut of the memory element of the entity programming unit with second group of program parameters programming and the second state with the voltage spacing between the first state of the threshold voltage statistical Butut of the memory element of the entity programming unit of first group of program parameters programming and the second state.Base this, the data retention of entity programming unit with second group of program parameters programming or anti-reading interference performance will be better than with the data retention of the entity programming unit of first group of program parameters programming or anti-reading interference performance.

Refer to Figure 17, similarly, owing to the entity erased cell in transient area 508 is to operate with cut-forms mode, therefore, the grid voltage of memory element only needs to be divided into two kinds of storage states.Particularly, relative to first group of program parameters, owing to the second verifying voltage VV2 of second group of program parameters is less, therefore, when memorizer control circuit unit 104 (or memory management circuitry 202) uses second group of program parameters to write/verify, by pulse, the entity erased cell that data are programmed to transient area 508 by critical voltage method, memory element just can complete the write of data under the programming operation of fewer number by the checking of the second verifying voltage VV2.Entity erased cell relative to system area 506, owing to the entity erased cell in transient area 508 just can complete the write of data under the programming operation of fewer number, therefore, programming operation is relatively low for the influence degree of the entity erased cell in transient area 508.Especially since transient area 508 is for temporal data, therefore, the entity erased cell in transient area 508 can be programmed continually, therefore, use second second group of less for verifying voltage VV2 program parameters, can effectively extend the life-span of the entity erased cell in transient area 508.Base this, with life-span of entity programming unit that the life-span of the entity programming unit of second group of program parameters programming will be better than with first group of program parameters programming.

Such as, in another exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) is also by the acquired adjusted value of the first incremental step pulse program adjusted value strengthening first group of program parameters the second incremental step pulse program adjusted value as second group of program parameters.

Figure 18 is the statistical figure of memory element in using the example of entity erased cell in first group of program parameters programing system district shown by another exemplary embodiment, and Figure 19 is the statistical figure of memory element in using the example of entity erased cell in second group of program parameters programming transient area shown by another exemplary embodiment.

Refer to Figure 18, the entity erased cell of system area 506 is to operate with cut-forms mode, and therefore, the grid voltage of memory element only needs to be divided into two kinds of storage states.Owing to the first incremental step pulse program adjusted value of first group of program parameters can be set at less value, therefore, when memorizer control circuit unit 104 (or memory management circuitry 202) uses first group of program parameters to write/verify, by pulse, the entity erased cell that critical voltage method writes data into system area 506, need to perform programming more repeatedly could by the checking of verifying voltage.But, owing to the first incremental step pulse program adjusted value is less and write voltage amplification during each programming is less, thus the electric charge in grid is mended and is caught the amount of electrons of layer and can be controlled more accurately.Base this, use the memory element of the entity erased cell of the system area 506 that first group of program parameters program can be programmed to more correctly state, thus can be effectively prevented from reading the generation of interference.

Refer to Figure 19, similarly, owing to the entity erased cell in transient area 508 is to operate with cut-forms mode, therefore, the grid voltage of memory element only needs to be divided into two kinds of storage states.Particularly, relative to first group of program parameters, owing to the second incremental step pulse program adjusted value of second group of program parameters is bigger, therefore, when memorizer control circuit unit 104 (or memory management circuitry 202) uses second group of program parameters to write/verify, by pulse, the entity erased cell that data are programmed to transient area 508 by critical voltage method, memory element just can complete the write of data under the programming operation of fewer number by the checking of verifying voltage.Entity erased cell relative to system area 506, owing to the entity erased cell in transient area 508 just can complete the write of data under the programming operation of fewer number, therefore, programming operation is relatively low for the influence degree of the entity erased cell in transient area 508.Particularly, owing to transient area 508 is for temporal data, therefore, the entity erased cell in transient area 508 can be programmed continually, therefore, use second group of program parameters that the second incremental step pulse program adjusted value is bigger, can effectively extend the life-span of the entity erased cell in transient area 508.

Must being appreciated that, Figure 16～Figure 19 adjusts first group of program parameters to produce the example of second group of program parameters, the invention is not restricted to this.In other exemplary embodiment, the first incremental step pulse program adjusted value of memorizer control circuit unit 104 (or memory management circuitry 202) first group of program parameters of adjustable, first be originally written into voltage, the first verifying voltage, the first read voltage, the first conducting voltage with first erase at least one of voltage obtaining the second incremental step pulse program adjusted value of second group of program parameters, second be originally written into voltage, the second verifying voltage, the second read voltage, the second conducting voltage are erased voltage with second.

Refer to Figure 20, in step S2001, memorizer control circuit unit 104 (or memory management circuitry 202) can receive the data being intended to storage.Such as, memory storage apparatus 100 can receive the data into instruction with this instruction corresponding from host computer system 1000, and wherein write instruction will indicate that the logical address storing these data.

In step S2003, memorizer control circuit unit 104 (or memory management circuitry 202) can judge whether received data belongs to the secondary sources of entity erased cell being intended to be written into the secondth district (such as, above-mentioned transient area 508).Such as, in this exemplary embodiment, the logical block configured is to map to the entity erased cell of data field 502, therefore, when received data is the logical block extremely configured to be stored, memorizer control circuit unit 104 (or memory management circuitry 202) can identify that received data is belonging to first to do the secondary sources kept in transient area 508.

If (namely received data is not belonging to secondary sources, belong to and be intended to be written into the firstth district (such as, said system 506) the primary sources of entity erased cell) time, in step S2005, memorizer control circuit unit 104 (or memory management circuitry 202) can use first group of program parameters by least one the entity erased cell (hereinafter referred to as first instance erased cell) among these data write to the entity erased cell in the firstth district.

If received data belongs to secondary sources, in step S2007, memorizer control circuit unit 104 (or memory management circuitry 202) can use second group of program parameters by least one the entity erased cell (hereinafter referred to as second instance erased cell) among these data write to the entity erased cell in the secondth district.

As mentioned above, the entity erased cell in system area 506 and transient area 508 is to operate with cut-forms mode, but, in this exemplary embodiment, reproducible nonvolatile memorizer module 106 can use multilayered memory unit mode to erase instruction for TLCNAND type flash memory and all entity erased cell before being written into data.That is, in this exemplary embodiment, although the entity erased cell in system area 506 and transient area 508 is to store 3 Bit datas, but memorizer control circuit unit 104 (or memory management circuitry 202) can use above-mentioned first group of program parameters to carry out the entity erased cell in operating system district 506 and transient area 508 with second group of program parameters, thus only use its lower entity programming unit.

It is worth mentioning that, in another example of the present invention is implemented, memorizer control circuit unit 104 (or memory management circuitry 202) also can before writing data to the entity erased cell of system area 506, the monolayer memory element mode instruction entity erased cell to system area 506 of erasing is used to erase operation, so that the entity erased cell of system area 506 is only capable of depositing the data of 1 bit.Particularly, at this under operation, the data of the entity erased cell being stored in system area 506 can be more stable and reliable.Such as, in this example, above-mentioned first instance erased cell is before being written into data, memorizer control circuit unit 104 (or memory management circuitry 202) can use the instruction of erasing of monolayer memory element mode to perform to erase operation to first instance erased cell, and above-mentioned second instance erased cell is before being written into data, memorizer control circuit unit 104 (or memory management circuitry 202) can use the instruction of erasing of multilayered memory unit mode to perform to erase operation to second instance erased cell.

In sum, the proposed memory cell programming method of exemplary embodiment of the present invention, memorizer control circuit unit and memory storage apparatus are according to being all that the system area with cut-forms mode operation uses different program parameters to carry out memory cells with the different storage demands of relief area, the data being stored in system area thus can be avoided to occur to read interference, avoid the entity erased cell rapid degradation in transient area simultaneously.

Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to foregoing embodiments, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein some or all of technical characteristic is carried out equivalent replacement；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.

Claims

1. a memory cell programming method, for a reproducible nonvolatile memorizer module, it is characterized in that, this reproducible nonvolatile memorizer module has multiple entity erased cell, those entity erased cell each have multiple entity programming unit, and this memory cell programming method includes:

Use one first group of program parameters that one primary sources write one of them the entity programming unit among those entity programming units；And

Use one second group of program parameters by one of them the entity programming unit among a secondary sources write to those entity programming units,

Wherein in this first group of program parameters, at least part of parameter differs in this second group of program parameters, and the data bit number writing the memory element of this one of them entity programming unit of these primary sources with this first group of program parameters is same as the data bit number of memory element of this one of them the entity programming unit writing these secondary sources with this second group of program parameters.

2. memory cell programming method according to claim 1, it is characterized in that, write the entity programming unit of these secondary sources among those entity programming units and map a corresponding logical address, and write the entity programming unit of these primary sources without mapping a corresponding logical address.

3. memory cell programming method according to claim 1, it is characterized in that, the data bit number that the data bit number writing the memory element of this one of them entity programming unit of these primary sources with this first group of program parameters is 1 bit and the memory element of this one of them the entity programming unit writing these secondary sources with this second group of program parameters is 1 bit.

4. memory cell programming method according to claim 3, it is characterised in that also include:

Those entity erased cell are at least grouped into one first district and one second district；

The step that these primary sources are write one of them the entity programming unit among those entity programming units by this first group of program parameters is wherein used to include: to use this first group of program parameters by these primary sources write to the entity erased cell belonging to this firstth district

The step that these secondary sources are write one of them the entity programming unit among those entity programming units by this second group of program parameters is wherein used to include: to use this second group of program parameters by these secondary sources write to the entity erased cell belonging to this secondth district.

5. memory cell programming method according to claim 4, it is characterised in that those entity programming units of those entity erased cell each include multiple lower entity programming unit and multiple upper entity programming units,

Wherein this first group of program parameters is preset the entity erased cell for belonging to this firstth district, and wherein the upper entity programming unit of the entity erased cell in this firstth district will not be used to storage data；

Wherein this second group of program parameters is for belonging to the entity erased cell in this secondth district, and the upper entity programming unit of the entity erased cell in this secondth district will not be used to storage data.

6. memory cell programming method according to claim 5, it is characterised in that also include:

Adjust this first group of program parameters to obtain this second group of program parameters.

7. memory cell programming method according to claim 4, it is characterised in that also include:

Receive data；

Judge whether these data belong to these secondary sources；

If these data are not belonging to these secondary sources, this first group of program parameters is used to write the data at least one first instance erased cell to those entity erased cell in this firstth district；And

If these data belong to these secondary sources, this second group of program parameters is used to write the data at least one second instance erased cell to those entity erased cell in this secondth district.

8. memory cell programming method according to claim 7, it is characterised in that also include:

Identify at least one logical block being intended to store these data；

Judge whether this at least one logical block maps to those entity erased cell in this secondth district；And

If this at least one logical block is those entity erased cell mapping to this secondth district, identify that these data are belonging to this secondary sources.

9. memory cell programming method according to claim 7, it is characterised in that also include:

A monolayer memory element mode is used to erase instruction to this at least one first instance erased cell execution one brush division operation；And

Use multilayered memory unit mode instruction of erasing that this at least one second instance erased cell is performed this operation of erasing.

10. memory cell programming method according to claim 1, it is characterized in that, this first group of program parameters includes one first incremental step pulse program adjusted value, one first is originally written into voltage, one first verifying voltage, one first read voltage, one first conducting voltage are erased at least one of voltage with one first.

11. memory cell programming method according to claim 1, it is characterized in that, the data retention of the entity programming unit programmed with this first group of program parameters among those entity programming units or anti-reading interference performance are better than the data retention of the entity programming unit with this second group of program parameters programming or anti-reading interference performance.

12. memory cell programming method according to claim 1, it is characterised in that be better than the life-span of the entity programming unit programmed with this first group of program parameters among those entity programming units with the life-span of the entity programming unit of this second group of program parameters programming.

13. memory cell programming method according to claim 1, it is characterized in that, with the voltage spacing between the first state more than the threshold voltage statistical Butut of the memory element of the entity programming unit with this second group of program parameters programming of the voltage spacing between the first state of the threshold voltage statistical Butut of the memory element of the entity programming unit of this first group of program parameters programming and the second state and the second state among those entity programming units.

14. memory cell programming method according to claim 9, it is characterised in that adjust this first group of program parameters and include with the step obtaining this second group of program parameters:

One first verifying voltage adjusting this first group of program parameter is used as one second verifying voltage of this second group of program parameter to obtain a voltage,

Wherein this first verifying voltage of this first group of program parameter is more than this second verifying voltage of this second group of program parameter.

15. memory cell programming method according to claim 9, it is characterised in that adjust this first group of program parameters and include with the step obtaining this second group of program parameters:

The one first incremental step pulse program adjusted value adjusting this first group of program parameter is used as one second incremental step pulse program adjusted value of this second group of program parameter to obtain a value,

Wherein this first incremental step pulse program adjusted value of this first group of program parameter is less than this second incremental step pulse program adjusted value of this second group of program parameter.

16. memory cell programming method according to claim 7, it is characterised in that these primary sources are a firmware code and this firstth district is independently in order to store a system area of this firmware code,

The transient area that wherein these secondary sources are user data and this secondth district is these user data temporary.

17. memory cell programming method according to claim 4, it is characterised in that also include:

Use this first group of parameter that storage has the entity programming unit of these primary sources perform one brush division operation；And

This second group of parameter is used to have the entity programming unit of these secondary sources to perform this operation of erasing storage.

18. a memorizer control circuit unit, it is used for accessing a reproducible nonvolatile memorizer module, it is characterised in that this memorizer control circuit unit includes:

One HPI, is electrically connected to a host computer system；

One memory interface, is electrically connected to this reproducible nonvolatile memorizer module, and wherein this reproducible nonvolatile memorizer module has multiple entity erased cell, and those entity erased cell each have multiple entity programming unit；And

One memory management circuitry, is electrically connected to this HPI and this memory interface,

Wherein this memory management circuitry uses one first group of program parameters one primary sources write one of them the entity programming unit among those entity programming units and uses one second group of program parameters by one of them the entity programming unit among a secondary sources write to those entity programming units

Wherein in this first group of program parameters, at least part of parameter differs in this this second group of program parameters, and the data bit number writing the memory element of this one of them entity programming unit of these primary sources with this first group of program parameters is same as the data bit number of memory element of this one of them the entity programming unit writing these secondary sources with this second group of program parameters.

19. memorizer control circuit unit according to claim 18, it is characterized in that, write the entity programming unit of these secondary sources among those entity programming units and map a corresponding logical address, and write the entity programming unit of these primary sources without mapping a corresponding logical address.

20. a memory storage apparatus, it is characterised in that including:

One connects interface unit, is electrically connected to a host computer system；

One reproducible nonvolatile memorizer module, wherein this reproducible nonvolatile memorizer module has multiple entity erased cell, and those entity erased cell each have multiple entity programming unit；And

One memorizer control circuit unit, is electrically connected to this connection interface unit and this reproducible nonvolatile memorizer module,

Wherein this memorizer control circuit unit uses one first group of program parameters one primary sources write one of them the entity programming unit among those entity programming units and uses one second group of program parameters by one of them the entity programming unit among a secondary sources write to those entity programming units

21. memory storage apparatus according to claim 20, it is characterized in that, write the entity programming unit of these secondary sources among those entity programming units and map a corresponding logical address, and write the entity programming unit of these primary sources without mapping a corresponding logical address.

22. memory storage apparatus according to claim 20, it is characterized in that, the data bit number that the data bit number writing the memory element of this one of them entity programming unit of these primary sources with this first group of program parameters is 1 bit and the memory element of this one of them the entity programming unit writing these secondary sources with this second group of program parameters is 1 bit.

23. memory storage apparatus according to claim 22, it is characterised in that those entity erased cell are at least grouped into one first district and one second district by this memorizer control circuit unit,

Wherein this first group of program parameters is being used to write in the operation of one of them the entity programming unit among those entity programming units by these primary sources, this memorizer control circuit unit uses this first group of program parameters by these primary sources write to the entity erased cell belonging to this firstth district

Wherein using this second group of program parameters to write in the operation of one of them the entity programming unit among those entity programming units by these secondary sources, this memorizer control circuit unit uses this second group of program parameters by these secondary sources write to the entity erased cell belonging to this secondth district.

24. memory storage apparatus according to claim 23, it is characterized in that, this first group of program parameters is preset the entity erased cell for belonging to this firstth district, and the upper entity programming unit of the entity erased cell in this firstth district will not be used to storage data；

25. memory storage apparatus according to claim 24, it is characterised in that this memorizer control circuit unit adjusts this first group of program parameters to obtain this second group of program parameters.

26. memory storage apparatus according to claim 25, it is characterised in that this memorizer control circuit unit receives data, and judges whether these data belong to these secondary sources,

If these data are not belonging to these secondary sources, this memorizer control circuit unit uses this first group of program parameters to write the data at least one first instance erased cell to those entity erased cell in this firstth district,

If these data belong to these secondary sources, this memorizer control circuit unit uses this second group of program parameters to write the data at least one second instance erased cell to those entity erased cell in this secondth district.

27. memory storage apparatus according to claim 25, it is characterized in that, this memorizer control circuit unit identification is intended to store at least one logical block of these data, and judges whether this at least one logical block maps to those entity erased cell in this secondth district

If this at least one logical block is those entity erased cell mapping to this secondth district, these memorizer control circuit these data of unit identification are belonging to this secondary sources.

28. memory storage apparatus according to claim 26, it is characterized in that, this memorizer control circuit unit uses monolayer memory element mode instruction of erasing that this at least one first instance erased cell performs one brush division operation, and this at least one second instance erased cell is performed this operation of erasing by the instruction of erasing of the multilayered memory unit mode of use.

29. memory storage apparatus according to claim 20, it is characterized in that, this first group of program parameters includes one first incremental step pulse program adjusted value, one first is originally written into voltage, one first verifying voltage, one first read voltage, one first conducting voltage are erased at least one of voltage with one first.

30. memory storage apparatus according to claim 25, it is characterized in that, adjusting this first group of program parameters to obtain in the operation of this second group of program parameters, this memorizer control circuit unit adjusts one first verifying voltage of this first group of program parameter and is used as one second verifying voltage of this second group of program parameter to obtain a voltage, and wherein this first verifying voltage of this first group of program parameter is more than this second verifying voltage of this second group of program parameter.

31. memory storage apparatus according to claim 25, it is characterized in that, adjusting this first group of program parameters to obtain in the operation of this second group of program parameters, this memorizer control circuit unit adjusts one first incremental step pulse program adjusted value of this first group of program parameter and is used as one second incremental step pulse program adjusted value of this second group of program parameter to obtain a value, and wherein this first incremental step pulse program adjusted value of this first group of program parameter is less than this second incremental step pulse program adjusted value of this second group of program parameter.

32. memory storage apparatus according to claim 23, it is characterised in that these primary sources are a firmware code and this firstth district is independently in order to store a system area of this firmware code,

33. memory storage apparatus according to claim 20, it is characterized in that, this memorizer control circuit unit use this first group of parameter to storage have these primary sources those entity programming units one of them perform one brush division operation, and use this second group of parameter to storage have these secondary sources those entity programming units one of them perform this operation of erasing.

34. memory storage apparatus according to claim 20, it is characterized in that, the data retention of the entity programming unit programmed with this first group of program parameters among those entity programming units or anti-reading interference performance are better than the data retention of the entity programming unit with this second group of program parameters programming or anti-reading interference performance.

35. memory storage apparatus according to claim 20, it is characterised in that be better than the life-span of the entity programming unit programmed with this first group of program parameters among those entity programming units with the life-span of the entity programming unit of this second group of program parameters programming.

36. memory storage apparatus according to claim 20, it is characterized in that, with the voltage spacing between the first state more than the threshold voltage statistical Butut of the memory element of the entity programming unit with this second group of program parameters programming of the voltage spacing between the first state of the threshold voltage statistical Butut of the memory element of the entity programming unit of this first group of program parameters programming and the second state and the second state among those entity programming units.