CN113628659B - Erasing method, device and computer readable storage medium - Google Patents
Erasing method, device and computer readable storage medium Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
Abstract
The application discloses an erasing method, which comprises the following steps: erasing the memory units in the memory block once; searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set corresponding to the memory cells in the memory block; determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage; applying the first erasing voltage to the memory cells in the memory block, and performing second erasing to change the threshold voltage range of the memory cells from the first threshold voltage range after one erasing to an initial threshold voltage range; the preset check voltage sets corresponding to different memory cells in the memory block are different.
Description
The application relates to a filing application of Chinese patent application with the application date of 2018, month 08 and 28, the application number of 201810991139.5 and the application name of 'an erasing method, an erasing device and a computer-readable storage medium'.
Technical Field
The present application relates to the field of computer technologies, and in particular, to an erasing method, an erasing device, and a computer readable storage medium.
Background
Nonvolatile memories such as computer flash memories have the property of storing data without power supply and have erasing and writing functions, and are widely used in various electronic products, but the erasing performance is not receiving much attention.
When the nonvolatile memory is erased, the erasing operation can be completed only by erasing five times. In the erasing process, the normal running of random access is affected due to the fact that the erasing time is long and the erasing action cannot be suspended, so that the access performance is affected.
Therefore, it is desirable to find a solution that can shorten the erase time.
Disclosure of Invention
In view of the foregoing, it is desirable to provide an erasing method, an erasing apparatus and a computer readable storage medium, which can shorten the erasing time.
The technical scheme of the embodiment of the application is realized as follows:
the embodiment of the application provides an erasing method, which comprises the following steps:
erasing the memory units in the memory block once;
searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set;
determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage;
and applying the first erasing voltage to the memory cells in the memory block, and performing second erasing so as to change the threshold voltage range of the memory cells from the first threshold voltage range after one erasing to the initial threshold voltage range.
In the above scheme, the erasing the memory cells in the memory block once includes:
pre-programming the memory units in the memory block; taking the pre-programmed storage unit as a storage unit to be erased in the storage block;
correspondingly, the one-time erasing of the storage units in the storage block comprises one-time erasing of the storage units to be erased in the storage block.
In the above solution, the searching the first verification voltage from the preset verification voltage set to enable the memory cells in the memory block to pass the verification includes:
searching an ith check voltage from a preset check voltage set, and applying the ith check voltage to a storage unit in the storage block to perform one-time check; judging whether a storage unit in the storage block passes the verification or not;
when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on;
taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage;
wherein i=1, 3,5, … N, N being a positive integer.
In the above scheme, the determining, by using the first verification voltage, a first erase voltage for performing a second erase on the memory cells in the memory block includes:
determining a voltage difference between the first verification voltage and a preset initial verification voltage;
obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells in the memory block are erased once;
and taking the sum of the obtained voltages as a first erasing voltage for performing second erasing on the memory cells in the memory block.
In the above scheme, the erasing the memory cells in the memory block once includes:
determining an initial erase voltage;
and applying the initial erasing voltage to the memory cells in the memory block, and performing first erasing so as to change the threshold voltage range of the memory cells into a first threshold voltage range.
In the above aspect, before the determining the initial erase voltage, the method further includes:
determining a storage block to be processed;
pre-programming the memory cells in the memory block to change the threshold voltage range of the memory cells from an initial threshold voltage range to a second threshold voltage range after pre-programming;
accordingly, the method for changing the threshold voltage range of the memory cell to the first threshold voltage range includes:
so that the threshold voltage range of the memory cell is changed from the second threshold voltage range after the pre-programming to the first threshold voltage range after the first erasing.
The embodiment of the application provides an erasing device, which comprises:
the erasing module is used for erasing the storage units in the storage block once;
the searching module is used for searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set;
the determining module is used for determining a first erasing voltage for erasing the memory cells in the memory block for the second time by utilizing the first checking voltage;
the erasing module is further configured to apply the first erasing voltage to the memory cells in the memory block, and perform a second erasing, so that the threshold voltage range of the memory cells is changed from the first threshold voltage range after one erasing to the initial threshold voltage range.
In the above scheme, the searching module is specifically configured to search an ith verification voltage from a preset verification voltage set, apply the ith verification voltage to a memory cell in the memory block, and perform a primary verification; judging whether a storage unit in the storage block passes the verification or not; when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on; taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage; wherein i=1, 3,5, … N, N being a positive integer.
In the above scheme, the determining module is specifically configured to determine a voltage difference between the first verification voltage and a preset initial verification voltage; obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells in the memory block are erased once; and taking the sum of the obtained voltages as a first erasing voltage for performing second erasing on the memory cells in the memory block.
Embodiments of the present application provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of any of the above-described erasure methods.
An embodiment of the present application provides an erasing apparatus, including: a memory, a processor, and a computer program stored on the memory and executable on the processor;
wherein the processor is configured to perform the steps of any of the above-described methods of erasing when the computer program is run.
The erasing method, the erasing device and the computer readable storage medium provided by the embodiment of the application erase the storage units in the storage block once; searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set; determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage; and applying the first erasing voltage to the memory cells in the memory block, and performing second erasing so as to change the threshold voltage range of the memory cells from the first threshold voltage range after one erasing to the initial threshold voltage range. In the embodiment of the application, after the first erasing is performed on the memory cells in the memory block, the first erasing voltage is applied to the memory cells in the memory block, and after the second erasing is performed, the threshold voltage range of the memory cells can be changed from the first threshold voltage range after one-time erasing to the initial threshold voltage range directly. Obviously, the threshold voltage range of the memory cells in the memory block can be changed into the initial threshold voltage range by erasing the memory cells twice, so that the erasing time is shortened.
In addition, since the threshold voltage range of the memory cell is changed to the initial threshold voltage range by erasing twice, the random access can be normally performed by shortening the erasing time, thereby improving the access performance.
Drawings
FIG. 1 is a flow chart of a related art erase operation performed on memory cells in a memory block;
FIG. 2 is a diagram illustrating the threshold voltage ranges of memory cells during an erase process in the related art;
FIG. 3 is a flow chart of an erasing method according to an embodiment of the application;
FIG. 4 is a flowchart illustrating an embodiment of an erase method according to the present application;
FIG. 5 is a schematic diagram of threshold voltages of memory cells in a memory block during an erase process according to an embodiment of the present application;
FIG. 6 is a schematic diagram of an erasing apparatus according to an embodiment of the present application;
FIG. 7 is a schematic diagram showing a second structure of an erasing apparatus according to an embodiment of the present application.
Detailed Description
In the related art, when a new Mobile flash Memory (MNAND) or a solid-state memory is used, the erase performance of the flash memory device is not receiving much attention. For example, in the erasing process, the erasing time is long and the erasing action cannot be suspended, so that the normal random access is affected. In addition, when the remaining space of the disk is smaller and smaller, the erasure time caused by the high occurrence rate of the folding or recycling operation of the data is longer, which affects the performance of the sequence or random access; the folding operation of the data means that the data storage is realized by programming one storage unit for a plurality of times; the data reclamation operation refers to the concentrated erasure of discarded data in memory cells that have been written with data but have not been erased.
Fig. 1 is a flowchart of a related art process for performing an erase operation on memory cells in a memory block, as shown in fig. 1, including the following steps:
step 101: the control unit of the memory preprogrammes the memory cells in the memory block.
Here, before erasing the memory cells in the memory block, pre-programming is required, mainly considering that some memory cells may have been written with data, some memory cells may not have been written with any data, erasing the memory cells written with data will not have any adverse effect on the corresponding memory cells, but erasing the memory cells not written with data will have over-erasing, and further damage the memory cells.
Step 102: the control unit determines an erase voltage for the current erase.
The erase voltage may be calculated according to equation (1), equation (1) as follows:
V＝PWELL+stepNO×stepsize (1)
wherein PWELL represents an initial erase voltage, which is a preset value, such as 16V; stepNO indicates the number of erasures; the step represents a first preset step size, and is not set too large, such as 1V, for better erasing effect; stepno×stepsize represents the lifting voltage.
Table 1 is the correspondence of the initial erase voltage, the lift voltage, and the erase voltage. Wherein the erase voltage is obtained according to formula (1). Assuming that PWELL is 16V and step is 1V, the first time of erasing, the lifting voltage=0×1=1v, the erasing voltage v=16+0×1=16v; then in the second erase, the lifting voltage=1×1=1v, the erase voltage v=16+1×1=17v; then in the third erase, the lifting voltage=2×1=2v, the erase voltage v=16+2×1=18v; then for the fourth erase, the lifting voltage=3×1=3v, the erase voltage v=16+3×1=19v; then the fifth erase, the lifting voltage=4×1=4v, the erase voltage v=16+4×1=20v.
| Initial erase voltage | Lifting voltage | Erase voltage | |
| First erase | 16V | 0V | 16V |
| Second erasure | 16V | 1V | 17V |
| Third erasure | 16V | 2V | 18V |
| Fourth time erase | 16V | 3V | 19V |
| Fifth erasure | 16V | 4V | 20V |
TABLE 1
Step 103: and the control unit applies an erasing voltage for erasing the memory cells in the memory block at the current time through a word line to erase the memory cells.
Step 104: after this erase, a verify voltage of 0V is applied to the gate of the memory cell.
Step 105: judging whether the verification is passed or not according to the verification voltage and the initial threshold voltage range of the storage unit; ending the erasing operation when the verification is passed; when the verification fails, step 102 is performed.
FIG. 2 is a schematic diagram of threshold voltages of memory cells during erasing in the related art, wherein the abscissa represents threshold voltages of memory cells and the ordinate represents distribution of memory cells as shown in FIG. 2; assuming that after shipping, the initial threshold voltage range of the memory cell is (-1, -0.2V); after the memory cells are pre-programmed according to the steps shown in fig. 1, it is apparent that 5 erase operations are required for the memory cells in the memory block to change the threshold voltage range of the memory cells to the initial threshold voltage range, assuming that the threshold voltage of the memory cells is above 4V. Excessive erase time, plus the inability to suspend erase operations during erase, will affect the normal performance of random access.
Based on the above, in the embodiment of the application, the memory cells in the memory block are erased once; searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set; determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage; and applying the first erasing voltage to the memory cells in the memory block, and performing second erasing so as to change the threshold voltage range of the memory cells from the first threshold voltage range after one erasing to the initial threshold voltage range.
So that the manner in which the features and aspects of the embodiments of the present application can be understood in more detail, a more particular description of the application, briefly summarized below, may be had by reference to the appended drawings, which are merely illustrative, and not intended to be limiting of the application.
As shown in fig. 3, an erasing method according to an embodiment of the present application is applied to a three-dimensional (3D,three Dimensional) NAND (NAND) memory, and includes the steps of:
step 301: and erasing the memory cells in the memory block once.
The 3D NAND is composed of a memory cell array; the memory cell array includes a plurality of memory cell strings; each memory cell string includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns. The directions corresponding to the columns are Z directions, namely the arrangement directions of the memory cell strings; the directions corresponding to the rows are X directions, namely word line directions; the direction perpendicular to the Z direction is the Y direction, i.e., the bit line direction.
Wherein the memory block may be composed of a plurality of memory cell strings, such as 6 memory cell strings; each memory cell string includes a plurality of memory cells, such as 128 memory cells; the plurality of memory cells may be arranged in a plurality of rows and a plurality of columns. The 3D NAND may include a control unit and a storage unit; the control unit can be a control unit in the 3D NAND, or can be a control unit arranged outside the 3D NAND; the storage unit is used for storing data; the control unit is capable of programming and erasing a memory block in the 3D NAND, and a threshold voltage of a memory cell in the memory block may be changed within a certain range during the programming and erasing.
In one embodiment, the erasing the memory cells in the memory block once includes: determining an initial erase voltage; and applying the initial erasing voltage to the memory cells in the memory block, and performing first erasing so as to change the threshold voltage range of the memory cells in the memory block into a first threshold voltage range.
The method comprises the steps of taking a storage block as a unit to erase, namely erasing all storage units in the storage block; the initial erase voltage is a predetermined value, such as 16V.
In an embodiment, before the determining the initial erase voltage, the method further comprises: determining a storage block to be processed; the memory cells in the memory block are pre-programmed to change the threshold voltage range of the memory cells from an initial threshold voltage range to a pre-programmed second threshold voltage range. The starting voltage of the second threshold voltage range is a turn-on voltage of the memory cell.
Here, the control unit may determine the memory block to be processed through the word line, the bit line.
In order to erase all the memory cells in the memory block, the memory cells in the memory block need to be pre-programmed before erasing, so that over-erasing of partial memory cells which are not written with data when erasing voltages are applied to all the memory cells in the memory block at the same time can be avoided.
Here, after the memory block memory cells are pre-programmed, the threshold voltage range of the memory cells is changed from the initial threshold voltage range to the second threshold voltage range after the pre-programming.
Step 302: searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set; and determining a first erasing voltage for performing second erasing on the memory cells of the memory block by using the first checking voltage.
Wherein the preset check voltage set comprises at least one voltage value; the minimum voltage value of the at least one voltage value, namely the initial verification voltage, can be set by a user according to the process of the memory cell; the indication of the maximum voltage value of the one voltage value may be set by a user according to the turn-on voltage of the memory cell; when the preset check voltage set includes a plurality of voltage values, the step value between every two adjacent voltage values is equal to a second preset step, for example, 1V. The preset check voltage sets corresponding to different memory cells in the memory block may be the same or different.
For example, assume that the turn-on voltages of the memory cells 1, 2 are 4V; for the memory cell 1, setting the initial verification voltage to be 0V, and taking the initial verification voltage as a first voltage value in a preset verification voltage set, and based on a second preset step value of 1V, obtaining the preset verification voltage set as follows: {0V,1V,2V,3V,4V }; for the memory cell 2, the initial verification voltage is set to be 1V, and the initial verification voltage is used as a first voltage value in a preset verification voltage set, and based on the second preset step value of 1V, the preset verification voltage set can be obtained as follows: {1V,2V,3V,4V }.
In an embodiment, the searching the first verification voltage from the preset verification voltage set to enable the memory cells in the memory block to pass verification includes: searching an ith check voltage from a preset check voltage set, and applying the ith check voltage to a storage unit in the storage block to perform one-time check; judging whether a storage unit in the storage block passes the verification or not; when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on; taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage; wherein i=1, 3,5, … N, N being a positive integer.
Here, verification is performed in units of memory cell strings in the memory block.
In order to avoid the situation that the next erasing operation is immediately performed when the verification is failed by using one verification voltage, so that the erasing times are excessive, the verification voltage which enables the memory cells in the memory block to pass the verification can be searched from a preset verification voltage set.
In actual application, when the first verification is performed, the 1 st verification voltage, namely the initial verification voltage, can be searched from a preset verification voltage set; applying the initial verification voltage to each memory cell in the memory cell string to perform primary verification; detecting a current flowing through the memory cell string; when the detected current is larger than the reference current, determining that each storage unit passes verification, and taking the corresponding verification voltage as a first verification voltage; otherwise, based on the initial check voltage and a second preset step length, the lifted check voltage is obtained; and performing second verification on the storage units in the storage block based on the lifted verification voltage.
Applying the raised verification voltage to each storage unit in the storage unit string when performing the second verification; detecting a current flowing through the memory cell string; when the detected current is larger than the reference current, determining that each storage unit passes verification; otherwise, based on a second preset step length, lifting the lifted check voltage to serve as the check voltage of the next check.
And the like, through repeated verification, the verification voltage which enables the memory cells in the memory block to pass the verification can be searched, and the verification voltage which passes the verification is used as a first verification voltage.
In one embodiment, the determining the first erase voltage for performing the second erase on the memory block memory cells using the first verify voltage includes: determining a voltage difference between the first verification voltage and a preset initial verification voltage; obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells of the memory block are erased once; and taking the obtained voltage and the first erasing voltage as a first erasing voltage for erasing the memory cells of the memory block for the second time.
In order to avoid performing excessive times of cyclic erase operation on the memory cell, the initial erase voltage is raised by using the voltage difference between the first verify voltage and a preset initial verify voltage, so as to obtain a first erase voltage for second erase. After the first erasing voltage is applied to all the memory cells in the memory block, the erasing operation of the memory block can be directly completed, that is, the threshold voltage range of the memory cells in the memory block is changed into the initial threshold voltage range, obviously, the excessive times of cyclic erasing operation can be avoided, and the erasing time is reduced.
Step 303: and applying the first erasing voltage to the memory cells in the memory block, and performing second erasing so as to change the threshold voltage range of the memory cells from the first threshold voltage range after one erasing to the initial threshold voltage range.
In practical application, the first erasing voltage can be applied to all the memory cells in the memory block through the control unit in the 3D NAND, so that the movement of charges stored in the memory cells to the substrate direction is accelerated, and the threshold voltage range of the memory cells can be changed into the initial threshold voltage range directly.
It should be noted that, the erasing method provided by the embodiment of the present application may be implemented by a state machine or firmware (firmware) in 3D NAND.
By adopting the technical scheme of the embodiment of the application, after the memory cells in the memory block are subjected to the first erasure, the first erasure voltage is applied to the memory cells in the memory block, and after the memory cells are subjected to the second erasure, the threshold voltage range of the memory cells can be changed from the first threshold voltage range after the first erasure to the initial threshold voltage range. Obviously, the threshold voltage range of the memory cells can be changed into the initial threshold voltage range by erasing the memory cells of the memory block twice, so that the erasing time is shortened.
In addition, since the threshold voltage range of the memory cell is changed to the initial threshold voltage range by erasing twice, the random access can be normally performed by shortening the erasing time, thereby improving the access performance.
The following describes the specific implementation procedure and principle of the erasing method according to the embodiment of the present application in detail by taking the specific embodiment as an example.
Fig. 4 is a schematic flow chart of a specific implementation of the erasing method according to the embodiment of the present application, as shown in fig. 4, taking erasing a 3D NAND as an example, specifically including the following steps:
step 401: the control unit of the 3D NAND preprogrammes the memory cells in the memory block.
Here, before erasing the memory cells in the memory block, pre-programming is required, mainly considering that some memory cells may have been written with data, some memory cells may not have been written with any data, erasing the memory cells written with data will not have any adverse effect on the corresponding memory cells, but erasing the memory cells not written with data will have over-erasing, and further damage the memory cells.
Step 402: the control unit determines an erase voltage for the current erase.
The erase voltage at the first erase is calculated according to equation (1) in step 102, assuming that PWELL is 16V and step is 1V, the erase voltage at the first erase v=16+0×1=16v. The erase voltage at the time of the second erase is calculated according to formula (2).
The erase voltage at the second erase is calculated according to formula (2), formula (2) being as follows:
V＝PWELL+(Vtop-EV)＝PWELL+Vdelta (2)
where PWELL represents an initial erase voltage; vdelta=vtop-EV, vtop represents a first verify voltage that causes the memory cells in the memory block to pass the verify, EV represents an initial verify voltage, and is a preset value.
Table 2 is the correspondence between the erase voltage and the verify voltage. Wherein the erase voltage at the second erase is obtained according to formula (2). In the second erasing, if PWELL is 16V, the initial verify voltage is 0V, and the first verify voltage obtained by multiple verifications is 4V, vdelta=4-0=4v, and the erase voltage v=16+4=20v in the second erasing.
| Initial erase voltage | Check voltage set | Erase voltage | |
| Second erasure | 16V | {0V，1V，2V，3V，4V} | 20V |
TABLE 2
Step 403: and the control unit applies an erasing voltage when erasing the memory cells in the memory block for the current time to erase the memory cells.
And erasing by taking the memory block as a unit, namely, the control unit applies an erasing voltage on the substrates of all the memory cells in the memory block to erase.
Step 404: after the erasing, the control unit applies a check voltage, namely 0V, to the memory cells in the memory block.
The verification is performed in units of memory cell strings in a memory block, i.e., the control unit applies an initial verification voltage to gates of respective memory cells in the memory cell strings of the memory block through Word Lines (WL). The initial verification voltage is preset by a user, such as 0V or 1V, etc.
Step 405: judging whether the verification is passed or not; ending the erasing operation when the verification is passed; when the check fails, step 406 is performed.
Detecting a current flowing through the memory cell string; when the detected current is larger than the reference current, determining that the memory cells in the memory block pass the verification, and ending the erasing operation; otherwise, step 406 is performed.
Step 406: and lifting the verification voltage based on the second preset step length to obtain the verification voltage of the next verification, and executing step 407.
Step 407: judging whether the verification is passed or not; when the verification passes, step 402 is performed; otherwise, step 406 is performed.
FIG. 5 is a schematic diagram showing a change in threshold voltage of memory cells of a memory block during an erase process according to an embodiment of the present application, wherein an abscissa indicates threshold voltage of memory cells and an ordinate indicates distribution of memory cells as shown in FIG. 5; assuming that after shipping, the initial threshold voltage range of the memory cell is (-1, -0.2V); after the memory cell is pre-programmed according to the erase flow shown in fig. 4, the threshold voltage of the memory cell is above 4V; performing 2 erase operations on memory cells of a memory block can change the threshold voltage range of the memory cells to the initial threshold voltage range. The period of the erasing voltage is 914us, the period of the verification voltage is 65us, the memory block comprises 6 memory cell strings, and the total time of the erasing time and the verification time is 4168us.
In the related art, the total time of the erasing time and the checking time is 6520us, and the erasing times are 5 times, and obviously, the embodiment of the application can shorten the erasing time, thereby ensuring the normal running of random access and further improving the access performance.
Based on the erasing method provided by each embodiment of the present application, an embodiment of the present application further provides an erasing apparatus, as shown in fig. 6, where the apparatus includes:
an erasing module 61, configured to erase the memory cells in the memory block once;
the searching module 62 is configured to search a preset check voltage set for a first check voltage that enables the memory cells in the memory block to pass the check;
a determining module 63, configured to determine a first erase voltage for performing a second erase on the memory cells in the memory block using the first verify voltage;
the erasing module 61 is further configured to apply the first erase voltage to the memory cells in the memory block, and perform a second erase, so that the threshold voltage range of the memory cells is changed from the first threshold voltage range after one erase to the initial threshold voltage range.
In one embodiment, the erase module 61 is specifically configured to determine an initial erase voltage; and applying the initial erasing voltage to the memory cells in the memory block, and performing first erasing so as to change the threshold voltage range of the memory cells in the memory block into a first threshold voltage range.
The apparatus further comprises: a pre-programming module; wherein,
the pre-programming module is used for determining a storage block to be processed; the memory cells in the memory block are pre-programmed to change the threshold voltage range of the memory cells from an initial threshold voltage range to a pre-programmed second threshold voltage range. The starting voltage of the second threshold voltage range is a turn-on voltage of the memory cell.
In an embodiment, the searching module 62 is specifically configured to search an ith verification voltage from a preset verification voltage set, apply the ith verification voltage to a memory cell in the memory block, and perform a primary verification; judging whether a storage unit in the storage block passes the verification or not; when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on; taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage; wherein i=1, 3,5, … N, N being a positive integer.
In an embodiment, the determining module 63 is specifically configured to determine a voltage difference between the first verification voltage and a preset initial verification voltage; obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells in the memory block are erased once; and taking the sum of the obtained voltages as a first erasing voltage for performing second erasing on the memory cells in the memory block.
Here, the erase module 61 applies the first erase voltage to all the memory cells in the memory block, thereby accelerating the movement of charges stored in the memory cells toward the substrate, and thus enabling the threshold voltage range of the memory cells to be directly changed to the initial threshold voltage range.
It should be noted that: the erasing device provided in the above embodiment only uses the division of each program module to illustrate when erasing the 3D NAND, and in practical application, the process allocation may be performed by different program modules according to needs, i.e. the internal structure of the device is divided into different program modules to complete all or part of the processes described above. In addition, the erasing device and the erasing method provided in the foregoing embodiments belong to the same concept, and detailed implementation processes of the erasing device and the erasing method are detailed in the method embodiments and are not described herein again.
In practical applications, the erasing module 61, the searching module 62 and the determining module 63 may be implemented by a processor located on the erasing device, such as a central processing unit (CPU, central Processing Unit), a microprocessor (MPU, micro Processor Unit), a digital signal processor (DSP, digital Signal Processor), or a field programmable gate array (FPGA, field Programmable Gate Array).
Fig. 7 is a schematic structural diagram of an erasing device according to the present application, and the erasing device 700 shown in fig. 7 includes: at least one processor 701, a memory 702, a user interface 703, at least one network interface 704. The various components in the erasure device 700 are coupled together by a bus system 705. It is appreciated that the bus system 705 is used to enable connected communications between these components. The bus system 705 includes a power bus, a control bus, and a status signal bus in addition to the data bus. But for clarity of illustration, the various buses are labeled as bus system 705 in fig. 7.
The user interface 703 may include, among other things, a display, keyboard, mouse, trackball, click wheel, keys, buttons, touch pad, or touch screen, etc.
The memory 702 in embodiments of the present application is used to store various types of data to support the operation of the erase device 700. Examples of such data include: any computer programs for operating on the erasing device 700, such as the operating system 7021 and application programs 7022; the operating system 7021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 7022 may contain various application programs for implementing various application services. A program for implementing the method of the embodiment of the present application may be contained in the application program 7022.
The method disclosed in the above embodiment of the present application may be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 701 or by instructions in the form of software. The processor 701 may be a general purpose processor, a digital signal processor, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 701 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiment of the application can be directly embodied in the hardware of the decoding processor or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium in a memory 702. The processor 701 reads information in the memory 702 and, in combination with its hardware, performs the steps of the method as described above.
It is to be appreciated that the memory 702 can be either volatile memory or nonvolatile memory, and can include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 702 described in embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.
Based on the erasing method provided by the embodiments of the present application, the present application further provides a computer readable storage medium, as shown in fig. 7, the computer readable storage medium may include: a memory 702 for storing a computer program executable by the processor 701 of the erasing device 700 to perform the steps of the method described above. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, or CD-ROM.
The foregoing description is only of the preferred embodiments of the present application, and is not intended to limit the scope of the present application.
Claims (10)
1. A method of erasing, the method comprising:
pre-programming memory cells in a memory block to change the threshold voltage range of the memory cells from an initial threshold voltage range to a second threshold voltage range;
erasing the memory cells in the memory block after the pre-programming for one time, so that the threshold voltage range of the memory cells is changed from the second threshold voltage range to a first threshold voltage range;
searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set corresponding to the memory cells in the memory block;
determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage;
applying the first erasing voltage to the memory cells in the memory block, and performing second erasing to change the threshold voltage range of the memory cells from the first threshold voltage range to the initial threshold voltage range;
the preset check voltage sets corresponding to different memory cells in the memory block are different.
2. The method of claim 1, wherein a minimum voltage value of the set of preset verify voltages is set according to a process associated with the corresponding memory cell, and a maximum voltage value of the set of preset verify voltages is set according to a turn-on voltage of the corresponding memory cell.
3. The method of claim 1, wherein the searching for a first verify voltage from a set of preset verify voltages corresponding to memory cells in the memory block such that the memory cells in the memory block pass the verification comprises:
searching an ith check voltage from a preset check voltage set, and applying the ith check voltage to a storage unit in the storage block to perform one-time check; judging whether a storage unit in the storage block passes the verification or not;
when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on;
taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage;
wherein i=1, 3,5, … N, N being a positive integer.
4. The method of claim 1, wherein determining a first erase voltage for a second erase of memory cells in the memory block using the first verify voltage comprises:
determining a voltage difference between the first verification voltage and a preset initial verification voltage;
obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells in the memory block are erased once;
and taking the sum of the obtained voltages as a first erasing voltage for performing second erasing on the memory cells in the memory block.
5. The method of claim 1, wherein the erasing the memory cells in the pre-programmed memory block once to change the threshold voltage range of the memory cells from the second threshold voltage range to the first threshold voltage range comprises:
after pre-programming memory cells in the memory block, determining an initial erase voltage;
and applying the initial erasing voltage to the memory cells in the pre-programmed memory block, and performing first erasing so as to change the threshold voltage range of the memory cells from the second threshold voltage range to a first threshold voltage range.
6. The method of claim 5, wherein prior to pre-programming the memory cells in the memory block, the method further comprises:
determining a storage block to be processed;
the pre-programming the memory cells in the memory block includes:
and pre-programming the storage units in the storage block to be processed.
7. A memory device, comprising: a memory cell array and a control unit; wherein,
the memory cell array comprises a plurality of memory blocks; each memory block of the plurality of memory blocks includes a plurality of memory cells;
the control unit is used for pre-programming the memory cells in the memory block so as to change the threshold voltage range of the memory cells from an initial threshold voltage range to a second threshold voltage range;
erasing the memory cells in the memory block after the pre-programming for one time, so that the threshold voltage range of the memory cells is changed from the second threshold voltage range to a first threshold voltage range;
searching a first check voltage which enables the memory cells in the memory block to pass the check from a preset check voltage set corresponding to the memory cells in the memory block; determining a first erase voltage for performing a second erase on memory cells in the memory block by using the first verify voltage;
applying the first erasing voltage to the memory cells in the memory block through selecting word lines, and performing second erasing so as to change the threshold voltage range of the memory cells from the first threshold voltage range to the initial threshold voltage range;
the preset check voltage sets corresponding to different memory cells in the memory block are different.
8. The memory device of claim 7, wherein a minimum voltage value of the set of preset verify voltages is set according to a related process of the corresponding memory cell, and a maximum voltage value of the set of preset verify voltages is set according to a turn-on voltage of the corresponding memory cell.
9. The storage device of claim 7, wherein the memory is configured to store the data,
the control unit is specifically configured to search an ith verification voltage from a preset verification voltage set, apply the ith verification voltage to a storage unit in the storage block, and perform a primary verification; judging whether a storage unit in the storage block passes the verification or not; when the verification is not passed, searching an (i+1) th verification voltage from a preset verification voltage set, applying the (i+1) th verification voltage to the storage units in the storage block, and performing verification again; judging whether a storage unit in the storage block passes the verification or not; and so on; taking the verification voltage which enables the memory cells in the memory block to pass verification as a first verification voltage; wherein i=1, 3,5, … N, N being a positive integer.
10. The storage device of claim 7, wherein the memory is configured to store the data,
the control unit is specifically configured to determine a voltage difference between the first verification voltage and a preset initial verification voltage; obtaining the sum of the voltage difference and the initial erasing voltage by utilizing the voltage difference and the initial erasing voltage applied when the memory cells in the memory block are erased once; and taking the sum of the obtained voltages as a first erasing voltage for performing second erasing on the memory cells in the memory block.
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| KR102295528B1 (en) * | 2015-08-25 | 2021-08-30 | 삼성전자 주식회사 | Memory device, Memory system, Method of operating the memory device and Method of operating the memory system |
| JP2017174482A (en) * | 2016-03-24 | 2017-09-28 | 力晶科技股▲ふん▼有限公司 | Non-volatile semiconductor memory device and erasure method thereof |
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| CN109243516A (en) | 2019-01-18 |
| CN109243516B (en) | 2021-08-10 |
| CN113628659A (en) | 2021-11-09 |
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