CN101661448B - Device and method for sorting data - Google Patents
Device and method for sorting data Download PDFInfo
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- CN101661448B CN101661448B CN2008101469088A CN200810146908A CN101661448B CN 101661448 B CN101661448 B CN 101661448B CN 2008101469088 A CN2008101469088 A CN 2008101469088A CN 200810146908 A CN200810146908 A CN 200810146908A CN 101661448 B CN101661448 B CN 101661448B
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Abstract
The invention discloses a device and a method for sorting data, wherein the data sorting device comprises a plurality of groups of buffer and an actuating controller. Each group of buffer is provided with a falling edge flop-flop buffer and a rising edge flop-flop buffer and receives serial data according to a rising edge trigger of a working frequency and a falling edge trigger of a working frequency. The actuating controller is connected to each group of buffers and actuates each buffer in turn according to the rising edge trigger of the working frequency.
Description
Technical field
The present invention refers to a kind of at Double Date Rate (Double Data Rate relevant for a kind of data sorting device and method especially; DDR) under the transmitting serial data, in order to keep the device and method of the correct ordering of serial data.
Background technology
Please refer to Fig. 1, be known bit shift register configuration diagram.Wherein, bit shift register 1 is made up of one first buffer 10, one second buffer 12, one the 3rd buffer 14 and one the 4th buffer 16, and is the bit shift register 1 of one 4 outputs.Bit shift register 1 is according to the triggering of frequency clk1 or clk2, carrying out the reception of serial data serial_data, and received serial data serial_data is presented on output terminal Q0～Q3.Yet the serial data serial_data that is presented on output terminal Q0～Q3 can be because in the bit shift register 1, and flip-flop is according to the triggering of out of phase frequency clk, and the data output that causes difference to sort.
Cooperate frequency plot shown in Figure 2, multiple with reference to figure 1.Wherein, during according to the first stroke data S1 of serial data serial_data transmission, different triggering phase places, and be divided into frequency clk1 and frequency clk2.When the first stroke data S1 of serial data serial_data triggers when transmitting according to the negative edge of frequency clk1, in time t0, the first stroke data S1 of serial data serial_data can be transferred into second buffer 12, then, second data S2 of serial data serial_data is when time t1, positive edge according to frequency clk1 triggers, and is transferred into first buffer 10.Then, the 3rd the data S3 of serial data serial_data is when time t2, and the negative edge triggering according to frequency clk1 is transferred into second buffer 12, and originally the first stroke data S1 in second buffer 12 then is transferred into the 4th buffer 16.Next, the 4th the data S4 of serial data serial_data is when time t3, and the positive edge triggering according to frequency clk1 is transferred into first buffer 10, and originally second data S2 in first buffer 10 then is transferred into the 3rd buffer 14.So, when time t3, bit shift register 1 is collected output terminal Q0～Q3 that serial data serial_data is presented on first buffer, 10 to the 4th buffers 16, and it is S4, S3, S2, S1 in proper order.
The composite Fig. 2 that closes, with reference to figure 1, when the first stroke data S1 of serial data serial_data triggers when transmitting according to the positive edge of frequency clk2, in time t0, the first stroke data S1 of serial data serial_data can be transferred into first buffer 10, and then, second data S2 of serial data serial_data is when time t1, negative edge according to frequency clk2 triggers, and is transferred into second buffer 12.Then, the 3rd the data S3 of serial data serial_data is when time t2, and the positive edge triggering according to frequency clk2 is transferred into first buffer 10, and originally the first stroke data S1 in first buffer 10 then is transferred into the 3rd buffer 14.Next, the 4th the data S4 of serial data serial_data is when time t3, and the negative edge triggering according to frequency clk2 is transferred into second buffer 12, and originally second data S2 in second buffer 12 then is transferred into the 4th buffer 16.So, when time t3, bit shift register 1 is collected output terminal Q0～Q3 that serial data serial_data is presented on first buffer, 10 to the 4th buffers 16, and it is S3, S4, S1, S2 in proper order.
Therefore, when use bit shift register 1 was collected serial data serial_data, the order (serial data sequence) that bit shift register 1 is collected serial data can be that the positive edge triggering transmission of frequency or the negative edge triggering transmission (rising edge or falling edge) of frequency have different putting in order according to the first stroke data S1.And in order to improve the problem of aforementioned serial data ordering, need the extra phase place (clock phase) that phase detector (phase detector) is detected frequency that increases, yet this kind mode will increase extra cost.
So, at standard action image architecture (Standard Mobile Imaging Architecture; SMIA) in the standard, for fear of the use of phase detector (phase detector), just the first stroke data S1 of standard serial data serial_data is at Double Date Rate (Double DataRate; DDR) under the transmission, the negative edge of necessary frequency of utilization triggers and transmits (falling edge of clock).
But, if there is unexpected situation to take place in transmission end (transmitter), substrate (substrate), plank (board) or the system (system), make that the first stroke data S1 is not the negative edge triggering transmission with frequency, then the ordering of serial data serial_data will entanglement, simultaneously, also can't from serial data serial_data, solve synchronous code (synchronization code), and cause the total system entanglement and can't reply.
Summary of the invention
In sum, the invention provides a kind of data sorting device and method, can be at Double Date Rate (Double Data Rate; DDR) under the transmitting serial data,, can be that the positive edge triggering transmission of frequency or the negative edge of frequency trigger transmission according to the first stroke data S1 to solve serial data in order to keep the correct ordering of serial data, and the problem that has difference to put in order.
Data sorting device of the present invention includes a plural groups buffer and an activation controller.Wherein, each group buffer all has a negative edge and triggers a buffer and a positive edge triggering buffer, and each group buffer all triggers to receive serial datum according to the positive edge triggering of a frequency of operation and the negative edge of frequency of operation, wherein, negative edge according to this frequency of operation triggers, the negative edge of first group of buffer triggers buffer and receives the first stroke data, and, positive edge according to this frequency of operation triggers, the positive edge of first group of buffer triggers buffer and receives second data, and next the negative edge according to this frequency of operation triggers, the negative edge of second group of buffer triggers buffer and receives the 3rd data, and, next positive edge according to this frequency of operation triggers, the positive edge of second group of buffer triggers buffer and receives the 4th data, or, positive edge according to this frequency of operation triggers, the positive edge of first group of buffer triggers buffer and receives the first stroke data, and the negative edge according to this frequency of operation triggers, the negative edge of second group of buffer triggers buffer and receives second data, and, triggering according to next positive edge of this frequency of operation, the positive edge of second group of buffer triggers buffer and receives the 3rd data.In addition, the activation controller is connected in each group buffer, triggers according to the positive edge of frequency of operation, in turn each group buffer of activation.
According to aforementioned data sorting device of the present invention, be to use the activation controller to come first group of buffer of activation, this activation controller is that the positive edge of frequency of operation triggers, at this moment, if the first stroke data of serial data are followed the SMIA standard, the first stroke data trigger institute by the negative edge of frequency and are transmitted, and second data are transmitted by the positive edge triggering of frequency, and the 3rd data are transmitted by the negative edge triggering of frequency again, and the rest may be inferred.Wherein, after an even number data of serial data are transmitted, the buffer (second group of buffer) of next group of activation controller meeting activation, so, serial data is identical when putting in order just with the serial data input.
In addition, if the first stroke data of serial data are not followed the SMIA standard, the first stroke data trigger institute by the positive edge of frequency and are transmitted, and second data are transmitted by the negative edge triggering of frequency, and the 3rd transmitted by the positive edge triggering of frequency again, the rest may be inferred, wherein, after an odd number data of serial data are transmitted, next group buffer (second group of buffer) of activation controller meeting activation, it is identical when so, serial data puts in order still with the serial data input.
To sum up, the present invention triggers according to the positive edge of frequency of operation, use the activation controller to take turns the method for each group buffer of activation, can avoid when the serial data transmission mode is violated the SMIA standard, still can keep putting in order of serial data, also need not use extra phase detector (phasedetector) simultaneously.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further specify claim of the present invention.And about other purpose of the present invention and advantage, will be set forth in follow-up explanation and diagram.
Description of drawings
Fig. 1 is known bit shift register configuration diagram;
Fig. 2 triggers the phase place synoptic diagram for frequency;
Fig. 3 is the configuration diagram of data sorting device of the present invention;
Fig. 4 triggers the phase place synoptic diagram for frequency;
Fig. 5 is the schematic flow sheet of serial data sort method of the present invention;
Fig. 6 is another schematic flow sheet of serial data sort method of the present invention.
The primary clustering symbol description
Known:
Serial data serial_data
Frequency clk1, clk2
The 3rd buffer 14
The 4th buffer 16
Output terminal Q0～Q3
The present invention:
First group of buffer 20
Second group of buffer 22
The first negative edge triggers buffer 200
The second negative edge triggers buffer 220
The first positive edge triggers buffer 202
The second positive edge triggers buffer 222
Serial data serial_data
Frequency clk1, clk2
Time t0-t3
Data S1-S4, SN
Embodiment
Please refer to Fig. 3, be the configuration diagram of data sorting device of the present invention.At this, output of the present invention is to be output as embodiment as an illustration with 4.So, data sorting device 2 of the present invention includes one first group of buffer 20, one second group of buffer 22 and activation controller 24, yet, if will increase the output figure place, open up the buffers of the newly-increased many groups of framework of web, to increase the output figure place according to circuit.
Include one first negative edge with reference to 3, the first groups of buffers 20 of figure again and trigger buffer 200 and one first positive edge triggering buffer 202, wherein, buffer 200,202 is a D type flip-flop.Simultaneously, the first negative edge triggers the negative edge triggering that buffer 200 is foundation one frequency of operation clk, and receives serial datum serial_data, and, the first positive edge triggering buffer 202 is the positive edge triggerings according to frequency of operation clk, and receives serial data serial_data.
In addition, second group of buffer 22 comprises that one second negative edge triggers buffer 220 and one second positive edge triggers buffer 222, and wherein, buffer 220,222 is a D type flip-flop.Simultaneously, the second negative edge triggering buffer 220 is the negative edge triggerings according to frequency of operation clk, and receives serial data serial_data, and, the second positive edge triggering buffer 222 is the positive edge triggerings according to frequency of operation clk, and receives serial data serial_data.In addition, activation controller 24 is connected in first group of buffer 20 and this second group of buffer 22, is that the positive edge according to frequency of operation clk triggers first group of buffer 20 of activation and second group of buffer 22 in turn.
Cooperate frequency plot shown in Figure 4, multiple with reference to figure 3.Wherein, during according to the first stroke data S1 of serial data serial_data transmission, different triggering phase places, and be divided into frequency clk1 and frequency clk2.When the first stroke data S1 of serial data serial_data follows the SMIA standard, transmit and trigger according to the negative edge of frequency of operation clk1, and when first group of buffer 20 activation.In time t0, the first stroke data S1 of serial data serial_data can be transferred into the first negative edge and trigger buffer 200, then, second data S2 of serial data serial_data is when time t1, positive edge according to frequency of operation clk1 triggers, and be transferred into the first positive edge and trigger buffer 202, and, activation controller 24 moves according to the positive edge triggering of frequency of operation clk1, with second group of buffer 22 of activation.
Then, the 3rd the data S3 of serial data serial_data can trigger according to the negative edge of frequency of operation clk1 when time t2, is transferred into the second negative edge and triggers buffer 220.Next, the 4th the data S4 of serial data serial_data is when time t3, and the positive edge triggering according to frequency of operation clk1 is transferred into the second positive edge and triggers buffer 222.So, when time t3, data sorting device 2 is collected output terminal Q0～Q3 that serial data serial_data is presented on first group of buffer 20 and second group of buffer 22, and it is S1, S2, S3, S4 in proper order.
In addition, when the first stroke data S1 of serial data serial_data does not follow the SMIA standard, and trigger when transmitting according to the positive edge of frequency of operation clk2, in time t0, the first stroke data S1 of serial data serial_data can be transferred into the first positive edge and trigger buffer 202, and activation controller 24 moves according to the positive edge triggering of frequency of operation clk2, with second group of buffer 22 of activation.Then, second data S2 of serial data serial_data is when time t1, and the negative edge triggering according to frequency of operation clk2 is transferred into the second negative edge and triggers buffer 220.Then, the 3rd the data S3 of serial data serial_data is when time t2, can trigger according to the positive edge of frequency of operation clk2, be transferred into the second positive edge and trigger buffer 222, and, activation controller 24 triggers action once more according to the positive edge of frequency of operation clk2, with first group of buffer 20 of activation once more.Next, the 4th the data S4 of serial data serial_data is when time t3, and according to the negative edge triggering of frequency of operation clk2, the first negative edge that is transferred into first group of buffer 20 triggers buffer 200.So, when time t3, data sorting device 2 is collected output terminal Q0～Q3 that serial data serial_data is presented on first group of buffer 20 and second group of buffer 22, and it is S4, S1, S2, S3 in proper order.
According to aforesaid explanation, if the first stroke data S1 of serial data serial_data follows the SMIA standard, the first stroke data S1 is transmitted by the negative edge triggering of frequency of operation clk1, then second data S2 can be transmitted by the positive edge triggering of frequency of operation clk1, and the 3rd data S3 transmitted by the negative edge triggering of frequency of operation clk1 again, and the rest may be inferred.Wherein, after the even number data of serial data serial_data were transmitted, activation controller 24 can second group of buffer 22 of activation.So, the serial signal serial_data that the output terminal Q0～Q3 of first group of buffer 20 and second group of buffer 22 is sent, it is identical when putting in order just with serial signal serial_data input.
In addition, if the first stroke data S1 of serial data serial_data does not follow the SMIA standard, the first stroke data S1 is transmitted by the positive edge triggering of frequency of operation clk2, second data S2 by the negative edge of frequency of operation clk2 trigger transmitted, and the 3rd data S3 transmitted by the positive edge triggering of frequency of operation clk2 again, and the rest may be inferred, wherein, after the odd number data of serial data serial_data were transmitted, activation controller 24 can first group of buffer 20 of activation.So, the serial signal serial_data that the output terminal Q0～Q3 of first group of buffer 20 and second group of buffer 22 is sent, it is identical when putting in order still with serial signal serial_data input.
Please refer to Fig. 5, the schematic flow sheet of serial data sort method of the present invention.In the serial data sort method step of the present invention, at first, following under the SMIA standard, trigger and the first stroke data S1 is reached first group of buffer (S100) according to the negative edge of frequency of operation, then, the positive edge triggering according to this frequency of operation reaches first group of buffer with second data S2, and the positive edge of this frequency of operation triggers second group of buffer of activation (S102).Then, according to next negative edge triggering of this frequency of operation, the 3rd data S3 reached second group of buffer (S104) of activation.At last, next the positive edge according to frequency of operation triggers again, and the 4th data S4 reached second group of buffer, and, follow the 3rd group of buffer of activation (S106).According to aforementioned sort method, to follow under the SMIA standard, serial data is if there are S1～SN data to transmit, and then its order from transmission will be S1, S2, S3, S4...SN.
Please refer to Fig. 6, another schematic flow sheet of serial data sort method of the present invention.In the serial data sort method step of the present invention, at first, do not following under the SMIA standard, triggering and the first stroke data S1 is reached first group of buffer according to the positive edge of frequency of operation, and the positive edge of this frequency of operation triggers second group of buffer of activation (S200).Then, the negative edge triggering according to this frequency of operation reaches second group of buffer (S202) with second data S2.Then, trigger, the 3rd data S3 reached second group of buffer of activation, and the positive edge of this frequency of operation triggers the 3rd group of buffer of activation (S204) according to the positive edge of next of this frequency of operation.At last, next the negative edge according to frequency of operation triggers again, and the 4th data S4 reached the 3rd group of buffer (S206).According to aforementioned sort method, not follow under the SMIA standard, serial data is if there are S1～SN data to transmit, and then it is similarly S1, S2, S3, S4...SN from transmission sequence.
In sum, data sorting device and method provided by the present invention is framework and a method of operating thereof of utilizing entity circuit (robust), and the serial signal that low voltage differential signal (SubLVDS) sequence produces is arranged and exported.Even meet accident, the first stroke data of aforementioned serial signal are not to follow the SMIA standard to transmit down (the negative edge according to frequency of operation triggers), whole serial data will be maintained original ordering, and, do not need to use phase detector (phase detector).
Therefore, data sorting device and method provided by the present invention can be at Double Date Rate (Double Data Rate; DDR) keep the correct ordering of serial data under the transmission serial signal, along with triggering, transmits at the positive edge of frequency of operation or negative edge triggers and transmits in order to the first stroke data of solving serial data, and the problem that has difference to put in order simultaneously, is also saved the use of phase detector.
The above only is the specific embodiment of the best of the present invention, but feature of the present invention is not limited thereto, and anyly is familiar with this skill person in the field of the invention, can think easily and variation or modification, all can be encompassed in claim of the present invention.
Claims (5)
1. a data sorting device is characterized in that, includes:
Plural groups buffer, each group buffer all has a negative edge and triggers a buffer and a positive edge triggering buffer, and, each group buffer is all according to the positive edge triggering of a frequency of operation and the negative edge triggering of this frequency of operation, to receive serial datum, wherein, negative edge according to this frequency of operation triggers, the negative edge of first group of buffer triggers buffer and receives the first stroke data, and, positive edge according to this frequency of operation triggers, the positive edge of first group of buffer triggers buffer and receives second data, and next the negative edge according to this frequency of operation triggers, the negative edge of second group of buffer triggers buffer and receives the 3rd data, and, next positive edge according to this frequency of operation triggers, the positive edge of second group of buffer triggers buffer and receives the 4th data, or, positive edge according to this frequency of operation triggers, and the positive edge of first group of buffer triggers buffer and receives the first stroke data, and triggers according to the negative edge of this frequency of operation, the negative edge of second group of buffer triggers buffer and receives second data, and, triggering according to next positive edge of this frequency of operation, the positive edge of second group of buffer triggers buffer and receives the 3rd data; And
One activation controller is connected in each group buffer, triggers according to the positive edge of this frequency of operation, in turn each group buffer of activation.
2. data sorting device as claimed in claim 1 is characterized in that: it all is a D type flip-flop with positive edge triggering buffer that negative edge triggers buffer.
3. serial data sort method, be applicable to many group buffers, it is characterized in that, each group buffer all has an odd number buffer and an even number buffer, this sort method includes: the negative edge according to a frequency of operation triggers, transmit the odd number buffer of the first stroke data to the first group buffer of serial datum, and, according to the positive edge triggering of this frequency of operation, transmit the even number buffer of second data to the first group buffer of this serial data, and, second group of buffer of activation, and, according to next negative edge triggering of this frequency of operation, transmit the odd number buffer of the 3rd data to the second group buffer of this serial data, and, according to next positive edge triggering of this frequency of operation, transmit the even number buffer of the 4th data to the second group buffer of this serial data, and, first group of buffer of activation; Or
Positive edge according to this frequency of operation triggers, transmit the even number buffer of the first stroke data to the first group buffer of this serial data, and, second group of buffer of activation, and, negative edge according to this frequency of operation triggers, transmit the odd number buffer of second data to the second group buffer of this serial data, and, according to next positive edge triggering of this frequency of operation, transmit the even number buffer of the 3rd data of this serial data to this second group of buffer, and, first group of buffer of activation, and, next negative edge according to this frequency of operation triggers, and transmits the odd number buffer of the 4th data to the first group buffer of this serial data.
4. serial data sort method as claimed in claim 3 is characterized in that: this first odd number buffer and this second odd number buffer are all a negative edge and trigger buffer.
5. serial data sort method as claimed in claim 3 is characterized in that: this first even number buffer and this second even number buffer are all a positive edge and trigger buffer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101469088A CN101661448B (en) | 2008-08-26 | 2008-08-26 | Device and method for sorting data |
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| CN2008101469088A CN101661448B (en) | 2008-08-26 | 2008-08-26 | Device and method for sorting data |
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| CN101661448A CN101661448A (en) | 2010-03-03 |
| CN101661448B true CN101661448B (en) | 2011-06-29 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1808159A (en) * | 2004-11-18 | 2006-07-26 | 三洋电机株式会社 | Semiconductor device with built-in scan test circuit |
| CN2872451Y (en) * | 2005-11-01 | 2007-02-21 | 智多微电子（上海）有限公司 | Dynamic switching circuit of clock |
| US7304897B2 (en) * | 2002-04-02 | 2007-12-04 | Via Technologies, Inc. | Method and system for reading data from a memory |
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2008
- 2008-08-26 CN CN2008101469088A patent/CN101661448B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7304897B2 (en) * | 2002-04-02 | 2007-12-04 | Via Technologies, Inc. | Method and system for reading data from a memory |
| CN1808159A (en) * | 2004-11-18 | 2006-07-26 | 三洋电机株式会社 | Semiconductor device with built-in scan test circuit |
| CN2872451Y (en) * | 2005-11-01 | 2007-02-21 | 智多微电子（上海）有限公司 | Dynamic switching circuit of clock |
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| CN101661448A (en) | 2010-03-03 |
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