CN116566383A - Synchronous five-frequency dividing circuit and five-frequency dividing signal generation method - Google Patents
Synchronous five-frequency dividing circuit and five-frequency dividing signal generation method Download PDFInfo
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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Abstract
The invention provides a synchronous five-frequency dividing circuit and a five-frequency dividing signal generating method, which are characterized in that through the operation of three expressions of D1= (Q1 |) & (Q3|), D2= ((Q1) & (Q2)) |((Q1) & (Q2|)), D3 = Q1& Q2, and then the 3D triggers are combined, the 5-bit cyclic state conversion of the Q3Q2Q1 combined state is realized, then the 1D triggers are utilized to shift the Q2 signal, and the inverse signal of the Q2 is combined to carry out logic operation, so that the five-frequency divider with 50% duty ratio is realized, the synchronous 5-frequency dividing circuit can be realized under the condition that only 4 rising edge triggered D triggers are used, 1-2 triggers can be saved compared with other circuits with the same duty ratio, the required trigger structure is simpler, the area and the cost can be effectively saved in an integrated circuit, and in addition, the circuit can also keep the duty ratio of the frequency dividing signal to be 50%.
Description
Technical Field
The invention relates to the technical field of signal frequency division, in particular to a synchronous five-frequency division circuit and a five-frequency division signal generation method.
Background
The flip-flop implemented divider is easier to obtain a 50% duty cycle divided output when the division ratio is even, but is harder to obtain a 50% duty cycle when the division ratio is odd. For example, for a divide-by-five circuit, the duty cycle of the output divide-by-five signal will typically be 40% or 60%. However, in high-speed circuits, there are very strict index requirements on the signal quality of the clock, and clocks other than 50% duty cycle can affect the operating state of the module. Therefore, for a divider with an odd division ratio, it is important to keep the divided signal at 50% duty cycle.
The frequency divider realized by the D flip-flops is usually built in a flip-flop cascade mode, and the number of the required flip-flops is larger than or equal to the frequency division ratio. In particular, for an odd-number frequency divider, in order to ensure that the duty ratio of an output signal is 50%, a trigger triggered by a rising edge and a falling edge are required to be used simultaneously, or the number of the triggers is increased, so that the built frequency dividing circuit has a complex structure.
Disclosure of Invention
The invention provides a synchronous five-frequency dividing circuit and a five-frequency dividing signal generation method, which are used for solving the defects of complex structure and high construction difficulty of the frequency dividing circuit in the prior art.
The invention provides a synchronous five-frequency dividing circuit, which comprises:
a first signal generation circuit configured based on the first logic gate circuit and the first D flip-flop for generating a first process signal;
a second signal generation circuit configured based on the second logic gate circuit and the second D flip-flop for generating a second process signal;
a third signal generation circuit configured based on the third logic gate circuit and the third D flip-flop for generating a third process signal; the first logic gate circuit is used for executing a logic operation (Q1 |) & (Q3|), the second logic gate circuit is used for executing a logic operation ((Q1 |) & (Q2)) | ] ((Q1) & (Q2|)), the third logic gate circuit is used for executing a logic operation Q1& Q2, Q1 is a first process signal output by the first D trigger at the last moment, Q2 is a second process signal output by the second D trigger at the last moment, and Q3 is a third process signal output by the third D trigger at the last moment; under the action of a basic clock signal, one period of a combined state of the third process signal, the second process signal and the first process signal is 5 reference clock periods, and the combined state is cyclically changed according to the sequence of 001, 010, 011, 100 and 000;
and the frequency division signal synthesis circuit is constructed based on the fourth D trigger and is used for delaying the second process signal by 1/2 reference clock period based on the reverse reference clock signal, generating a second process delay signal, and carrying out logic operation on the reverse second process signal and the reverse second process delay signal to obtain a five-frequency division signal.
According to the synchronous five-frequency dividing circuit provided by the invention, the frequency dividing signal synthesizing circuit comprises a first inverter, the fourth D flip-flop, a second inverter and a first NAND gate circuit; the reference clock signal is input into the first inverter for inversion, and the output end of the first inverter is connected with the clock edge of the fourth D flip-flop; the D end of the fourth D trigger is connected with the in-phase output end of the second D trigger, the in-phase output end of the fourth D trigger is connected with the input end of the second phase inverter, and the fourth D trigger is triggered by a rising edge; the output end of the second inverter and the inverting output end of the second D trigger are respectively connected with the two input ends of the first NAND gate circuit.
According to the synchronous five-frequency dividing circuit provided by the invention, the first logic gate circuit is a first NOR gate circuit, the output end of the first NOR gate circuit is connected with the D end of the first D trigger, the clock edge of the first D trigger is connected with the reference clock signal, and the first D trigger is triggered by the rising edge; the input end of the first NOR gate circuit is respectively connected with the in-phase output end of the first D trigger and the in-phase output end of the third D trigger.
According to the synchronous five-frequency dividing circuit provided by the invention, the output end of the second logic gate circuit is connected with the D end of the second D trigger, the clock edge of the second D trigger is connected with the reference clock signal, and the second D trigger is triggered by the rising edge; the second logic gate circuit comprises a second NAND gate circuit, a third NAND gate circuit, a fourth NAND gate circuit and a second D trigger;
the input end of the second NAND gate circuit is respectively connected with the non-inverting output end of the first D trigger and the inverting output end of the second D trigger; the input end of the third NAND gate circuit is respectively connected with the inverting output end of the first D trigger and the non-inverting output end of the second D trigger; the input end of the fourth NAND gate circuit is respectively connected with the output end of the second NAND gate circuit and the output end of the third NAND gate circuit; and the output end of the fourth NAND gate circuit is connected with the D end of the second D trigger.
According to the synchronous five-frequency dividing circuit provided by the invention, the third logic gate circuit is a second NOR gate circuit, the output end of the second NOR gate circuit is connected with the D end of the third D trigger, the clock edge of the third D trigger is connected with the reference clock signal, and the third D trigger is triggered by the rising edge; the input end of the second NOR gate circuit is respectively connected with the inverting output end of the first D trigger and the inverting output end of the second D trigger.
The invention also provides a five-frequency-division signal generation method based on any one of the synchronous five-frequency-division circuits, which comprises the following steps:
generating a first process signal using a first signal generation circuit constructed based on a first logic gate circuit and a first D flip-flop;
generating a second process signal using a second signal generation circuit constructed based on a second logic gate circuit and a second D flip-flop;
generating a third process signal using a third signal generation circuit constructed based on a third logic gate circuit and a third D flip-flop; the first logic gate circuit is used for executing a logic operation (Q1 |) & (Q3|), the second logic gate circuit is used for executing a logic operation ((Q1 |) & (Q2)) | ] ((Q1) & (Q2|)), the third logic gate circuit is used for executing a logic operation Q1& Q2, Q1 is a first process signal output by the first D trigger at the last moment, Q2 is a second process signal output by the second D trigger at the last moment, and Q3 is a third process signal output by the third D trigger at the last moment; under the action of a basic clock signal, one period of a combined state of the third process signal, the second process signal and the first process signal is 5 reference clock periods, and the combined state is cyclically changed according to the sequence of 001, 010, 011, 100 and 000;
and delaying the second process signal by 1/2 reference clock period based on the reverse reference clock signal by using a frequency division signal synthesis circuit constructed based on the fourth D trigger to generate a second process delay signal, and carrying out logic operation on the reverse second process signal and the reverse second process delay signal to obtain a five-frequency division signal.
According to the method for generating a divided-by-five signal provided by the invention, the second process signal is delayed by 1/2 reference clock period based on the reverse reference clock signal, a second process delay signal is generated, and logic operation is performed on the reverse second process signal and the reverse second process delay signal to obtain the divided-by-five signal, which specifically comprises:
inverting the reference clock signal based on a first inverter to obtain an inverted reference clock signal;
delaying the second process signal by 1/2 reference clock cycles with the fourth D flip-flop based on the inverted reference clock signal, generating a second process delayed signal;
inverting the second process delay signal based on a second inverter to obtain an inverted second process delay signal;
and carrying out logic operation on the inverted second process signal and the inverted second process delay signal based on the first NAND gate circuit to obtain a five-frequency division signal.
According to the method for generating the five-division signal provided by the invention, a first process signal is generated by using a first signal generating circuit constructed based on a first logic gate circuit and a first D trigger, and the method concretely comprises the following steps:
based on a first NOR gate circuit in the first signal generating circuit, performing logic operation on a first process signal output at a moment on an in-phase output end of a first D trigger in the first signal generating circuit and a third process signal output at a moment on an in-phase output end of a third D trigger in the third signal generating circuit to obtain a first D end input signal at a current moment;
and generating a first process signal at the current moment by using the first D trigger based on the first D end input signal at the current moment.
According to the method for generating the five-division signal provided by the invention, the second process signal is generated by using a second signal generating circuit constructed based on a second logic gate circuit and a second D flip-flop, and the method is specifically used for:
based on a second NAND gate in the second logic gate, performing logic operation on a first process signal output at one moment on an in-phase output end of the first D trigger and a second inverted process signal output at one moment on an opposite-phase output end of the second D trigger to obtain a first NAND gate output signal at the current moment;
based on a third NAND gate in the second logic gate circuit, performing logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a second process signal output at one moment on an in-phase output end of the second D trigger to obtain a second NAND gate output signal at the current moment;
based on a fourth NAND gate in the second logic gate, performing logic operation on the first NAND gate output signal and the second NAND gate output signal at the current moment to obtain a second D-terminal input signal at the current moment;
and generating a second process signal at the current moment by using the second D trigger based on the second D end input signal at the current moment.
According to the method for generating the five-division signal provided by the invention, a third process signal is generated by using a third signal generating circuit constructed based on a third logic gate circuit and a third D trigger, and the method concretely comprises the following steps:
based on a second NOR gate in the third signal generating circuit, carrying out logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a reverse second process signal output at one moment on an inverting output end of the second D trigger to obtain a third D end input signal at the current moment;
and generating a third process signal at the current moment by using the third D trigger based on the third D end input signal at the current moment.
According to the synchronous five-frequency dividing circuit and the five-frequency dividing signal generating method, through the operations of three expressions of D1= (Q1 |) & (Q3 |), D2= ((Q1 |) & (Q2)) |((Q1) & (Q2|)), D3 = Q1& Q2, the 5-bit cyclic state conversion of the Q3Q2Q1 combined state is achieved by combining 3D triggers, then the Q2 signal is shifted by using 1D trigger, and the five-frequency divider with the 50% duty ratio is achieved by combining the reverse signal of the Q2 to perform logic operation, the synchronous 5-frequency dividing circuit can be achieved under the condition that only 4 rising edge triggered D triggers are used, 1-2 triggers can be saved compared with other circuits with the same frequency dividing ratio, the required trigger structure is simpler, the area and the cost can be effectively saved in an integrated circuit, and in addition, the duty ratio of the frequency dividing signal can be kept to be 50%.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a synchronous divide-by-five circuit according to the present invention;
FIG. 2 is a schematic diagram of signal waveforms provided by the present invention;
FIG. 3 is a state machine diagram of the combined state of three process signals provided by the present invention;
fig. 4 is a schematic diagram of a frequency-divided signal synthesizing circuit according to the present invention;
fig. 5 is a flow chart of a method for generating a divide-by-five signal according to the present invention;
reference numerals:
110: a first signal generating circuit; 111: a first logic gate circuit; 112: a first D flip-flop; 120: a second signal generating circuit; 121: a second logic gate circuit; 122: a second D flip-flop; 130: a third signal generating circuit; 131: a third logic gate circuit; 132: a third D flip-flop; 140: a frequency-divided signal synthesizing circuit; 141: a fourth D flip-flop; 142: a first inverter; 143: a second inverter; 144: a first NAND gate.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Fig. 1 is a schematic diagram of a synchronous divide-by-five circuit according to the present invention, as shown in fig. 1, the synchronous divide-by-five circuit includes:
a first signal generation circuit 110 constructed based on the first logic gate circuit 111 and the first D flip-flop 112 for generating a first process signal;
a second signal generation circuit 120 constructed based on a second logic gate 121 and a second D flip-flop 122 for generating a second process signal;
third signal generation circuitry 130, constructed based on third logic gate 131 and third D flip-flop 132, for generating a third process signal;
the frequency-divided signal synthesis circuit 140, which is constructed based on the fourth D flip-flop 141, is configured to delay the second process signal by 1/2 of a reference clock period based on the inverted reference clock signal, generate a second process delay signal, and perform a logic operation on the inverted second process signal and the inverted second process delay signal to obtain a divide-by-five signal.
Specifically, a signal generating circuit is jointly constructed by using the logic gate circuit and the D trigger to generate a process signal meeting a preset condition by utilizing the characteristic that the D trigger can be turned over from one stable state to another under the action of a certain external signal. The first signal generating circuit 110 may be configured based on a first logic gate circuit 111 and a first D flip-flop 112 connected in series, where the first logic gate circuit 111 is configured to perform a logic operation: (Q1 |) & (Q3 |); the second signal generating circuit 120 is constructed based on a second logic gate circuit 121 and a second D flip-flop 122 connected in series, wherein the second logic gate circuit 121 is configured to execute logic: ((Q1 |) & (Q2)) || (Q1) & (Q2|)); a third signal generating circuit is constructed based on a third logic gate circuit 131 and a third D flip-flop 132 connected in series, wherein the third logic gate circuit 131 is configured to execute logic: q1& Q2.
Here, Q1 is a first process signal output at a time point on the first D flip-flop, Q2 is a second process signal output at a time point on the second D flip-flop, and Q3 is a third process signal output at a time point on the third D flip-flop. Accordingly, Q1-! Is the inverse of Q1, Q2-! Is the inverse of Q2, Q3-! Is the inverse of Q3. Under the action of the base clock signal, the third process signal (denoted as Q3) output by the third signal generating circuit 130, the second process signal (denoted as Q2) output by the second signal generating circuit 120, and the first process signal (denoted as Q1) output by the first signal generating circuit 110 are as shown in fig. 2, it can be seen that one period of the combined state (i.e., Q3Q2Q 1) of the three process signals is 5 reference clock periods, and the combined state is cyclically changed in the order of 001, 010, 011, 100, and 000. That is, in the i-th basic clock cycle, Q3Q2Q1 maintains a state, for example, 001, then in the i+1th basic clock cycle, Q3Q2Q1 is converted to 010, and in the i+2th basic clock cycle, Q3Q2Q1 is converted to 011. By analogy, Q3Q2Q1 transitions to 000 at the i+4 base clock cycles, and Q3Q2Q1 transitions back to 001 at the i+5 base clock cycles, completing a cycle.
It should be noted that, as shown in fig. 3, after Q3, Q2, and Q1 enter the corresponding logic gates in an arbitrary initial state, the combined states thereof are counted in the timings of 001, 010, 011, 100, and 000 in the next reference clock cycle, and cyclically shifted in the timings in the subsequent reference clock cycle.
The second process signal output from the second signal generating circuit 120 is input to the frequency-divided signal synthesizing circuit 140 constructed based on the fourth D flip-flop 141. The frequency-divided signal synthesis circuit 140 is configured to delay the second process signal by 1/2 reference clock period based on the inverted reference clock signal, generate a second process delay signal, and perform logic operation on the inverted second process signal and the inverted second process delay signal to obtain a divide-by-five signal. The fourth D flip-flop delays the second process signal by 1/2 of the reference clock period under the action of the inverted reference clock signal, so as to obtain a second process delayed signal, and the waveform of the second process delayed signal is shown in fig. 2. Then, after inverting the second process delay signal to obtain an inverted second process delay signal, performing a logic operation on the inverted second process signal and the inverted second process delay signal, and specifically performing the following logic operation on the inverted second process delay signal: (Q2B & Q2 XB) ++! Wherein Q2B is the inverted second process signal, Q2XB is the inverted second process delay signal, and a divide-by-five signal of the reference clock signal is obtained, and the waveform of the divide-by-five signal is shown in fig. 2.
It can be seen that, in the synchronous divide-by-five circuit provided in the embodiment of the present invention, the operations of three expressions of d1= (Q1 |) & (Q3 |) & (Q2)) | (Q1) & (Q2 |)), d2= (Q1) & Q1& Q2) are performed by using d1= (Q1 |) & (Q3 |) & (Q2 |)), and then combining with 3D flip-flops, the 5-bit cyclic state conversion of the Q3Q2Q1 combined state is implemented, then the Q2 signal is shifted by using 1D flip-flop, and the inverse signal of Q2 is combined to perform the logic operation, so that the five frequency divider with 50% duty ratio is implemented, the synchronous divide-by-five circuit can be implemented under the condition that only 4D flip-flops triggered by rising edges are used, compared with other circuits with the same duty ratio, the required flip-flops can save 1-2 flip-flops, and the required flip-flops have a relatively simple structure, and can effectively save area and cost in the integrated circuit, and in addition, the duty ratio of the divided signal can be kept at 50%.
In some of the embodiments, as shown in fig. 4, the divided signal synthesizing circuit 140 includes a first inverter 142, the fourth D flip-flop 141, a second inverter 143, and a first nand gate 144; the reference clock signal is input into the first inverter 142 for inverting, so as to obtain an inverted reference clock signal, and the output end of the first inverter 142 is connected to the clock edge of the fourth D flip-flop 141, so as to control the trigger timing of the fourth D flip-flop 141 by using the inverted reference clock signal. The D terminal of the fourth D flip-flop 141 is connected to the non-inverting output terminal of the second D flip-flop 122 to delay the second process signal by 1/2 of a reference clock cycle, the non-inverting output terminal of the fourth D flip-flop 141 is connected to the input terminal of the second inverter 143 for inverting the second process delay signal output by the fourth D flip-flop 141, and the fourth D flip-flop 141 is a rising edge trigger. The output of the second inverter 143 and the inverting output of the second D flip-flop 122 are connected to two inputs of the first nand gate 144, respectively.
In the first signal generating circuit 110, the first logic gate circuit 111 is a first nor gate circuit, an output end of the first nor gate circuit is connected to a D end of the first D flip-flop 112, a clock edge of the first D flip-flop 112 is connected to a reference clock signal, and the first D flip-flop 112 is triggered by a rising edge; the input of the first nor gate is connected to the non-inverting output of the first D flip-flop 112 and the non-inverting output of the third D flip-flop 132, respectively (for performing (Q1 ||q3) |, i.e., (Q1 |)/(Q3|)).
In the second signal generating circuit 120, an output terminal of the second logic gate 121 is connected to a D terminal of the second D flip-flop 122, a clock edge of the second D flip-flop 122 is connected to the reference clock signal, and the second D flip-flop 122 is triggered by a rising edge. The second logic gate 121 includes a second nand gate, a third nand gate, a fourth nand gate, and a second D flip-flop. Wherein the input terminal of the second nand gate circuit is connected to the non-inverting output terminal of the first D flip-flop 112 and the inverting output terminal of the second D flip-flop 122, respectively (for performing (Q1 & (Q2 |)) -; the input end of the third NAND gate circuit is respectively connected with the inverting output end of the first D trigger 112 and the non-inverting output end of the second D trigger 122 (used for executing ((Q1 |) & Q2) |); the input end of the fourth NAND gate circuit is respectively connected with the output end of the second NAND gate circuit and the output end of the third NAND gate circuit (for executing (((Q1 & (Q2)) -; the output of the fourth nand gate is connected to the D terminal of the second D flip-flop 122.
In the third signal generating circuit 130, the third logic gate circuit 131 is a second nor gate circuit, an output end of the second nor gate circuit is connected to a D end of the third D flip-flop 132, a clock edge of the third D flip-flop 132 is connected to a reference clock signal, and the third D flip-flop 132 is triggered by a rising edge; the input of the second nor gate is connected to the inverting output of the first D flip-flop 112 and the inverting output of the second D flip-flop 122, respectively (for performing ((Q1 |) | (Q2 |)) | (i.e., Q1& Q2)).
The method for generating a divided-by-five signal provided by the present invention is described below, and the method for generating a divided-by-five signal described below and the synchronous divided-by-five circuit described above can be referred to correspondingly to each other.
Based on any of the above embodiments, fig. 5 is a flow chart of a method for generating a divide-by-five signal according to the present invention, as shown in fig. 5, the method includes:
step 510, generating a first process signal by using a first signal generating circuit constructed based on a first logic gate circuit and a first D flip-flop;
step 520, generating a second process signal using a second signal generation circuit constructed based on a second logic gate circuit and a second D flip-flop;
step 530, generating a third process signal using a third signal generation circuit constructed based on a third logic gate circuit and a third D flip-flop;
the first logic gate circuit is used for executing a logic operation (Q1 |) & (Q3|), the second logic gate circuit is used for executing a logic operation ((Q1 |) & (Q2)) | ] ((Q1) & (Q2|)), the third logic gate circuit is used for executing a logic operation Q1& Q2, Q1 is a first process signal output by the first D trigger at the last moment, Q2 is a second process signal output by the second D trigger at the last moment, and Q3 is a third process signal output by the third D trigger at the last moment; under the action of a basic clock signal, one period of a combined state of the third process signal, the second process signal and the first process signal is 5 reference clock periods, and the combined state is cyclically changed according to the sequence of 001, 010, 011, 100 and 000;
step 540, using a frequency-divided signal synthesis circuit constructed based on the fourth D flip-flop, delaying the second process signal by 1/2 reference clock period based on the inverted reference clock signal, generating a second process delay signal, and performing logic operation on the inverted second process signal and the inverted second process delay signal to obtain a five-divided signal.
It should be noted that the execution sequence of steps 510, 520, 530 is not limited in any way in the embodiment of the present invention.
Based on any of the above embodiments, the delaying the second process signal by 1/2 reference clock period based on the inverted reference clock signal, generating a second process delay signal, and performing a logic operation on the inverted second process signal and the inverted second process delay signal to obtain a divide-by-five signal, which specifically includes:
inverting the reference clock signal based on a first inverter to obtain an inverted reference clock signal;
delaying the second process signal by 1/2 reference clock cycles with the fourth D flip-flop based on the inverted reference clock signal, generating a second process delayed signal;
inverting the second process delay signal based on a second inverter to obtain an inverted second process delay signal;
and carrying out logic operation on the inverted second process signal and the inverted second process delay signal based on the first NAND gate circuit to obtain a five-frequency division signal.
Based on any one of the above embodiments, the generating the first process signal by using the first signal generating circuit constructed based on the first logic gate circuit and the first D flip-flop specifically includes:
based on a first NOR gate circuit in the first signal generating circuit, performing logic operation on a first process signal output at a moment on an in-phase output end of a first D trigger in the first signal generating circuit and a third process signal output at a moment on an in-phase output end of a third D trigger in the third signal generating circuit to obtain a first D end input signal at a current moment;
and generating a first process signal at the current moment by using the first D trigger based on the first D end input signal at the current moment.
Based on any of the above embodiments, the generating the second process signal using a second signal generating circuit constructed based on a second logic gate circuit and a second D flip-flop is specifically configured to:
based on a second NAND gate in the second logic gate, performing logic operation on a first process signal output at one moment on an in-phase output end of the first D trigger and a second inverted process signal output at one moment on an opposite-phase output end of the second D trigger to obtain a first NAND gate output signal at the current moment;
based on a third NAND gate in the second logic gate circuit, performing logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a second process signal output at one moment on an in-phase output end of the second D trigger to obtain a second NAND gate output signal at the current moment;
based on a fourth NAND gate in the second logic gate, performing logic operation on the first NAND gate output signal and the second NAND gate output signal at the current moment to obtain a second D-terminal input signal at the current moment;
and generating a second process signal at the current moment by using the second D trigger based on the second D end input signal at the current moment.
Based on any one of the above embodiments, the generating the third process signal by using a third signal generating circuit constructed based on a third logic gate circuit and a third D flip-flop specifically includes:
based on a second NOR gate in the third signal generating circuit, carrying out logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a reverse second process signal output at one moment on an inverting output end of the second D trigger to obtain a third D end input signal at the current moment;
and generating a third process signal at the current moment by using the third D trigger based on the third D end input signal at the current moment.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A synchronous divide-by-five circuit, comprising:
a first signal generation circuit configured based on the first logic gate circuit and the first D flip-flop for generating a first process signal;
a second signal generation circuit configured based on the second logic gate circuit and the second D flip-flop for generating a second process signal;
a third signal generation circuit configured based on the third logic gate circuit and the third D flip-flop for generating a third process signal; the first logic gate circuit is used for executing a logic operation (Q1 |) & (Q3|), the second logic gate circuit is used for executing a logic operation ((Q1 |) & (Q2)) | ] ((Q1) & (Q2|)), the third logic gate circuit is used for executing a logic operation Q1& Q2, Q1 is a first process signal output by the first D trigger at the last moment, Q2 is a second process signal output by the second D trigger at the last moment, and Q3 is a third process signal output by the third D trigger at the last moment; under the action of a basic clock signal, one period of a combined state of the third process signal, the second process signal and the first process signal is 5 reference clock periods, and the combined state is cyclically changed according to the sequence of 001, 010, 011, 100 and 000;
and the frequency division signal synthesis circuit is constructed based on the fourth D trigger and is used for delaying the second process signal by 1/2 reference clock period based on the reverse reference clock signal, generating a second process delay signal, and carrying out logic operation on the reverse second process signal and the reverse second process delay signal to obtain a five-frequency division signal.
2. The synchronous divide-by-five circuit of claim 1, wherein the divided signal combining circuit comprises a first inverter, the fourth D flip-flop, a second inverter, and a first nand gate; the reference clock signal is input into the first inverter for inversion, and the output end of the first inverter is connected with the clock edge of the fourth D flip-flop; the D end of the fourth D trigger is connected with the in-phase output end of the second D trigger, the in-phase output end of the fourth D trigger is connected with the input end of the second phase inverter, and the fourth D trigger is triggered by a rising edge; the output end of the second inverter and the inverting output end of the second D trigger are respectively connected with the two input ends of the first NAND gate circuit.
3. The synchronous divide-by-five circuit of claim 1, wherein the first logic gate is a first nor gate, an output of the first nor gate is connected to a D terminal of the first D flip-flop, a clock edge of the first D flip-flop is connected to the reference clock signal, and the first D flip-flop is a rising edge trigger; the input end of the first NOR gate circuit is respectively connected with the in-phase output end of the first D trigger and the in-phase output end of the third D trigger.
4. The synchronous divide-by-five circuit of claim 1, wherein an output of the second logic gate is coupled to a D terminal of the second D flip-flop, a clock edge of the second D flip-flop is coupled to the reference clock signal, and the second D flip-flop is a rising edge trigger; the second logic gate circuit comprises a second NAND gate circuit, a third NAND gate circuit, a fourth NAND gate circuit and a second D trigger;
the input end of the second NAND gate circuit is respectively connected with the non-inverting output end of the first D trigger and the inverting output end of the second D trigger; the input end of the third NAND gate circuit is respectively connected with the inverting output end of the first D trigger and the non-inverting output end of the second D trigger; the input end of the fourth NAND gate circuit is respectively connected with the output end of the second NAND gate circuit and the output end of the third NAND gate circuit; and the output end of the fourth NAND gate circuit is connected with the D end of the second D trigger.
5. The synchronous divide-by-five circuit of claim 1, wherein the third logic gate is a second nor gate, an output of the second nor gate is connected to a D terminal of the third D flip-flop, a clock edge of the third D flip-flop is connected to the reference clock signal, and the third D flip-flop is a rising edge trigger; the input end of the second NOR gate circuit is respectively connected with the inverting output end of the first D trigger and the inverting output end of the second D trigger.
6. A divided-by-five signal generation method based on the synchronous divided-by-five circuit according to any one of claims 1 to 5, comprising:
generating a first process signal using a first signal generation circuit constructed based on a first logic gate circuit and a first D flip-flop;
generating a second process signal using a second signal generation circuit constructed based on a second logic gate circuit and a second D flip-flop;
generating a third process signal using a third signal generation circuit constructed based on a third logic gate circuit and a third D flip-flop; the first logic gate circuit is used for executing a logic operation (Q1 |) & (Q3|), the second logic gate circuit is used for executing a logic operation ((Q1 |) & (Q2)) | ] ((Q1) & (Q2|)), the third logic gate circuit is used for executing a logic operation Q1& Q2, Q1 is a first process signal output by the first D trigger at the last moment, Q2 is a second process signal output by the second D trigger at the last moment, and Q3 is a third process signal output by the third D trigger at the last moment; under the action of a basic clock signal, one period of a combined state of the third process signal, the second process signal and the first process signal is 5 reference clock periods, and the combined state is cyclically changed according to the sequence of 001, 010, 011, 100 and 000;
and delaying the second process signal by 1/2 reference clock period based on the reverse reference clock signal by using a frequency division signal synthesis circuit constructed based on the fourth D trigger to generate a second process delay signal, and carrying out logic operation on the reverse second process signal and the reverse second process delay signal to obtain a five-frequency division signal.
7. The method for generating a divided-by-five signal according to claim 6, wherein the delaying the second process signal by 1/2 reference clock period based on the inverted reference clock signal generates a second process delay signal, and performing a logic operation on the inverted second process signal and the inverted second process delay signal to obtain the divided-by-five signal, specifically comprising:
inverting the reference clock signal based on a first inverter to obtain an inverted reference clock signal;
delaying the second process signal by 1/2 reference clock cycles with the fourth D flip-flop based on the inverted reference clock signal, generating a second process delayed signal;
inverting the second process delay signal based on a second inverter to obtain an inverted second process delay signal;
and carrying out logic operation on the inverted second process signal and the inverted second process delay signal based on the first NAND gate circuit to obtain a five-frequency division signal.
8. The method of generating a divide-by-five signal according to claim 6, wherein the generating a first process signal using a first signal generating circuit constructed based on a first logic gate circuit and a first D flip-flop, specifically comprises:
based on a first NOR gate circuit in the first signal generating circuit, performing logic operation on a first process signal output at a moment on an in-phase output end of a first D trigger in the first signal generating circuit and a third process signal output at a moment on an in-phase output end of a third D trigger in the third signal generating circuit to obtain a first D end input signal at a current moment;
and generating a first process signal at the current moment by using the first D trigger based on the first D end input signal at the current moment.
9. The method of generating a divide-by-five signal according to claim 6, wherein the generating a second process signal using a second signal generating circuit constructed based on a second logic gate circuit and a second D flip-flop is specifically configured to:
based on a second NAND gate in the second logic gate, performing logic operation on a first process signal output at one moment on an in-phase output end of the first D trigger and a second inverted process signal output at one moment on an opposite-phase output end of the second D trigger to obtain a first NAND gate output signal at the current moment;
based on a third NAND gate in the second logic gate circuit, performing logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a second process signal output at one moment on an in-phase output end of the second D trigger to obtain a second NAND gate output signal at the current moment;
based on a fourth NAND gate in the second logic gate, performing logic operation on the first NAND gate output signal and the second NAND gate output signal at the current moment to obtain a second D-terminal input signal at the current moment;
and generating a second process signal at the current moment by using the second D trigger based on the second D end input signal at the current moment.
10. The method of generating a divide-by-five signal according to claim 6, wherein the generating a third process signal using a third signal generating circuit constructed based on a third logic gate circuit and a third D flip-flop, specifically comprises:
based on a second NOR gate in the third signal generating circuit, carrying out logic operation on a reverse first process signal output at one moment on an inverting output end of the first D trigger and a reverse second process signal output at one moment on an inverting output end of the second D trigger to obtain a third D end input signal at the current moment;
and generating a third process signal at the current moment by using the third D trigger based on the third D end input signal at the current moment.
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