CN116545239A - Charge pump system, power supply device, memory and electronic equipment - Google Patents

Charge pump system, power supply device, memory and electronic equipment Download PDF

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Publication number
CN116545239A
CN116545239A CN202310819502.6A CN202310819502A CN116545239A CN 116545239 A CN116545239 A CN 116545239A CN 202310819502 A CN202310819502 A CN 202310819502A CN 116545239 A CN116545239 A CN 116545239A
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China
Prior art keywords
charge pump
voltage
output
module
clock
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Granted
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CN202310819502.6A
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Chinese (zh)
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CN116545239B (en
Inventor
方刘禄
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Xinyaohui Technology Co ltd
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Xinyaohui Technology Co ltd
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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application provides a charge pump system, a power supply device, a memory and an electronic device. Further, the operational amplifier is used for obtaining a first output voltage according to the divided voltage and the reference voltage, and outputting the first output voltage to the clock driving module and the charge pump module respectively, wherein at least one of the divided voltage coefficient of the divided voltage circuit and the reference voltage is adjusted according to the voltage required by the load. Further, the clock driving module is used for outputting a first clock signal and a second clock signal to the charge pump module according to the first output voltage. The first clock signal and the second clock signal are used for controlling the charge pump module to work so that the charge pump module outputs a second output voltage according to the first output voltage. By adopting the method and the device, the output voltage of the charge pump system can be flexibly adjusted, and the ripple wave of the output voltage is reduced.

Description

Charge pump system, power supply device, memory and electronic equipment
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a charge pump system, a power supply device, a memory, and an electronic device.
Background
The charge pump has the advantages of high efficiency, small volume, low noise and the like, and is widely applied to chips such as memories, display drivers and the like. In a charge pump, the output voltage of the charge pump is generally controlled to rise or fall by controlling the intermittent on and off of a clock module in the charge pump, so as to control the charge pump circuit to output a stable high voltage. However, when the clock module stops working, the duty ratio of the clock signal generated by the clock module may be locally distorted, so that the output voltage of the charge pump circuit is rippled, and the performance of the load circuit of the charge pump is further affected.
Disclosure of Invention
The embodiment of the application provides a charge pump system, a power supply device, a memory and electronic equipment, which can flexibly adjust the output voltage of the charge pump system, reduce the ripple of the output voltage and have strong applicability.
In a first aspect, embodiments of the present application provide a charge pump system including an output voltage control module, a clock drive module, and a charge pump module. The output voltage control module comprises a voltage dividing circuit and an operational amplifier. The first connecting end of the voltage dividing circuit is connected with the voltage output end of the charge pump module, the second connecting end of the voltage dividing circuit is grounded, the third connecting end of the voltage dividing circuit is connected with the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier is connected with the reference voltage, and the output end of the operational amplifier is connected with the input end of the clock driving module and the voltage input end of the charge pump module. The first output end of the clock driving module is connected with the first signal input end of the charge pump module, the second output end of the clock driving module is connected with the second signal input end of the charge pump module, and the voltage output end of the charge pump module is used for being connected with a load. In the case of the charge pump system, the voltage dividing circuit is used for outputting the divided voltage to the operational amplifier according to the sampled output voltage of the charge pump module. Further, the operational amplifier is used for obtaining a first output voltage according to the divided voltage and the reference voltage, and outputting the first output voltage to the clock driving module and the charge pump module respectively. At least one of the divided voltage coefficient of the voltage dividing circuit and the reference voltage is adjusted according to the voltage required by the load. It will be appreciated that the divided voltage coefficient may be used to adjust the divided voltage to change the magnitude of the first output voltage, and the reference voltage may also be used to change the magnitude of the first output voltage to meet the voltage requirements for powering the clock drive module and the charge pump module. Further, the clock driving module is used for outputting a first clock signal and a second clock signal to the charge pump module according to the first output voltage. The first clock signal and the second clock signal are used for driving the charge pump module to work so that the charge pump module outputs a second output voltage according to the first output voltage.
It can be understood that the magnitude of at least one parameter of the divided voltage coefficient and the reference voltage is flexibly adjusted according to the voltage of the load requirement, so that the magnitude of the first output voltage output by the operational amplifier is adjusted to meet the voltage requirement for supplying power to the clock driving module and the charge pump module, and finally the second output voltage output by the charge pump module meets the voltage requirement of the load, so that the magnitude of the output voltage of the charge pump system is flexibly adjusted. In addition, since the operational amplifier can output an internal power supply voltage (i.e., a first output voltage) to the charge pump module and the clock driving module, the output voltage ripple (i.e., the ripple of a second output voltage) of the charge pump module is not affected by an external power supply, and the clock signal output by the clock driving module is a continuous clock signal, so that the clock driving module does not need to be controlled to be repeatedly turned on and off, the influence of the clock driving module on the output voltage ripple of the output voltage is eliminated, and the output voltage ripple of the charge pump system is greatly reduced.
With reference to the first aspect, in one possible implementation manner, the divided voltage coefficient is positively related to the voltage of the load demand, specifically, when the voltage of the load demand increases, the divided voltage coefficient increases, and the first output voltage increases, that is, when the magnitude of the first output voltage increases. When the voltage required by the load is reduced, the divided voltage coefficient is reduced, and the first output voltage is reduced, namely the amplitude of the first output voltage is reduced at the moment. It can be seen that the magnitude of the divided voltage coefficient is flexibly adjusted according to the voltage required by the load, so that the magnitude of the first output voltage is increased or reduced, and the magnitude of the first output voltage meets the voltage requirement for supplying power to the clock driving module and the charge pump module.
With reference to the first aspect, in one possible implementation manner, the reference voltage is positively related to the voltage of the load demand, in particular, when the voltage of the load demand increases, the reference voltage increases, and the first output voltage increases, i.e. when the magnitude of the first output voltage increases. When the voltage required by the load is reduced, the reference voltage is reduced, and the first output voltage is reduced, namely the amplitude of the first output voltage is reduced at the moment. It will be appreciated that the magnitude of the reference voltage is flexibly adjusted according to the voltage required by the load, so as to increase or decrease the magnitude of the first output voltage, and the magnitude of the first output voltage meets the voltage requirement for supplying power to the clock driving module and the charge pump module.
With reference to the first aspect, in one possible implementation manner, the charge pump system further includes a first selector and a second selector. The output end of the operational amplifier is connected with the first input end of the first selector and the first input end of the second selector, the second input end of the first selector and the second input end of the second selector are used for being connected with a power supply, the control end of the first selector and the control end of the second selector are used for being connected with a controller, the output end of the first selector is connected with the voltage input end of the charge pump module, and the output end of the second selector is connected with the input end of the clock driving module. And under the condition that the output voltage ripple required by the charge pump system is smaller than a first threshold value, the first selector is used for receiving a first control signal issued by the controller and outputting a first output voltage to the charge pump module based on the first control signal. The second selector is used for receiving a second control signal issued by the controller and outputting a first output voltage to the clock driving module based on the second control signal.
It can be appreciated that, in the case that the output voltage ripple required by the charge pump system is smaller than the first threshold, the first selector and the second selector output the first output voltage (i.e. the internal power supply voltage) to the charge pump module and the clock driving module, respectively, so that the magnitude of the output voltage ripple of the charge pump module (i.e. the ripple of the second output voltage) is not affected by the external power supply, thereby greatly reducing the output voltage ripple of the charge pump module.
With reference to the first aspect, in one possible implementation manner, in a case where a high-frequency ripple of the power supply is greater than a low-frequency ripple of the power supply, the first selector is configured to receive a third control signal issued by the controller, and output a first output voltage to the charge pump module based on the third control signal. The second selector is used for receiving a fourth control signal sent by the controller and outputting a power supply voltage of the power supply to the clock driving module based on the fourth control signal. Further, the clock driving module is used for outputting a third clock signal and a fourth clock signal to the charge pump module according to the power supply voltage of the power supply. The third clock signal and the fourth clock signal are used for controlling the charge pump module to work so that the charge pump module outputs a third output voltage according to the first output voltage.
With reference to the first aspect, in a possible implementation manner, in a case where a high-frequency ripple of the power supply is smaller than a low-frequency ripple of the power supply, the first selector is configured to receive a fifth control signal issued by the controller, and output a power supply voltage of the power supply to the charge pump module based on the fifth control signal. The second selector is used for receiving a sixth control signal issued by the controller and outputting a first output voltage to the clock driving module based on the sixth control signal. Further, the clock driving module is used for outputting a fifth clock signal and a sixth clock signal to the charge pump module according to the first output voltage. The fifth clock signal and the sixth clock signal are used for controlling the charge pump module to work so that the charge pump module outputs a fourth output voltage according to the power supply voltage of the power supply.
With reference to the first aspect, in one possible implementation manner, the charge pump module includes an M-stage charge pump circuit, a first input terminal of the 1 st stage charge pump circuit is used as a voltage input terminal of the charge pump module, an output terminal of the i-stage charge pump circuit is connected to the first input terminal of the i+1st stage charge pump circuit, and an output terminal of the M-stage charge pump circuit is used as a voltage output terminal of the charge pump module. Wherein M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than M. The M-stage charge pump circuits comprise at least one stage of charge pump circuits and other stages of charge pump circuits, wherein the second input end of each stage of charge pump circuit in the at least one stage of charge pump circuits is used as a first signal input end of the charge pump module, and the second input end of each stage of charge pump circuit in the other stages of charge pump circuits is used as a second signal input end of the charge pump module.
With reference to the first aspect, in one possible implementation manner, the charge pump circuit includes a switch unit and a capacitor unit, where a first connection end of the switch unit is used as a first input end of the charge pump circuit, a second connection end of the switch unit is connected with a first connection end of the capacitor unit and then used as an output end of the charge pump circuit, and a second connection end of the capacitor unit is used as a second input end of the charge pump circuit. When the first clock signal is at a high level and the second clock signal is at a low level, the capacitor unit in each of the at least one stage of charge pump circuits charges the capacitor unit in the next stage of charge pump circuit of each of the at least one stage of charge pump circuits. Or when the first clock signal is at a low level and the second clock signal is at a high level, the capacitor unit in each of the other stages charges the capacitor unit in the next stage of the other stages.
With reference to the first aspect, in one possible implementation manner, the clock driving module includes an oscillator and a clock buffer; the input end of the oscillator is used as the input end of the clock driving module, the output end of the oscillator is connected with the input end of the clock buffer, the first output end of the clock buffer is used as the first output end of the clock driving module, and the second output end of the clock buffer is used as the second output end of the clock driving module. The oscillator is used for outputting an oscillation signal to the clock buffer according to the first output voltage, and the clock buffer is used for outputting a first clock signal and a second clock signal to the charge pump module according to the oscillation signal.
With reference to the first aspect, in one possible implementation manner, a clock period of each of the first clock signal and the second clock signal is determined by at least one of a current required by the load, an energy conversion efficiency of the charge pump system, and an output voltage ripple range of the charge pump system.
It can be understood that the clock period of each clock signal can be designed according to the current required by the load, the energy conversion efficiency of the charge pump system and the output voltage ripple range of the charge pump system, so that the output voltage ripple of the charge pump module accords with the output voltage ripple range of the charge pump system, and the applicability is stronger.
In a second aspect, embodiments of the present application provide a power supply device comprising a housing and a charge pump system as provided in any one of the first aspect and possible embodiments thereof disposed inside the housing. It is understood that the power supply device may be a low dropout regulator. It can be understood that the charge pump system can output low ripple output voltage, so that the power supply device can output low ripple output voltage to the load, thereby reducing the cost and power consumption of the power supply device and having strong applicability.
In a third aspect, embodiments of the present application provide a memory comprising an array of memory cells and a charge pump system as provided in any one of the first aspect and its possible embodiments. Wherein the charge pump system may power the memory cell array. It can be appreciated that the charge pump system can output a low ripple output voltage to the memory cell array to supply power, improving the stability of the operation of the memory.
In a fourth aspect, embodiments of the present application provide an electronic device comprising a power management chip and a charge pump system as provided in any one of the first aspect and possible implementations thereof disposed on the power management chip. It is understood that the charge pump system may supply power to the power management chip, and the power management chip may process the power supply voltage provided by the charge pump system to drive the subsequent circuit in the electronic device to operate.
In the embodiment of the application, the magnitude of at least one parameter in the divided voltage coefficient and the reference voltage is flexibly adjusted according to the voltage of the load requirement, so that the magnitude of the first output voltage output by the operational amplifier is adjusted to meet the voltage requirement for supplying power to the clock driving module and the charge pump module, and finally the second output voltage output by the charge pump module meets the voltage requirement of the load, and the magnitude of the output voltage of the charge pump system is flexibly adjusted. In addition, since the operational amplifier can output an internal power supply voltage (i.e., a first output voltage) to the charge pump module and the clock driving module, the output voltage ripple (i.e., the ripple of a second output voltage) of the charge pump module is not affected by an external power supply, and the clock signal output by the clock driving module is a continuous clock signal, so that the clock driving module does not need to be controlled to be repeatedly turned on and off, the influence of the clock driving module on the output voltage ripple of the output voltage is eliminated, and the output voltage ripple of the charge pump module is greatly reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first configuration of a charge pump system according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a second configuration of a charge pump system according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a third configuration of a charge pump system according to an embodiment of the present disclosure;
FIG. 4 is a schematic waveform diagram of a clock signal provided by a clock driving module according to an embodiment of the present disclosure;
FIG. 5 is a fourth schematic diagram of a charge pump system according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a charge pump module according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a power supply device provided in an embodiment of the present application;
FIG. 8 is a schematic diagram of a memory according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
For a better understanding of the technical solutions of the present disclosure, the related art related to the present disclosure is further described in detail below.
The structure and operation principle of the charge pump system provided in the present application will be exemplified with reference to fig. 1 to 6.
Referring to fig. 1, fig. 1 is a schematic diagram of a first structure of a charge pump system according to an embodiment of the present application. As shown in fig. 1, the charge pump system 1 includes an output voltage control module 11, a clock driving module 12, and a charge pump module 13, and the output voltage control module 11 includes a voltage dividing circuit 111 and an operational amplifier OPA. The first connection end of the voltage dividing circuit 111 is connected to the voltage output end of the charge pump module 13, the second connection end of the voltage dividing circuit 111 is grounded, the third connection end of the voltage dividing circuit 111 is connected to the inverting input end of the operational amplifier OPA, the non-inverting input end of the operational amplifier OPA is connected to the reference voltage Vref, the output end of the operational amplifier OPA is connected to the input end of the clock driving module 12 and the voltage input end of the charge pump module 13, the first output end of the clock driving module 12 is connected to the first signal input end of the charge pump module 13, the second output end of the clock driving module 12 is connected to the second signal input end of the charge pump module 13, and the voltage output end of the charge pump module 13 is connected to the load 2.
The voltage dividing circuit 111 may be formed by connecting a plurality of resistors in series, or connecting a plurality of resistors in parallel, or connecting a plurality of resistors in series and parallel. Illustratively, as shown in fig. 1, the voltage dividing circuit 111 may be composed of resistors R1, … …, and a resistor Rn.
In one embodiment, in the case of operation of the charge pump system 1, the voltage dividing circuit 111 is configured to output the divided voltage to the operational amplifier OPA according to the sampled output voltage V2 of the charge pump module 13. Further, the operational amplifier OPA is configured to obtain a first output voltage V1 according to the divided voltage and the reference voltage Vref, and output the first output voltage V1 to the clock driving module 12 and the charge pump module 13, respectively. In a specific implementation, the voltage dividing circuit 111 may sample the output voltage of the charge pump module 13 to obtain a sampled output voltage V2 of the charge pump module 13. The voltage dividing circuit 111 may divide the sampling output voltage V2 to obtain a divided voltage and output the divided voltage to the operational amplifier OPA. The operational amplifier OPA may amplify a difference between the reference voltage Vref and the divided voltage to obtain a first output voltage V1, and output the first output voltage V1 to the clock driving module 12 and the charge pump module 13, respectively.
Wherein at least one of the divided voltage coefficient of the voltage dividing circuit 111 and the reference voltage Vref is adjusted according to the voltage required by the load 2. It will be appreciated that the divided voltage coefficient may be used to adjust the divided voltage to change the magnitude of the first output voltage V1, and the reference voltage Vref may also be used to change the magnitude of the first output voltage V1, thereby meeting the voltage requirements for powering the clock driving module 12 and the charge pump module 13. Also, the output voltage control module 11 may output an internal power supply voltage (i.e., a first output voltage V1) to the clock driving module 12 and the charge pump module 13, and the internal power supply may supply the power supply voltage (i.e., the first output voltage V1) for driving the clock driving module 12 and the charge pump module 13 to operate to the clock driving module 12 and the charge pump module 13.
Further, the clock driving module 12 may output the first clock signal CLK and the second clock signal CLKB to the charge pump module 13 according to the first output voltage V1 output by the output voltage control module 11. The first clock signal CLK and the second clock signal CLKB are used for driving the charge pump module 13 to operate, so that the charge pump module 13 outputs the second output voltage Vout according to the first output voltage V1.
In a specific implementation, the first signal input end of the charge pump module 13 is configured to receive the first clock signal CLK output by the clock driving module 12, the second signal input end of the charge pump module 13 is configured to receive the second clock signal CLKB output by the clock driving module 12, and the voltage input end of the charge pump module 13 is configured to receive the first output voltage V1. At this time, the first clock signal CLK and the second clock signal CLKB may drive the charge pump module 13 to operate, so that the charge pump module 13 performs voltage conversion on the first output voltage V1 and outputs the second output voltage Vout. When the voltage output terminal of the charge pump module 13 is used for connecting the load 2, the charge pump module 13 outputs a second output voltage Vout to the load 2 to supply power to the load 2.
In this embodiment of the present application, the magnitude of at least one parameter of the divided voltage coefficient and the reference voltage Vref is flexibly adjusted according to the voltage required by the load 2, so as to adjust the magnitude of the first output voltage V1 output by the operational amplifier OPA to meet the voltage requirement of supplying power to the clock driving module 12 and the charge pump module 13, and finally, make the second output voltage Vout output by the charge pump module 13 meet the voltage requirement of the load 2, so as to flexibly adjust the magnitude of the output voltage of the charge pump system 1. In addition, since the operational amplifier OPA can output an internal power supply voltage (i.e., the first output voltage V1) to the charge pump module 13 and the clock driving module 12, the magnitude of the output voltage ripple (i.e., the ripple of the second output voltage Vout) of the charge pump module 13 is not affected by the external power supply, and the clock signal output by the clock driving module 12 is a continuous clock signal, so that the clock driving module 12 does not need to be controlled to be turned on and off repeatedly, and the influence of the clock driving module 12 on the output voltage ripple of the output voltage is eliminated, thereby greatly reducing the output voltage ripple of the charge pump module 13. In addition, the supply of external power to the charge pump module 13 and the clock drive module 12 can be avoided, thereby reducing the cost and power consumption of the charge pump system 1.
In one embodiment, the divided voltage coefficient is positively related to the voltage required by the load 2, wherein the divided voltage coefficient is the ratio of the preset reference voltage to the voltage required by the load 2. Specifically, when the voltage demanded by the load 2 increases, the divided voltage coefficient increases, and the first output voltage increases, that is, the magnitude of the first output voltage V1 increases at this time. When the voltage required by the load 2 decreases, the divided voltage coefficient decreases, and the first output voltage V1 decreases, i.e., the magnitude of the first output voltage V1 decreases at this time. At this time, the reference voltage Vref is a predetermined reference voltage. It follows that the magnitude of the divided voltage coefficient is flexibly adjusted according to the voltage required by the load 2, so that the magnitude of the first output voltage V1 is increased or decreased, and the magnitude of the first output voltage V1 satisfies the voltage requirement for supplying power to the clock driving module 12 and the charge pump module 13. Illustratively, the voltage dividing circuit 111 includes a resistor ladder composed of n resistors, and the divided voltage coefficient of the voltage dividing circuit 111 is the divided voltage coefficient of the resistor ladder.
In one embodiment, the reference voltage Vref is positively correlated to the voltage demanded by the load 2. Specifically, when the voltage demanded by the load 2 increases, the reference voltage Vref increases, and the first output voltage V1 increases, that is, the magnitude of the first output voltage V1 increases at this time. When the voltage required by the load 2 decreases, the reference voltage Vref decreases, and the first output voltage V1 decreases, i.e., the magnitude of the first output voltage V1 decreases at this time. At this time, the divided voltage coefficient is a ratio of a preset reference voltage to a preset load 2 voltage, and the preset load voltage is an initial voltage before the voltage required by the load 2 changes. It will be appreciated that the magnitude of the reference voltage Vref is flexibly adjusted according to the voltage required by the load 2, so as to increase or decrease the magnitude of the first output voltage V1, and the magnitude of the first output voltage V1 satisfies the voltage requirement for supplying power to the clock driving module 12 and the charge pump module 13.
In the embodiment of the present application, the operational amplifier OPA may increase or decrease the magnitude of the first output voltage V1 according to the real-time adjusted divided voltage and the reference voltage Vref, so as to meet the voltage requirement of supplying power to the clock driving module 12 and the charge pump module 13, so that the second output voltage Vout meets the power supply voltage requirement of the load 2.
Referring to fig. 2, fig. 2 is a schematic diagram of a second structure of a charge pump system according to an embodiment of the present application. As shown in fig. 2, the charge pump system 1 further includes a first selector Mux1 and a second selector Mux2. The output end of the operational amplifier OPA is connected to the first input end of the first selector Mux1 and the first input end of the second selector Mux2, the second input end of the first selector Mux1 and the second input end of the second selector Mux2 are used for being connected to a power supply, the control end sel0 of the first selector Mux1 and the control end sel1 of the second selector Mux2 are used for being connected to the controller 3, the output end of the first selector Mux1 is connected to the voltage input end of the charge pump module 13, and the output end of the second selector Mux2 is connected to the input end of the clock driving module 12.
In one embodiment, in an application scenario where the charge pump system 1 is applied to a low output voltage ripple, the controller 3 is configured to issue a first control signal to the first selector Mux1 and issue a second control signal to the second selector Mux2 when the output voltage ripple required by the charge pump system 1 is less than a first threshold. Illustratively, the first control signal is low and the second control signal is low. At this time, the first selector Mux1 is configured to receive the first control signal sent by the controller 3, and output the first output voltage V1 to the charge pump module 13 based on the first control signal. The second selector Mux2 is configured to receive a second control signal sent by the controller 3, and output the first output voltage V1 to the clock driving module 12 based on the second control signal.
In this embodiment of the present application, the operational amplifier OPA outputs an internal power supply voltage (i.e., the first output voltage V1) to the charge pump module 13 and the clock driving module 12, so that the output voltage ripple (i.e., the ripple of the second output voltage Vout) of the charge pump module 13 is not affected by the external power supply, and the clock signal output by the clock driving module 12 is a continuous clock signal, so that the clock driving module 12 does not need to be controlled to be repeatedly turned on and off, and the influence of the clock driving module 12 on the output voltage ripple of the output voltage is eliminated, thereby greatly reducing the output voltage ripple of the charge pump module 13.
In one embodiment, the controller 3 is configured to issue the third control signal to the first selector Mux1 and issue the fourth control signal to the second selector Mux2 when the high-frequency ripple of the power supply required by the charge pump system 1 is greater than the low-frequency ripple of the power supply. Illustratively, the third control signal is low and the fourth control signal is high. At this time, the first selector Mux1 is configured to receive the third control signal sent by the controller 3, and output the first output voltage V1 to the charge pump module 13 based on the third control signal. The second selector Mux2 is configured to receive a fourth control signal sent by the controller 3, and output a supply voltage VCC of the power supply to the clock driving module 12 based on the fourth control signal. The clock driving module 12 is configured to output a third clock signal and a fourth clock signal to the charge pump module 13 according to a power supply voltage VCC of the power supply. The third clock signal and the fourth clock signal are used for controlling the charge pump module 13 to operate, so that the charge pump module 13 outputs a third output voltage according to the first output voltage V1.
In one embodiment, the controller 3 is configured to issue the fifth control signal to the first selector Mux1 and issue the sixth control signal to the second selector Mux2 when the high frequency ripple of the power supply required by the charge pump system 1 is smaller than the low frequency ripple of the power supply. Illustratively, the fifth control signal is high and the sixth control signal is low. At this time, the first selector Mux1 is configured to receive the fifth control signal sent from the controller 3, and output the power supply voltage VCC of the power supply to the charge pump module 13 based on the fifth control signal. The second selector Mux2 is configured to receive a sixth control signal sent by the controller 3, and output the first output voltage V1 to the clock driving module 12 based on the sixth control signal. The clock driving module 12 is configured to output a fifth clock signal and a sixth clock signal to the charge pump module 13 according to the first output voltage V1. Illustratively, the fifth clock signal and the first clock signal CLK are the same clock signal, and the sixth clock signal and the second clock signal CLKB are the same clock signal. The fifth clock signal and the sixth clock signal are used for controlling the charge pump module 13 to operate, so that the charge pump module 13 outputs a fourth output voltage according to the power supply voltage VCC of the power supply.
The charge pump system 1 provided by the embodiment of the application is suitable for application scenes of low-output voltage ripples, application scenes of power supplies with high-frequency ripples larger than low-frequency ripples and application scenes of power supplies with high-frequency ripples smaller than low-frequency ripples, and is more widely applied.
Referring to fig. 3, fig. 3 is a schematic diagram of a third structure of a charge pump system according to an embodiment of the present application. As shown in fig. 3, the clock driving module 12 includes an oscillator 121 and a clock buffer 122. The input end of the oscillator 121 is the input end of the clock driving module 12, and the output end of the oscillator 121 is connected to the input end of the clock buffer 122. The input of the oscillator 121 is connected to the output of the second selector Mux2, or the input of the oscillator 121 may be directly connected to the output of the operational amplifier OPA. A first output terminal of the clock buffer 122 is used as a first output terminal of the clock driving module 12, that is, the clock buffer 122 can output the first clock signal CLK to the charge pump module 13, and a second output terminal of the clock buffer 122 is used as a second output terminal of the clock driving module 12, that is, the clock buffer 122 can output the second clock signal CLKB to the charge pump module 13.
In the case that the output voltage ripple required by the charge pump system 1 is smaller than the first threshold, the oscillator 121 is configured to receive the first output voltage V1 output by the operational amplifier OPA. The oscillator 121 is configured to generate an oscillation signal according to the first output voltage V1 and output the oscillation signal to the clock buffer 122. The clock buffer 122 is used for generating a first clock signal CLK and a second clock signal CLKB from the oscillation signal and outputting the first clock signal CLK and the second clock signal CLKB to the charge pump module 13.
In the case where the high frequency ripple of the power supply is larger than the low frequency ripple of the power supply, the oscillator 121 is configured to receive the power supply voltage VCC of the power supply output by the operational amplifier OPA. The oscillator 121 is configured to generate an oscillation signal from a power supply voltage VCC of a power supply, and output the oscillation signal to the clock buffer 122. The clock buffer 122 is used for generating a third clock signal and a fourth clock signal according to the oscillation signal, and outputting the third clock signal and the fourth clock signal to the charge pump module 13.
In case that the high frequency ripple of the power supply is smaller than the low frequency ripple of the power supply, the oscillator 121 is configured to receive the first output voltage V1 outputted by the operational amplifier OPA. The oscillator 121 is configured to generate an oscillation signal according to the first output voltage V1 and output the oscillation signal to the clock buffer 122. The clock buffer 122 is configured to generate a fifth clock signal and a sixth clock signal according to the oscillation signal, and output the fifth clock signal and the sixth clock signal to the charge pump module 13.
In the embodiment of the present application, the clock driving module 12 can adjust two clock signals in real time according to the first output voltage V1 or the power voltage VCC of the power supply, so that the application is more flexible.
For convenience of description, the first clock signal CLK and the second clock signal CLKB will be described as examples.
For example, when the duty ratio of the first clock signal CLK and the second clock signal CLKB is 50%, waveforms of the first clock signal CLK and the second clock signal CLKB are as shown in fig. 4, the first clock signal CLK and the second clock signal CLKB are inverse signals to each other, when the first clock signal CLK is a high level signal, the second clock signal CLKB is a low level signal, and when the first clock signal CLK is a low level signal, the second clock signal CLKB is a high level signal.
In one embodiment, the clock period of each of the first clock signal CLK and the second clock signal CLKB is determined by at least one of the current demanded by the load 2, the energy conversion efficiency of the charge pump system 1, and the output voltage ripple range of the charge pump system 1. The current required by the load 2, that is, the current required by the load 2 after the charge pump system 1 is externally connected with the load 2, can make the load 2 be in the current size of normal operation. The energy conversion efficiency of the charge pump system 1 may be a ratio of the output power to the input power of the charge pump system 1. It should be understood that the clock period of each clock signal may be designed according to the current required by the load 2, the energy conversion efficiency of the charge pump system 1, and the output voltage ripple range of the charge pump system 1, so that the output voltage ripple of the charge pump module 13 conforms to the output voltage ripple range of the charge pump system 1, and the applicability is higher. It is understood that the first clock signal CLK and the second clock signal CLKB in the present embodiment may be replaced with the third clock signal and the fourth clock signal, or replaced with the fifth clock signal and the sixth clock signal, which will not be described in detail below.
Referring to fig. 5, fig. 5 is a schematic diagram of a fourth structure of a charge pump system according to an embodiment of the present application. As shown in fig. 5, the charge pump module 13 includes an M-stage charge pump circuit. Wherein the first input of the stage 1 charge pump circuit serves as the voltage input of the charge pump module 13. The first input terminal of the 1 st stage charge pump circuit is connected to the output terminal of the first selector Mux1, or the first input terminal of the 1 st stage charge pump circuit may be directly connected to the output terminal of the operational amplifier OPA. The output end of the i-th stage charge pump circuit is connected to the first input end of the i+1-th stage charge pump circuit, that is, the input end of each stage of charge pump circuit in the charge pump module 13 is connected to the output end of the previous stage of charge pump circuit, and the output end of the M-th stage of charge pump circuit is used as the voltage output end of the charge pump module 13. Wherein M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than M.
In the case that the output voltage ripple required by the charge pump system 1 is smaller than the first threshold, the M-stage charge pump circuit is configured to receive the first output voltage V1 output by the output voltage control module 11, boost the magnitude of the first output voltage V1 to a second output voltage Vout, and output the second output voltage Vout to the load 2.
When the high-frequency ripple of the power supply is larger than the low-frequency ripple of the power supply, the M-stage charge pump circuit is configured to receive the first output voltage V1 output by the first selector Mux1, boost the magnitude of the first output voltage V1 to a third output voltage, and output the third output voltage to the load 2.
When the high-frequency ripple of the power supply is smaller than the low-frequency ripple of the power supply, the M-stage charge pump circuit is configured to receive the power supply voltage VCC of the power supply output by the first selector Mux1, boost the power supply voltage VCC of the power supply to a fourth output voltage, and output the fourth output voltage to the load 2.
In one embodiment, the M-stage charge pump circuit includes at least one stage of charge pump circuits, a second input of each of the at least one stage of charge pump circuits serving as a first signal input of the charge pump module 13, and other stages of charge pump circuits, a second input of each of the other stages of charge pump circuits serving as a second signal input of the charge pump module 13.
Illustratively, at least one stage of the charge pump circuit may be an odd stage of the charge pump circuit, and the other stages of the charge pump circuit may be even stages of the charge pump circuit, as particularly shown in fig. 5. Illustratively, at least one stage of the charge pump circuits may be a first S stage of the M stages of the charge pump circuits, and the other stages of the charge pump circuits may be s+1st to mth stages of the charge pump circuits, S being a positive integer less than M. Illustratively, at least one stage of the charge pump circuit may be an even stage of the charge pump circuit, and the other stages of the charge pump circuit may be an odd stage of the charge pump circuit.
In one embodiment, for each stage of the M stages of charge pump circuits, the charge pump circuit includes a switch unit and a capacitor unit, a first connection terminal of the switch unit is used as a first input terminal of the charge pump circuit, a second connection terminal of the switch unit is connected with the first connection terminal of the capacitor unit and then used as an output terminal of the charge pump circuit, and a second connection terminal of the capacitor unit is used as a second input terminal of the charge pump circuit. In a first period of each clock cycle, when the first clock signal CLK is high and the second clock signal CLKB is low, the capacitance unit in each of the at least one stage charge pump circuits charges the capacitance unit in the next one of the at least one stage charge pump circuits. At this time, the capacitor unit in the next stage charge pump circuit stores the output charge of the previous stage charge pump circuit. In the second period of each clock cycle, when the first clock signal CLK is at a low level and the second clock signal CLKB is at a high level, the capacitance unit in each of the other stages charges the capacitance unit in the next stage of the other stages. At this time, the capacitor unit in the next stage charge pump circuit stores the output charge of the previous stage charge pump circuit. At the end of each clock cycle, the capacitor unit in the mth stage charge pump circuit stores the output charge of the previous M-1 stage charge pump circuit, thereby outputting the second output voltage Vout required by the load 2.
It will be appreciated that the implementation of the charge pump module 13 outputting the third output voltage when the charge pump module 13 receives the third clock signal and the fourth clock signal, and the implementation of the charge pump module 13 outputting the fourth output voltage when the charge pump module 13 receives the fifth clock signal and the sixth clock signal can be referred to the implementation of the charge pump module 13 outputting the second output voltage Vout when the charge pump module 13 receives the first clock signal CLK and the second clock signal CLKB.
The first period of time may be before the second period of time or after the second period of time.
In one embodiment, a switching unit in a charge pump circuit includes a switch, a multi-stage diode. The capacitance unit includes a multi-stage capacitance.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a charge pump module according to an embodiment of the present application. As shown in fig. 6, this structure uses a diode as a charge transfer device, and the charge pump module 13 is composed of five stages of charge pump circuits. Each stage of the charge pump circuit includes a diode and a capacitor, and a first connection terminal of the diode included in the 1 st stage of the charge pump circuit is used as a voltage input terminal of the charge pump module 13, and may be connected to an output terminal of the first selector Mux1, or may also be directly connected to an output terminal of the operational amplifier OPA. The second connection end of the diode included in the 5 th stage charge pump circuit is used as the voltage output end of the charge pump module 13, the input end in each stage charge pump circuit is connected with the output end of the previous stage charge pump circuit, namely the first connection end of the diode in each stage charge pump circuit is connected with the second connection end of the diode in the previous stage charge pump circuit, and the second connection end of the diode in each stage charge pump circuit is connected with the first connection end of the capacitor and then used as the output end of the charge pump circuit. The second connection terminal of the capacitor in the odd-numbered stage charge pump circuit is used as the second input terminal of the charge pump circuit and is used for receiving any one of the first clock signal CLK, the third clock signal and the fifth clock signal output by the clock driving module 12, and the second connection terminal of the capacitor in the even-numbered stage charge pump circuit is used as the second input terminal of the charge pump circuit and is used for receiving any one of the second clock signal CLKB, the fourth clock signal and the sixth clock signal output by the clock driving module 12.
Referring to fig. 6 and fig. 4 together, as shown in fig. 4, the first clock signal CLK and the second clock signal CLKB generated by the clock driving module 12, when the charge pump module 13 receives the first output voltage V1, the first diode D1 in the 1 st stage charge pump circuit is turned on to charge the first capacitor C1, where va=v1. At time t1, the first clock signal CLK transitions to a high level and the second clock signal CLKB transitions to a low level. Since the voltage drop across the first capacitor C1 of the stage 1 charge pump circuit cannot be abrupt, va=v1+vdd at this time, and since the negative voltage of the first diode D1 is greater than the positive voltage at this time, the first diode D1 is in the off state. Wherein VDD is the magnitude of the first clock signal CLK and the second clock signal CLKB. For example, the magnitudes of the first clock signal CLK and the second clock signal CLKB may be equal to the magnitude of the first output voltage V1, i.e., vdd=v1. At time t2, the first clock signal CLK transitions to a low level and the second clock signal CLKB transitions to a high level. The second diode D2 of the 2 nd stage charge pump circuit is turned on to charge the second capacitor C2, where vb=v1+vdd+vdd. In this way, the voltages at Vc, vd and Ve are stepped up by repeating the charge and discharge through the third diode D3 and the third capacitor C3 in the 3 rd stage charge pump, the fourth diode D4 and the fourth capacitor C4 in the 4 th stage charge pump, and the fifth diode D5 and the fifth capacitor C5 in the 5 th stage charge pump until the charge pump module 13 boosts the magnitude of the first output voltage V1 to the second output voltage Vout and outputs the second output voltage Vout to the load 2.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a power supply device according to an embodiment of the present application. As shown in fig. 7, the power supply device 4 includes a housing 41 and a charge pump system 1 provided inside the housing 41. The working process of the charge pump system 1 can be specifically referred to the embodiments corresponding to fig. 2 to 6, and is not repeated here. Since the charge pump system 1 can output low ripple output voltage, the power supply device 4 can output voltage meeting different ripple requirements to the load 2, thereby reducing the cost and power consumption of the power supply device 4 and having strong applicability.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a memory according to an embodiment of the present application. As shown in fig. 8, the memory 5 includes a memory cell array 51 and a charge pump system 1. The charge pump system 1 can output voltages meeting different ripple requirements to the memory cell array 51 to supply power, so that the stability of the operation of the memory is improved.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 9, the electronic device 6 includes a power management chip 61 and a charge pump system 1 provided on the power management chip 61. The charge pump system 1 may supply power to the power management chip 61, and the power management chip 61 may process a supply voltage provided by the charge pump system 1 to drive a subsequent circuit in the electronic device 6 to operate.
It should be noted that the above-described terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. It will be understood that the examples corresponding to fig. 1 to 6 are only for explaining the embodiments of the present application, and should not be construed as limiting, and that in alternative implementations, fig. 1 to 6 may also have other implementations, for example, the diode in fig. 6 may be replaced by other devices or switching circuits having a switching effect, which are not listed here.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (13)

1. The charge pump system is characterized by comprising an output voltage control module, a clock driving module and a charge pump module, wherein the output voltage control module comprises a voltage dividing circuit and an operational amplifier; the first connecting end of the voltage dividing circuit is connected with the voltage output end of the charge pump module, the second connecting end of the voltage dividing circuit is grounded, the third connecting end of the voltage dividing circuit is connected with the inverting input end of the operational amplifier, the non-inverting input end of the operational amplifier is connected with a reference voltage, the output end of the operational amplifier is connected with the input end of the clock driving module and the voltage input end of the charge pump module, the first output end of the clock driving module is connected with the first signal input end of the charge pump module, the second output end of the clock driving module is connected with the second signal input end of the charge pump module, and the voltage output end of the charge pump module is used for being connected with a load;
The voltage dividing circuit is used for outputting divided voltage to the operational amplifier according to the sampling output voltage of the charge pump module; the operational amplifier is used for obtaining a first output voltage according to the divided voltage and the reference voltage, and outputting the first output voltage to the clock driving module and the charge pump module respectively, wherein at least one of the divided voltage coefficient of the divided voltage circuit and the reference voltage is regulated according to the voltage required by the load;
the clock driving module is used for outputting a first clock signal and a second clock signal to the charge pump module according to the first output voltage; the first clock signal and the second clock signal are used for controlling the charge pump module to work so that the charge pump module outputs a second output voltage according to the first output voltage.
2. The charge pump system of claim 1, wherein the divided voltage coefficient is positively correlated with the voltage of the load demand;
when the divided voltage coefficient increases, the first output voltage increases;
when the divided voltage coefficient decreases, the first output voltage decreases.
3. The charge pump system of claim 1, wherein the reference voltage is positively correlated with the voltage of the load demand;
when the reference voltage increases, the first output voltage increases;
when the reference voltage decreases, the first output voltage decreases.
4. The charge pump system of claim 1, further comprising a first selector and a second selector;
the output end of the operational amplifier is connected with the first input end of the first selector and the first input end of the second selector, the second input end of the first selector and the second input end of the second selector are used for being connected with a power supply, the control end of the first selector and the control end of the second selector are used for being connected with a controller, the output end of the first selector is connected with the voltage input end of the charge pump module, and the output end of the second selector is connected with the input end of the clock driving module;
the first selector is configured to receive a first control signal issued by the controller and output the first output voltage to the charge pump module based on the first control signal, when an output ripple required by the charge pump system is smaller than a first threshold; the second selector is used for receiving a second control signal issued by the controller and outputting the first output voltage to the clock driving module based on the second control signal.
5. The charge pump system of claim 4, wherein in the event that the high frequency ripple of the power supply is greater than the low frequency ripple of the power supply, the first selector is configured to receive a third control signal issued by the controller and output the first output voltage to the charge pump module based on the third control signal; the second selector is used for receiving a fourth control signal issued by the controller and outputting the power supply voltage of the power supply to the clock driving module based on the fourth control signal;
the clock driving module is used for outputting a third clock signal and a fourth clock signal to the charge pump module according to the power supply voltage of the power supply; the third clock signal and the fourth clock signal are used for controlling the charge pump module to work so that the charge pump module outputs a third output voltage according to the first output voltage.
6. The charge pump system of claim 4, wherein in the event that the high frequency ripple of the power supply is less than the low frequency ripple of the power supply, the first selector is configured to receive a fifth control signal issued by the controller and output a supply voltage of the power supply to the charge pump module based on the fifth control signal; the second selector is configured to receive a sixth control signal sent by the controller, and output the first output voltage to the clock driving module based on the sixth control signal;
The clock driving module is used for outputting a fifth clock signal and a sixth clock signal to the charge pump module according to the first output voltage; the fifth clock signal and the sixth clock signal are used for controlling the charge pump module to work, so that the charge pump module outputs a fourth output voltage according to the power supply voltage of the power supply.
7. The charge pump system of any of claims 1-6, wherein the charge pump module comprises an M-stage charge pump circuit, a first input of a 1 st stage charge pump circuit being a voltage input of the charge pump module, an output of an i-th stage charge pump circuit being connected to a first input of an i+1 th stage charge pump circuit, an output of the M-th stage charge pump circuit being a voltage output of the charge pump module; m is a positive integer greater than or equal to 2, i is a positive integer greater than or equal to 1 and less than M;
the M-stage charge pump circuits comprise at least one stage of charge pump circuits and other stages of charge pump circuits, wherein a second input end of each stage of charge pump circuit in the at least one stage of charge pump circuits is used as a first signal input end of the charge pump module, and a second input end of each stage of charge pump circuit in the other stages of charge pump circuits is used as a second signal input end of the charge pump module.
8. The charge pump system of claim 7, wherein the charge pump circuit comprises a switch unit and a capacitor unit, a first connection terminal of the switch unit is used as a first input terminal of the charge pump circuit, a second connection terminal of the switch unit is connected with a first connection terminal of the capacitor unit and then used as an output terminal of the charge pump circuit, and a second connection terminal of the capacitor unit is used as a second input terminal of the charge pump circuit;
when the first clock signal is at a high level and the second clock signal is at a low level, the capacitor unit in each of the at least one stage of charge pump circuits charges the capacitor unit in a next stage of charge pump circuit of each of the at least one stage of charge pump circuits; or when the first clock signal is at a low level and the second clock signal is at a high level, the capacitor unit in each of the other stages of charge pump circuits charges the capacitor unit in a charge pump circuit of a next stage of charge pump circuit of each of the other stages of charge pump circuits.
9. The charge pump system of any of claims 1-6, wherein the clock drive module comprises an oscillator and a clock buffer; the input end of the oscillator is used as the input end of the clock driving module, the output end of the oscillator is connected with the input end of the clock buffer, the first output end of the clock buffer is used as the first output end of the clock driving module, and the second output end of the clock buffer is used as the second output end of the clock driving module;
The oscillator is used for outputting an oscillation signal to the clock buffer according to the first output voltage;
the clock buffer is used for outputting the first clock signal and the second clock signal to the charge pump module according to the oscillation signal.
10. The charge pump system of claim 9, wherein a clock period of each of the first clock signal and the second clock signal is determined by at least one of a current demanded by the load, an energy conversion efficiency of the charge pump system, and an output ripple range of the charge pump system.
11. A power supply device, characterized in that it comprises a housing and a charge pump system according to any one of claims 1-10 arranged inside the housing.
12. A memory comprising an array of memory cells and a charge pump system according to any one of claims 1-10; the charge pump system supplies power to the memory cell array.
13. An electronic device comprising a power management chip and the charge pump system of any of claims 1-10 disposed on the power management chip.
CN202310819502.6A 2023-07-06 2023-07-06 Charge pump system, power supply device, memory and electronic equipment Active CN116545239B (en)

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