CN105162418B - A kind of oscillating circuit for eliminating comparator delay and mismatch - Google Patents
A kind of oscillating circuit for eliminating comparator delay and mismatch Download PDFInfo
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- CN105162418B CN105162418B CN201510626725.6A CN201510626725A CN105162418B CN 105162418 B CN105162418 B CN 105162418B CN 201510626725 A CN201510626725 A CN 201510626725A CN 105162418 B CN105162418 B CN 105162418B
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Abstract
The invention discloses a kind of oscillating circuits of elimination comparator delay and mismatch, which includes a continuous current source I, switch K, switch KB, double capacitive tank modules, the first comparison module, the second comparison module and a logic module LOGIC；The output end of first comparison module and the second comparison module is connected with logic module LOGIC；Double capacitive tank modules include two groups and connection and the identical square wave of structure generates unit, each square wave generates unit and increases a capacitance, a little switch, voltage control unit and some logic modules etc., and, cooperation considers the factors such as the charge injection in the reset of capacitance original state, the implementation method of voltage control unit, voltage-controlled performance requirement and various switches, delay and mismatch to comparison module can be significantly improved to get to frequency more to stablize and accurate clock signal clk amplitude and clock signal clk signal frequency.
Description
Technical field
The present invention relates to the oscillating circuits in integrated circuit fields more particularly to a kind of Analog Circuit Design, more specifically
It says, is related to a kind of oscillating circuit of elimination comparator delay and mismatch.
Background technology
The circuit that oscillating current can be generated is called oscillating circuit, is widely answered in electronic science and technology field
With in local oscillator, Medical Instruments and the measuring instrument in the carrier oscillator of transmitter, receiver in communication system
Signal source etc..There are many type of oscillator, divide by the waveform of signal, can be divided into sine-wave oscillator and non-sinusoidal waveform oscillation
Device.The waveform that sine-wave oscillator generates is in close proximity to sine wave or cosine wave, and frequency of oscillation is more stable；Non-sinusoidal waveform
The waveform that oscillator generates is non-sinusoidal impulse waveform, such as square wave, rectangular wave, sawtooth wave.
Referring to Fig. 1, Fig. 1 show double capacitive tank circuit structural schematic diagrams commonly used in the prior art.As shown,
The annular oscillation circuit generally includes 4 switches (two K switches and two KB switches), two capacitances C1 and C2, two comparisons
A circuit COMP and logic unit LOGIC.Wherein, switch K and switch KB is two opposite signals, they make 4 to open
Pass is divided into two groups, and two K switches are one group, and two KB switches are another set；It centainly disconnects for another group, that is, works as when one group of closure
When two K switches are opened, two KB switches are certain to be disconnected, conversely, when two KB switches are opened, two K switches centainly disconnect.
Assuming that when two K switches are opened, then continuous current source I charges to capacitance C1, on the top crown voltage V1 of capacitance C1
It rises, when voltage V1 is more than VREF, the output switching activity of two comparator COMP, K and KB signals change in logic unit LOGIC,
CLK signal generates one and rises (or decline) edge, voltage V1 by switch discharge to, while current source I starts to capacitance C2
Charging so recycles, just generates clock signal clk.
Referring to Fig. 2, Fig. 2 is voltage V1, V2 caused by double capacitive tank circuit structures in the prior art and clock letter
The waveform diagram of number CLK.As shown, when voltage V1 or voltage V2 still rises a period of time after reaching VREF, this is
Caused by due to the delay of comparator COMP and/or input terminal mismatch etc..
Specifically, for common comparator COMP, since the V-VREF postponed and mismatch generates is about
0.12V, if VREF=1.2V,：
1), the absolute value of frequency has ± 10% deviation.
2), in difference Corner V-VREF have ± 50% gap, can then introduce the variation of ± 5% frequency.
It will be apparent to those skilled in the art that if voltage V1 or voltage V2 still rises a period of time after reaching VREF, this
The frequency of output clock signal clk can be made to reduce.Meanwhile this section of delay time is unpredictable, by temperature and technique etc.
The influence of factor so that the output frequency of clock signal clk changes greatly, and here it is cause the frequency of Non-sinusoidal Oscillations device often
The not high reason of stability.
It is to reduce electricity accordingly, it is determined that being the error of device model or the error of back segment interconnection parasitic resistance capacitance extraction
The key and industry urgent problem of road phantom error.
Invention content
It is a primary object of the present invention to overcoming the deficiencies of existing technologies, a kind of elimination comparator delay and mismatch are provided
Oscillating circuit, the influence brought with mismatch by eliminating comparator delay, so as to get frequency more stablizes and accurate clock
Signal CLK amplitudes and clock signal clk signal frequency.
To reach above-mentioned purpose, technical scheme is as follows：
A kind of oscillating circuit for eliminating comparator delay and mismatch, the oscillating circuit include a continuous current source I, open
Close K, switch KB, double capacitive tank modules, the first comparison module, the second comparison module and a logic module LOGIC；It is described
The output end of first comparison module and the second comparison module is connected with the logic module LOGIC；Double capacitive tank modules
Unit is generated including two groups and connection and the identical square wave of structure, the first square wave generates unit and the second square wave generates unit difference
By the break-make of the switch K and switch KB control and the continuous current source I, when one group of closure, another group centainly disconnects；It is described
First square wave generates unit and respectively includes identical and connected with each other capacitance C1, the C2 branch of 6 switches, 2 capacitances and have
The first voltage control unit of normal voltage V-VREF；Wherein, 6 switches include 2 and are serially connected in the capacitance C1 respectively,
Switch K1 and K2 in C2 branches, by the output end VOUT phases of switch K1 and capacitance C1 contacts and the first voltage control unit
Even switch K3, switch K1 and capacitance C1 contacts are connected with the input terminal VIN of the first voltage control unit switch K4,
By switch K2 and capacitance C2 contacts and the input terminal VIN of the first voltage control unit switch K3 being connected and will switch
The switch K4 that K2 and capacitance C2 contacts are connected with the output end VOUT of the first voltage control unit；First comparison module
Input positive terminal and first square wave generate unit and the contact of switch K is connected, the input negative terminal of first comparison module
Access normal voltage V-VREF；Second square wave generates unit, and to respectively include 6 switches, 2 capacitances identical and mutually simultaneously
Capacitance C3, the C4 branch connect and the second voltage control unit with normal voltage V-VREF；Wherein, 6 switches include 2
It is a to be serially connected in the capacitance C3 respectively, switch K3 and K4 in C4 branches, by switch K3 and capacitance C3 contacts and second electricity
The switch K2 that presses the output end VOUT of control unit connected, will switch K3 and capacitance C3 contacts and the second voltage control unit
The connected switch K1 of input terminal VIN, by the input terminal VIN of switch K4 and capacitance C4 contacts and the second voltage control unit
Connected switch K2 and switch K4 and capacitance C4 contacts are connected with the output end VOUT of the second voltage control unit
Switch K1；The contact that the input positive terminal of second comparison module generates unit and switch KB with second square wave is connected, institute
State the input negative terminal access normal voltage V-VREF of the second comparison module；Wherein, the switch K and switch KB is two opposite
Signal, the continuous current source I can only charge simultaneously to circuit all the way；Four capacitance C1, C2, C3, C4 capacitances are equal, and work
When work starts, the top crown of four capacitances C1, C2, C3, C4 are reset to ground；During the work time, it opens for remaining other 12
Pass is divided into two groups, respectively by switch K and switch KB controls；Work as K, K1, K4 switch conductions, KB, K2 are described when K3 switches disconnect
Continuous current source I flows to the capacitance C1, and the top crown voltage V1 of the capacitance C1 is increased, and the top crown voltage V1 is added to
The first voltage control unit input terminal VIN, the first voltage control unit is by input voltage VIN and normal voltage V-
VREF subtracts each other, at this point, the capacitance C2 top crowns are then connected on the output end VOUT of the first voltage control unit；When described
When the top crown voltage V1 of capacitance C1 is increased to the first comparison module overturning, KB, K2, K3 switch conductions, K, K1, K4 switches
It disconnects, the continuous current source I charges to the capacitance C3, and the capacitance C1 top crowns then keep first comparison module to turn over
Input voltage V1 when turning, and V-VREF is passed to by the first voltage control unit top crown of the capacitance C2,
The top crown voltage V1 of the capacitance C1 is pulled down to V-VREF；At the same time, the top crown voltage V2 of the capacitance C3 is increased,
The top crown voltage V2 is added to the second voltage control unit input terminal VIN, and the second voltage control unit will be defeated
Enter voltage VIN and normal voltage V-VREF to subtract each other, at this point, the capacitance C4 top crowns are then connected on the second voltage control unit
Output end VOUT on；When the top crown voltage V2 of the capacitance C3 is increased to the second comparison module overturning, KB, K2,
K3 switches disconnect, K, K1, K4 switch conductions, and the continuous current source I again charges to the capacitance C1, the capacitance C3 top crowns
Input voltage V2 when second comparison module then being kept to overturn, and passed V-VREF by the second voltage control unit
The top crown of the capacitance C4 is passed, the top crown voltage V1 of the capacitance C3 is pulled down to V-VREF, into next cycle
Period.
Preferably, first and second voltage control unit is realized by amplifier, analog adder or switched-capacitor circuit.
Preferably, the logic module LOGIC includes the S/R latch and two d type flip flops；Described first compares mould
The output end of block and the second comparison module meets two input terminals R, S of the S/R latch respectively；Two of the S/R latch
Output end Q, QB are connected with the input terminal of described two d type flip flops respectively.
Preferably, the value of the voltage V1 and voltage V2 is equal.
Preferably, the ratio of the value of the voltage V1 and voltage V2 and normal voltage V-VREF are 20:1~5:1.
Preferably, the ratio of the value of the voltage V1 and voltage V2 and normal voltage V-VREF are 10:1.
Preferably, the value of the normal voltage V-VREF is 0.12V.
It can be seen from the above technical proposal that the oscillating circuit provided by the invention for eliminating comparator delay and mismatch is set
Meter, can (can be with by increasing by two capacitances, a little switch, two voltage control units on the circuit base of the prior art
With realizations such as amplifier, analog adder, switched-capacitor circuits) and some logic modules etc., also, coordinate and consider that capacitance is initial
The reset of state, the implementation method of voltage control unit, voltage-controlled performance requirement (for example, speed and driving capability etc.) and
The factors such as the charge injection in various switches, can significantly improve the delay to comparison module and mismatch.
Description of the drawings
Fig. 1 show double capacitive tank circuit structural schematic diagrams commonly used in the prior art
Fig. 2 is the waveform of voltage V1, V2 and clock signal clk caused by double capacitive tank circuit structures in the prior art
Schematic diagram
Fig. 3 is the circuit diagram for the waveform generation part that one embodiment of the invention eliminates comparator delay and mismatch
Fig. 4 show the complete oscillating circuit schematic diagram of a preferred embodiment that the present invention eliminates comparator delay and mismatch
Fig. 5 one embodiment of the invention eliminates one kind of comparator delay and the logic module LOGIC in mismatch oscillating circuit
Way of realization schematic diagram
K, KB, K1, K2 caused by oscillating circuits of the Fig. 6 for one embodiment of the invention elimination comparator delay with mismatch,
The waveform diagram of K3 and K4
Specific implementation mode
To keep present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is made into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, the general replacement known to those skilled in the art
Cover within the scope of the present invention.In the present specification and in detail in the claims, it should be understood that when an element is referred to as " even
Connect " to another element or when with another element " being connected ", it can be directly connected to, or intervening element may be present.
Fig. 3 and Fig. 4 are please referred to, Fig. 3 is that one embodiment of the invention eliminates comparator delay and the waveform of mismatch generates
Partial circuit diagram；Fig. 4 show present invention elimination comparator delay and a preferred embodiment of mismatch is completely vibrated
Circuit diagram.
As shown in figure 3, in an embodiment of the present invention, the oscillating circuit of elimination comparator delay and mismatch includes one
Continuous current source I, switch K, switch KB, double capacitive tank modules, the first comparison module, the second comparison module and a logic
Module LOGIC；The output end of first comparison module and the second comparison module is connected with logic module LOGIC.
Double capacitive tank modules include two groups and connection and the identical square wave of structure generates unit (i.e. the first square wave generates singly
Member and the second square wave generate unit), the first square wave generates unit and the second square wave generates unit respectively by switch K and switch KB controls
System and the break-make of continuous current source I, when one group of closure, another group centainly disconnects.
First square wave generates unit and respectively includes six switch, two capacitances identical and connected with each other capacitance C1, C2
Branch and first voltage control unit with normal voltage V-VREF.In general, the value of normal voltage V-VREF is 0.12V.
This six switches include two and are serially connected in the capacitance C1 respectively, switch K1 and K2 in C2 branches, will switch K1
The switch K3 that is connected with the output end VOUT of first voltage control unit with capacitance C1 contacts, by switch K1 and capacitance C1 contacts with
Connected the input terminal VIN of first voltage control unit switch K4, will switch K2 and capacitance C2 contacts and described first electric
Press the switch K3 and control switch K2 and capacitance C2 contacts with the first voltage that the input terminal VIN of control unit is connected
Switch K4 connected the output end VOUT of unit.
The contact that the input positive terminal of first comparison module generates unit and switch K with the first square wave is connected, and first compares mould
The input negative terminal access normal voltage V-VREF of block.
It also includes six identical and connected with each other capacitances of switch, two capacitances that second square wave, which generates unit respectively,
C3, C4 branch and second voltage control unit with normal voltage V-VREF；Wherein, this six switches include two and go here and there respectively
It is connected on switch K3 and K4 in capacitance C3, C4 branch, by the output of switch K3 and capacitance C3 contacts and second voltage control unit
Connected end VOUT switch K2, switch K3 and capacitance C3 contacts are opened with what the input terminal VIN of second voltage control unit was connected
K1 is closed, by switch K4 and capacitance C4 contacts and the input terminal VIN of the second voltage control unit switch K2 being connected and will be switched
The switch K1 that K4 and capacitance C4 contacts are connected with the output end VOUT of second voltage control unit.
The contact that the input positive terminal of second comparison module generates unit and switch KB with the second square wave is connected, second ratio
Compared with the input negative terminal access normal voltage V-VREF of module.
Note that switch K and switch KB receives is two opposite signals, that is to say, that continuous current source I is simultaneously
It can charge to capacitive branch all the way；The capacitance of four capacitances C1, C2, C3, C4 are equal, and when oscillating circuit work beginning, and four
A capacitance C1, C2, C3, the top crown of C4 are both needed to be reset to ground potential.During the work time, remaining other 12 switches are divided into
Two groups, respectively by switch K and switch KB controls.
Specifically, work as K, K1, K4 switch conductions, KB, K2, when K3 switches disconnect, continuous current source I flows to capacitance C1, electricity
The top crown voltage V1 for holding C1 is increased, and top crown voltage V1 is added to first voltage control unit input terminal VIN, first voltage
Control unit subtracts each other input voltage VIN and normal voltage V-VREF, at this point, capacitance C2 top crowns are then connected on first voltage control
On the output end VOUT of unit；When the top crown voltage V1 of capacitance C1 is increased to the overturning of the first comparison module, KB, K2, K3 are opened
Conducting, K, K1 are closed, K4 switches disconnect, and continuous current source I charges to capacitance C3, and capacitance C1 top crowns then keep the first comparison module
Input voltage V1 when overturning, and V-VREF is passed to by first voltage control unit the top crown of capacitance C2, capacitance C1
Top crown voltage V1 be pulled down to V-VREF；At the same time, the top crown voltage V2 of capacitance C3 is increased, and top crown voltage V2 adds
Enter to second voltage control unit input terminal VIN, second voltage control unit is by input voltage VIN and normal voltage V-VREF phases
Subtract, at this point, capacitance C4 top crowns are then connected on the output end VOUT of second voltage control unit；When the top crown of the capacitance C3
When voltage V2 is increased to the second comparison module overturning, KB, K2, K3 switches disconnect, K, K1, K4 switch conductions, continuous current
Source I again charges to capacitance C1, input voltage V2 when capacitance C3 top crowns then keep the second comparison module to overturn, and passes through second
V-VREF is passed to the top crown of capacitance C4 by voltage control unit, and the top crown voltage V1 of capacitance C3 is pulled down to V-VREF,
The oscillating curve of generation enters next cycle period again.
In an embodiment of the present invention, the value of voltage V1 and voltage V2 are typically equal, the value of voltage V1 and voltage V2
Ratio with normal voltage V-VREF can be 20:1~5:1, preferably, the value of voltage V1 and voltage V2 and normal voltage V-
The ratio of VREF is 10:1.
The value of normal voltage V-VREF be generally dependent on need to improve oscillating circuit frequency it is related, normal voltage V-VREF
Value be can be with 0.12V.In practical application, the reset, voltage control unit for considering capacitance original state can be coordinated
In implementation method, voltage-controlled performance requirement (for example, speed and driving capability etc.) and various switches charge injection etc. because
Element, so that it may to significantly improve delay and the mismatch to comparison module.
It please refers to 4, Fig. 4 and show that the present invention eliminates comparator delay and electricity is completely vibrated in a preferred embodiment of mismatch
Road schematic diagram.In an embodiment of the present invention, the first and second voltage control units can be by amplifier, analog adder or switch
The circuits such as capacitance are realized.
Referring to Fig. 5, one embodiment of the invention eliminates the logic module LOGIC in comparator delay and mismatch oscillating circuit
A kind of way of realization schematic diagram；As shown, logic module LOGIC includes S/R latch and two d type flip flops；First ratio
Meet two input terminals R, S of S/R latch respectively compared with the output end of module and the second comparison module；Two outputs of S/R latch
Q, QB is held to be connected respectively with the input terminal of two d type flip flops.
Referring to Fig. 6, K caused by oscillating circuits of the Fig. 6 for one embodiment of the invention elimination comparator delay with mismatch,
The waveform diagram of KB, K1, K2, K3 and K4.As shown, the output waveform of K, KB, K1, K2, K3 and K4 eliminate the need for comparing
Device postpones and the influence of mismatch.
Although the present invention disclosed with preferred embodiment it is as above, right many embodiments illustrate only for the purposes of explanation and
, it is not limited to the present invention, if those skilled in the art can make without departing from the spirit and scope of the present invention
Dry changes and retouches, and the protection domain advocated of the present invention should be subject to claims.
Claims (7)
1. a kind of oscillating circuit for eliminating comparator delay and mismatch, which is characterized in that the oscillating circuit includes a constant current
Current source I, switch K, switch KB, double capacitive tank modules, the first comparison module, the second comparison module and a logic module
LOGIC；The output end of first comparison module and the second comparison module is connected with the logic module LOGIC；
Double capacitive tank modules include two groups and connection and the identical square wave of structure generates unit, and the first square wave generates unit
Unit is generated respectively by the break-make of the switch K and switch KB control and the continuous current source I, the switch with the second square wave
K and switch KB, in one group of closure, another group centainly disconnects；
It includes six identical and connected with each other capacitance C1, C2 branches of switch, two capacitances that first square wave, which generates unit,
With the first voltage control unit with normal voltage V-VREF；Wherein, six switches include two and are serially connected in institute respectively
State switch K1 and K2 in capacitance C1, C2 branch, by the defeated of switch K1 and capacitance C1 contacts and the first voltage control unit
Connected outlet VOUT switch K3, by the input terminal VIN phases of switch K1 and capacitance C1 contacts and the first voltage control unit
Even switch K4, switch K2 and capacitance C2 contacts are connected with the input terminal VIN of the first voltage control unit switch K3,
And the switch K4 that switch K2 and capacitance C2 contacts are connected with the output end VOUT of the first voltage control unit；Described
The contact that the input positive terminal of one comparison module generates unit and switch K with first square wave is connected, first comparison module
Input negative terminal access normal voltage V-VREF；
It includes six identical and connected with each other capacitance C3, C4 branches of switch, two capacitances that second square wave, which generates unit,
With the second voltage control unit with normal voltage V-VREF；Wherein, six switches include two and are serially connected in institute respectively
State switch K3 and K4 in capacitance C3, C4 branch, by the defeated of switch K3 and capacitance C3 contacts and the second voltage control unit
Connected outlet VOUT switch K2, by the input terminal VIN phases of switch K3 and capacitance C3 contacts and the second voltage control unit
Switch K1 even, the switch K2 that switch K4 and capacitance C4 contacts are connected with the input terminal VIN of the second voltage control unit,
And the switch K1 that switch K4 and capacitance C4 contacts are connected with the output end VOUT of the second voltage control unit；Described
The contact that the input positive terminal of two comparison modules generates unit and switch KB with second square wave is connected, second comparison module
Input negative terminal access normal voltage V-VREF；
Wherein, the switch K and switch KB is two opposite signals, and the continuous current source I simultaneously only can be to circuit all the way
Charging；Four capacitance C1, C2, C3, C4 capacitances are equal, and when work beginning, the top crown of four capacitances C1, C2, C3, C4 are equal
It is reset to ground；During the work time, remaining other 12 switches are divided into two groups, respectively by switch K and switch KB controls；
Work as K, K1, K4 switch conductions, KB, K2, when K3 switches disconnect, the continuous current source I flows to the capacitance C1, the electricity
The top crown voltage V1 for holding C1 is increased, and the top crown voltage V1 is added to the first voltage control unit input terminal VIN, institute
It states first voltage control unit to subtract each other input voltage VIN and normal voltage V-VREF, at this point, the capacitance C2 top crowns then connect
On the output end VOUT of the first voltage control unit；
When the top crown voltage V1 of the capacitance C1 is increased to the first comparison module overturning, KB, K2, K3 switch conductions,
K, K1, K4 switch disconnect, and the continuous current source I charges to the capacitance C3, and the capacitance C1 top crowns then keep described the
Input voltage V1 when one comparison module is overturn, and V-VREF is passed to by the capacitance by the first voltage control unit
The top crown voltage V1 of the top crown of C2, the capacitance C1 is pulled down to V-VREF；At the same time, the top crown of the capacitance C3
Voltage V2 is increased, and the top crown voltage V2 is added to the second voltage control unit input terminal VIN, the second voltage control
Unit processed subtracts each other input voltage VIN and normal voltage V-VREF, at this point, the capacitance C4 top crowns are then connected on second electricity
On the output end VOUT for pressing control unit；
When the top crown voltage V2 of the capacitance C3 is increased to the second comparison module overturning, KB, K2, K3 switches disconnect,
K, K1, K4 switch conduction, the continuous current source I again charges to the capacitance C1, described in the capacitance C3 top crowns are then kept
Input voltage V2 when second comparison module is overturn, and V-VREF is passed to by the electricity by the second voltage control unit
Hold the top crown of C4, the top crown voltage V1 of the capacitance C3 is pulled down to V-VREF, into next cycle period；
Wherein, switch Kl, K2, K3, K4 included by the first voltage control unit and the second voltage control unit institute
Including switch Kl, K2, K3, K4 be same group of switch respectively.
2. the oscillating circuit according to claim 1 for eliminating comparator delay and mismatch, which is characterized in that first He
Second voltage control unit is realized by amplifier, analog adder or switched-capacitor circuit.
3. the oscillating circuit according to claim 1 for eliminating comparator delay and mismatch, which is characterized in that the logic mould
Block LOGIC includes S/R latch and two d type flip flops；The output end of first comparison module and the second comparison module connects respectively
Two input terminals R, S of the S/R latch；Two output ends Q, QB of the S/R latch respectively with described two d type flip flops
Input terminal be connected.
4. the oscillating circuit according to claim 1 for eliminating comparator delay and mismatch, which is characterized in that the voltage V1
It is equal with the value of voltage V2.
5. the oscillating circuit according to claim 4 for eliminating comparator delay and mismatch, which is characterized in that the voltage V1
It is 20 with the value of voltage V2 and the ratio of normal voltage V-VREF:1~5:1.
6. the oscillating circuit according to claim 5 for eliminating comparator delay and mismatch, which is characterized in that the voltage V1
It is 10 with the value of voltage V2 and the ratio of normal voltage V-VREF:1.
7. the oscillating circuit according to claim 1 for eliminating comparator delay and mismatch, which is characterized in that the standard electric
It is 0.12V to press the value of V-VREF.
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| CN201510626725.6A CN105162418B (en) | 2015-09-28 | 2015-09-28 | A kind of oscillating circuit for eliminating comparator delay and mismatch |
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| CN201510626725.6A CN105162418B (en) | 2015-09-28 | 2015-09-28 | A kind of oscillating circuit for eliminating comparator delay and mismatch |
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| CN105162418B true CN105162418B (en) | 2018-08-28 |
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| JPH06224705A (en) * | 1993-01-26 | 1994-08-12 | Matsushita Electric Works Ltd | Oscillating circuit |
| JP2004015447A (en) * | 2002-06-07 | 2004-01-15 | New Japan Radio Co Ltd | Oscillation circuit |
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| JPH06224705A (en) * | 1993-01-26 | 1994-08-12 | Matsushita Electric Works Ltd | Oscillating circuit |
| JP2004015447A (en) * | 2002-06-07 | 2004-01-15 | New Japan Radio Co Ltd | Oscillation circuit |
| CN101814907A (en) * | 2009-02-20 | 2010-08-25 | 凌通科技股份有限公司 | Signal delay circuit and oscillator using signal delay circuit |
| CN104143968A (en) * | 2014-07-30 | 2014-11-12 | 深圳市芯海科技有限公司 | On-chip oscillator circuit capable of eliminating control logic delay |
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