CN103066952B - Built-in oscillation circuit - Google Patents

Built-in oscillation circuit Download PDF

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CN103066952B
CN103066952B CN 201210592630 CN201210592630A CN103066952B CN 103066952 B CN103066952 B CN 103066952B CN 201210592630 CN201210592630 CN 201210592630 CN 201210592630 A CN201210592630 A CN 201210592630A CN 103066952 B CN103066952 B CN 103066952B
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tube
mirror
output
frequency
connected
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CN 201210592630
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CN103066952A (en )
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褚云飞
蔡康康
胡铁刚
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杭州士兰微电子股份有限公司
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Abstract

本发明提供一种内置振荡电路,本发明所述内置振荡电路采用负反馈闭环路形式,利用频率-电压转化方式,使内置振荡电路能够在芯片中全部集成,省略了需要外部额外设置的晶振,节约了工艺成本,并且通过将环形振荡器产生的振荡频率转化为反馈电压,并与参考电压进行比较,然后将比较结果反馈到环形振荡器的控制端,改变环形振荡器的频率,从而通过对输出频率的偏差进行补偿,从而使环路稳定输出低温漂的工作频率,产生高精度的输出频率。 The present invention provides a built-in oscillation circuit, the present invention is a built-in oscillation circuit using negative feedback in the form of a closed loop, with a frequency - voltage conversion mode, so that the built-in oscillation circuit can be fully integrated in a chip, the need for external crystal omitted additionally provided, processing savings, and the oscillation frequency of the ring oscillator is generated by converting the feedback voltage, and compared with a reference voltage and the comparison result is fed back to the control terminal of the ring oscillator to change the frequency of the ring oscillator, such that by variations in the output frequency is compensated so that the temperature drift of the output of the loop stable operating frequency, to produce a highly accurate output frequency.

Description

内置振荡电路 Built-in oscillation circuit

技术领域 FIELD

[0001] 本发明涉及振荡电路设备,尤其涉及一种内置振荡电路。 [0001] The present invention relates to an oscillation circuit device, particularly to a built-in oscillation circuit.

背景技术 Background technique

[0002] 科学技术的日新月异,使得各种设备的发展趋向低功耗,面积小以及低成本,精准的时钟发生电路也趋向于全片上集成,高精度,高频率的方向发展。 Changing [0002] of science and technology, such devices tend to develop various low power, low cost and small size, precise direction tends clock generation circuit are integrated on the entire film, high-precision, high-frequency development. 振荡器电路通常用于给各种集成电路芯片提供时钟信号。 Oscillator circuits are commonly used for various integrated circuit chip provides a clock signal. 一般给各种电路芯片提供时钟信号的振荡器电路有以下几种: Generally provide a clock signal to various circuit chip oscillator circuit are the following:

[0003] -种是基于环形振荡器的产生电路。 [0003] - generating species is based ring oscillator circuit. 环形振荡器产生电路使用较为广泛,但是在CMOS工艺中,由于存在温度、工艺和电源电压的不稳定性,使得所述片内集成时钟电路的输出频率稳定性较差。 A ring oscillator generating circuit more widely used, but in a CMOS process, the instability due to temperature, process and supply voltage, so that said integrated circuit chip clock output frequency stability is poor.

[0004] 再一种是RC松弛(Relaxation)振荡器,由于其频率精度较高,目前的发展较为迅速,但由于RC松弛振荡器的工作频率较低,因此不适合较高频率的时钟信号应用。 [0004] Yet another is an RC relaxation (Relaxation) oscillator frequency due to its higher precision, the more rapid development of the current, because of the low RC relaxation oscillator frequency, the clock signal is not suitable for higher frequency applications .

[0005] 另一种,也是较为常见的是时钟信号是采用石英晶体(Crystal)振荡器电作为时钟基准。 [0005] Another, more common is the use of a clock signal (the Crystal) quartz crystal oscillator circuit as a reference clock.

[0006] 目前对于消费类电子产品,比如27/49M,315/433M频段的射频发射系统,作为产生时钟基准的振荡器电路一般采用的都是第三种结构,图1为现有技术中时钟信号产生电路的结构示意图,如图1所示,晶振通过振荡器产生信号,并通过PLL/DLL锁定来获得时钟信号。 [0006] At present, for consumer electronics, such as 27 / 49M, 315 / 433M-band radio frequency transmission system, a reference oscillator circuit generates a clock are generally used third configuration, FIG. 1 is a prior art clock schematic structural diagram of signal generating circuit shown in FIG, 1 is generated by the crystal oscillator signal by PLL / DLL locked clock signal is obtained. 在芯片内部(即片上)需要用锁相环(PLL)或延时锁相环(DLL)来获得合适的时钟信号。 Within the chip (i.e., on-chip) need to use a phase locked loop (PLL) or a delay locked loop (DLL) to obtain the appropriate clock signal. 这种振荡器电路能实现很高的精度(1~lOOppm),但是这种方案需要额外增加的外部晶振,不仅极大地提高了产品的成本,且需要占用较大的芯片面积和功耗,并降低了整个芯片的竞争能力,因此影响在一些对成本比较敏感的消费类产品中的应用,例如玩具遥控产品、无线控制产品及红外遥控产品等。 This oscillator circuit can be realized with high accuracy (1 ~ lOOppm), but this solution requires the additional external crystal, not only greatly increases the cost of the product, and the need to occupy a large chip area and power consumption, and reducing the competitiveness of the entire chip, used in some of the cost-sensitive consumer products therefore impacts, such as toys, remote control, wireless infrared remote control products and products.

发明内容 SUMMARY

[0007] 本发明的目的是解决现有技术的不足,提供一种新型的内置振荡电路,解决由于工艺、电源电压和温度的变化产生的频率偏移,并且成本低廉,频率范围更大的的内置振荡电路。 [0007] The object of the present invention is to solve the deficiencies of the prior art, to provide a novel built-in oscillation circuit, due to variations in the process to resolve the frequency offset, supply voltage and temperature generated, and cost, a greater frequency range built-in oscillation circuit.

[0008] 为解决上述问题,本发明提供一种内置振荡电路,包括基本电流产生电路、环形振荡器、频率-电压转化电路以及差分放大电路; [0008] In order to solve the above problems, the present invention provides a built-in oscillation circuit, comprising a base current generating circuit, a ring oscillator, the frequency - voltage conversion circuit and a differential amplifier circuit;

[0009] 所述基本电流产生电路包括第一运算放大器、第一放大管、可修调电阻和镜像电路,所述第一运算放大器接收一参考电压,经所述可修调电阻修调后由第一放大管输出一中间电流,所述中间电流经所述镜像电路输出参考电流; [0009] The base current generating circuit includes a first operational amplifier, a first amplifier tube, can trim resistance and mirror circuit, the first operational amplifier receives a reference voltage via said resistor trimming after the trim a first intermediate output amplifier tube current, the output intermediate current through the reference current mirror circuit;

[0010] 所述环形振荡器产生频率信号; [0010] The ring oscillator generates a frequency signal;

[0011] 所述频率-电压转化电路包括开关管模块、充放电容和输出电容,所述开关管模块接收所述参考电流和频率信号,并在所述频率信号的控制下,进行使所述参考电流对所述充放电容进行充电、以及在充放电容和输出电容之间进行电荷重新分配和对所述充放电容进行放电的过程,以使所述输出电容输出反馈电压; [0011] The frequency - voltage conversion circuit comprises a switch module, and output capacitors charge and discharge, receiving the reference frequency signal and a tube current of the switching module, and under the control of the frequency signal, for the a reference current to the charge-discharge capacity to charge and discharge electric charge between the charge redistribution and output capacitors and the charge-discharge process of discharging the capacitor, the output capacitor so that the output voltage feedback;

[0012] 所述差分放大电路比较所述反馈电压和参考电压并产生控制电压,所述控制电压对所述环形振荡器的频率信号进行反馈校正,直至频率信号稳定输出。 [0012] The differential amplifying circuit compares the feedback voltage and a reference voltage and generates a control voltage, the control voltage of the frequency signal of the ring oscillator feedback correction signal until a stable output frequency.

[0013] 进一步的,所述环形振荡器的频率信号稳定输出时,所述频率信号的值与修调电阻的电阻值和充放电容的电容值有关。 [0013] Further, when the frequency signal of the ring oscillator is stable output, the frequency and the resistance value of the trimming resistor and capacitance value of the charge signal discharge capacity concerned.

[0014] 进一步的,所述内置振荡器的输出频率为: [0014] Further, the output frequency of the oscillator is:

[0015] [0015]

Figure CN103066952BD00091

[0016] 其中,fout为所述环形振荡器的输出频率,Cc为所述充放电容的电容值,(Rp+Rn) 为所述可修调电阻的电阻值,K为比例系数。 [0016] wherein, fout is the output frequency of the ring oscillator, Cc is the capacitance value of the charge and the discharge capacity, (Rp + Rn) of said trim resistance of the resistor, K is a proportionality factor.

[0017] 进一步的,在所述基本电流产生电路中,所述第一运算放大器的两输入端分别接所述参考电压和第一放大管的第一连接端、输出端接所述第一放大管的控制端;所述可修调电阻一端接地、另一端接所述第一放大管的第一连接端,所述镜像电路的输入端接所述第一放大管的第二连接端、输出端输出所述参考电流。 [0017] Further, in the base current generating circuit, two input terminals of said first operational amplifier are respectively connected to the reference voltage and a first terminal of the first amplifier tube is connected, the first amplification output end control end of the tube; a second connecting end of said trimming resistors is grounded at one end, a first end connected to the other end of the first amplifier tube, said input terminal of said mirror circuit of the first amplifier tube, an output the output end of the reference current.

[0018] 进一步的,所述镜像电路包括第一镜像输出管,所述第一镜像输出管的控制端接所述第一放大管的控制端、所述第一镜像输出管的第一连接端输出所述参考电流、所述第一镜像输出管的第二连接端接所述电源电压。 [0018] Further, the mirror image output circuit comprises a first tube, the first mirror control terminal of the control terminal of the first outlet tube amplifier tube, connected to a first output terminal of the first mirror tube output of the reference current, a second outlet tube connected to the first mirror termination of the supply voltage.

[0019] 进一步的,所述镜像电路包括第一镜像输入管、第二镜像输入管、第一镜像输出管和第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、所述第一镜像输入管的第二连接端接一电源电压,所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,所述第一镜像输出管的控制端接所述第一镜像输入端的控制端、所述第一镜像输出管的第一连接端接所述第二镜像输出管的第二连接端,所述第一镜像输出管的第二连接端接所述电源电压,所述第二镜像输出管的控制端接所述第二镜像输入管的控制端,所述第二镜像输出管的第一连接端输出所述参考电流、所述第二镜像输出管的第二连接端与一第一镜像输出管的第一连接端连接。 [0019] Further, the input mirror circuit comprises a first mirror transistor, the second mirror inlet tube, outlet tube and the second mirror image of the first output transistor, the first image input control terminal of the first tube amplifying a second connector connecting a second end of the tube, a second connection terminal connected to a first end of the first mirror of the second mirror input tube inlet tube, the first tube end mirror input a supply voltage , a control terminal connected to a second input terminal of the second mirror connected to a second pipe end of the first amplifier tube, the control terminal of the first mirror of the first mirror outlet tube input end, said first a first control terminal connected to a second end connected to the second outlet tube a mirror image of the outlet tube, connected to a second end of said power source voltage to the first mirror output tube, said second tube output mirror terminating the control terminal of the second mirror inlet tube, connecting a first end of the second tube output mirror the reference current output, connected to a second end of the second outlet tube with a mirror image of the first outlet tube a first connector terminal.

[0020] 进一步的,所述镜像电路为多路可修调镜像电路,所述可修调电阻对所述参考电流实现低位频率偏差调节,所述多路可修调镜像电路实现高位低位频率选择以及所述参考电流实现高位频率偏差调节。 [0020] Further, the mirror circuit is a multiple, trimming mirror circuit, said trimming resistor of the reference current is adjusted to achieve the low frequency deviation, the trimming can be multiplexed to achieve high low frequency mirror circuit selection and the reference current to achieve high frequency deviation adjustment.

[0021 ] 进一步的,所述可修调镜像电路为共源共栅电流镜结构。 [0021] Further, the current mirror circuit can trim mirror cascode structure.

[0022] 进一步的,所述多路可修调镜像电路包括第一镜像输入管、第二镜像输入管、多个第一镜像输出管和多个第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、 所述第一镜像输入管的第二连接端接一电源电压,所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,每一所述第一镜像输出管的控制端均接所述第一镜像输入管的控制端、每一所述第一镜像输出管的第二连接端接所述电源电压,每一所述第二镜像输出管的控制端均接所述第二镜像输入管的控制端,所述第二镜像输出管的相连后输出所述参考电流,每一所述第二镜像输出管的第二连接端与一第一镜像输出管的第一连接端连接。 [0022] Further, the multiplexer may trimming mirror circuit includes a first input mirror tube, a second tube input image, a plurality of first mirror and a plurality of outlet tube outlet tube second mirror, the first mirror input control terminal of the first amplifying a second tube end of the tube is connected, a second connection terminal connected to a first end of the first mirror of the second mirror inlet tube of the inlet tube, the inlet tube first mirror a second end connected to a supply voltage, a second end connected to said input of said second mirror amplifying a second tube connected to a first end of the tube, each of said first mirror control terminal are connected to the outlet tube end of said second supply voltage terminal connected to a control input of said first mirror tube, each of said first mirror outlet tube, said second mirror control terminal of each output tube are connected to the second input mirror control end of the tube, the tube is connected to the output of the second output mirror the reference current, a second end of each of the second connecting pipe connected to the mirror output terminal connected to a first output a first mirror tube.

[0023] 进一步的,所述内置振荡电路包括M个第一镜像输出管,所述基本电流产生电路接收一多位控制信号,所述多位控制信号包括频率选择位、镜像电路调节位和电阻调节位, 所述频率选择位控制N个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围选择,所述镜像电路调节位控制L个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围内粗调,所述电阻调节位控制所述可修调电阻的电阻值以实现频率范围内精调,其中,N、L及M均为正整数,所述N个第一镜像输出管和L个第一镜像输出管均为不同的第一镜像输出管,且N+L=M。 [0023] Further, the built-in oscillation circuit comprises M first mirror output transistor, the base current generating circuit receives a multi-bit control signal, the multi-bit frequency selection control signal comprises a bit, and bit adjustment mirror circuit resistance adjusting the position, the frequency selection control bits N ratio of said first mirror output value of the first tube to achieve a mirror image tube input frequency range selected, the mirror control circuit adjusts the L-bit output of the first mirror scale value input tube and the first mirror tube to achieve coarse frequency range, the resistance adjusting a resistance value of said control bit trimming resistors to achieve fine tuning in the frequency range, where, N, L and M are positive integers, the N L first mirror and a first outlet tube outlet tube are different from the mirror image of the first outlet tube, and N + L = M.

[0024] 进一步的,所述频率-电压转化电路还包括脉冲信号产生电路和寄生电容消除电路,所述脉冲信号产生电路根据所述频率信号产生多个控制开关模块的脉冲信号,所述寄生消除电路包括第一寄生消除电路和第二寄生消除电路,所述充放电容包括第一充放电容和第二充放电容,所述开关管模块包括第一开关管、第一充电管、第一放电管、第二开关管、 第二充电管、第二放电管、第一防串扰管和第二防串扰管; [0024] Further, the frequency - voltage conversion circuit further comprises a pulse signal generating circuit and parasitic capacitance cancellation circuit, the pulse signal generation circuit generates a plurality of pulse signals to control switching module based on the frequency signal, eliminating the parasitic elimination circuit comprises a first circuit and second parasitic parasitic cancellation circuit, the charge and discharge capacitor comprises a first capacitor and a second charge and discharge capacitor charging and discharging, the switch module comprises a first switching transistor, a first charging pipe, a first a discharge tube, a second switch, a second charging pipe, a second discharge tube, the first tube and the second cross-talk preventing crosstalk prevention tube;

[0025] 所述第一开关管的控制端接所述频率信号、第一连接端接所述参考电流、第二连接端接第一节点,所述第二开关管的控制端接所述频率信号的反相信号、第一连接端接所述参考电流、第二连接端接第二节点, [0025] The control terminal of the first frequency signal switch, a first end connected to said reference current, a second end connected to a first node, a control terminal of the second switch frequency the inverted signal, a first end connected to said reference current, a second end connected to the second node,

[0026] 所述第一充放电容一端接所述第一节点、另一端接地,所述第二充放电容一端接所述第二节点、另一端接地, [0026] The charge and discharge said first capacitor one end of the first node, the other end, said second end of said charging and discharging a capacitive node, the other end grounded,

[0027] 所述第一充电管的控制端接脉冲信号,两连接端分别接第一节点和输出电容之间,所述第二充电管的控制端接脉冲信号,两连接端分别接第二节点和输出电容之间,所述第一放电管的控制端接脉冲信号,两连接端分别接地和第一节点,所述第二放电管的控制端接脉冲信号,两连接端分别接地和第二节点, [0027] The pulse signal of the first control terminal of the charging tube, the capacitance between the first node and the output terminals are connected to two connections, the control terminal of the second charge pulse tube, two second connection terminals respectively connected between the node and the output capacitor, the discharge control terminal of the first pulse signal, and two ground terminals are connected to a first node, a control terminal of the second discharge pulse signal, and two ground terminals are connected to the first second node,

[0028] 所述第一寄生电容消除电路输入端接所述脉冲信号、输出端接所述第一节点,所述第二寄生消除电路输入端接所述脉冲信号、输出端接所述第二节点; [0028] The first parasitic capacitance cancellation circuit the pulse signal input end, an output end of said first node, said second input terminal of the circuit to eliminate the parasitic pulse signal, the second output end node;

[0029] 所述第一防串扰管的控制端接脉冲信号、两连接端连接于所述第一充电管和输出电容之间,所述第二防串扰管的控制端接脉冲信号、两连接端连接于第二充电管和输出电容之间。 [0029] The control terminal of the first pulse signal crosstalk prevention pipe, connected to the two connection end between the first tube and the charging output capacitor, the control terminal of the second pulse signal crosstalk prevention pipe, connected to two between the second terminal is connected to the output capacitor and the charging tube.

[0030] 进一步的,所述开关模块还包括第三放电管和第四放电管,所述第三放电管的控制端接脉冲信号、两连接端接所述第一充放电容和地之间,所述第四放电管的控制端接脉冲信号、两连接端接所述第二充放电容之间。 [0030] Further, the switching module further comprises a third and a fourth discharge tube discharge, the discharge control terminal of the third pulse signal, a first end of said two connecting between the capacitor and the charge-discharge said fourth discharge control terminal of the pulse signals, the two second connection end between the capacitive charge and discharge.

[0031] 进一步的,所述第一开关管、第一充电管、第一放电管、第二开关管、第二充电管、 第二放电管、第一防串扰管、第二防串扰管、第三放电管和第四放电管接收不同的脉冲信号,所述第一开关管、第一充电管、第一放电管、第二开关管、第二充电管、第二放电管、第一防串扰管、第二防串扰管、第三放电管和第四放电管均为MOS管。 [0031] Further, the first switch, a first charging pipe, a first discharge tube, a second switch, a second charging pipe, a second discharge tube, the first crosstalk prevention tube, a second tube preventing crosstalk, the third and fourth discharge pulse discharge different received signals, the first switch, a first charging pipe, a first discharge tube, a second switch, a second charging pipe, a second discharge tube, the first anti- crosstalk tube, the second tube preventing crosstalk, the third and fourth discharge are discharge MOS transistor.

[0032] 进一步的,所述第一寄生消除电路和所述第二寄生消除电路的结构相同。 [0032] Further, said first and said second cancellation circuit parasitic eliminate parasitic same circuit configuration.

[0033] 进一步的,所述第一寄生消除电路具有第三节点,所述第三节点的寄生电容与所述第一节点的寄生电容相等。 [0033] Further, the cancellation circuit having a first parasitic third node, a parasitic capacitance and a parasitic capacitance equal to the first node of the third node. 所述第一寄生消除电路包括第i^一MOS管至第十七MOS管, 所述第十一MOS管的源极和栅极相接、漏极接所述第三节点,所述第十三MOS管的栅极接脉冲信号、漏极接所述第三节点、源极接所述第十二MOS管的源极,所述第十二MOS管的栅极接脉冲信号、源极和漏极相接并接所述参考电压,所述第十四MOS管和第十五MOS管的漏极均接所述第三节点、栅极和源极均接地,所述第十六M0S管的漏极接所述第三节点、栅极接脉冲信号、源极接所述第十七M0S管的源极,所述第十七M0S管的栅极接所述脉冲信号、源极和漏极相接并接所述第二节点。 The first parasitic cancellation circuit includes a first MOS transistor to i ^ a seventeenth MOS transistor, the source and gate contact, a drain connected to said third node, said eleventh MOS transistor, said tenth a gate connected to the pulse signals of the three MOS transistor, a drain connected to the third node, a source connected to the source of the twelfth MOS transistor, a gate connected said twelfth MOS transistor a pulse signal, a source, and and a drain contact connected to the reference voltage, the drain of said fourteenth MOS transistor and a fifteenth MOS transistor are connected to the third node, a source grounded and a gate, said sixteenth tube M0S a drain connected to the third node, a gate connected to a pulse signal, a source connected to the source of the seventeenth M0S tube, the tube M0S seventeenth gate connected to the pulse signal, a source and drain and contact electrode connected to the second node.

[0034] 进一步的,在所述频率-电压转化电路中,所述第二寄生消除电路具有第四节点, 所述第四节点的寄生电容与所述第二节点的寄生电容相等。 [0034] Further, in the frequency - voltage conversion circuit, the cancellation circuit having a second parasitic fourth node, a parasitic capacitance and a parasitic capacitance equal to said second node of said fourth node. 所述第二寄生消除电路包括第十八M0S管至第二十四M0S管,所述第十八M0S管的源极和栅极相接、漏极接所述第四节点,所述第二十M0S管的栅极接脉冲信号、漏极接所述第四节点、源极接所述第十九M0S 管的源极,所述第十九M0S管的栅极接脉冲信号、源极和漏极相接并接所述参考电压,所述第二十一M0S管和第二十二M0S管的漏极均接所述第四节点、栅极和源极均接地,所述第二十三M0S管的漏极接所述第四节点、栅极接脉冲信号、源极接所述第二十四M0S管的源极,所述第二十四M0S管的栅极接所述脉冲信号、源极和漏极相接并接所述第二节点。 The second cancellation circuit comprises a parasitic eighteenth through twenty-fourth tube M0S M0S tube, the tube M0S eighteenth source gate contact and a drain connected to the fourth node, said second the gate pulse signal connection ten M0S tube, a drain connected to the fourth node, a source connected to the tube M0S nineteenth source, a gate connected to said pulse signal nineteenth M0S tube, and a source and a drain contact connected to the reference voltage, the twenty-first and twenty-second M0S drain pipes are connected to pipe M0S the fourth node, the gate and source grounded, the twentieth a gate connected to said pulse signal having a drain connected to the fourth node M0S three tubes, connected to the gate pulse signal, a source connected to the twenty-fourth tube M0S the source of the twenty-fourth tube M0S , source and drain contact and said second contact point.

[0035] 进一步的,所述频率-电压转化电路还包括脉冲信号产生电路,所述脉冲信号产生电路根据所述频率信号产生多个控制开关模块的脉冲信号,所述开关管模块包括第一开关管、第一充电管、第一放电管和第一防串扰管; [0035] Further, the frequency - voltage conversion circuit further comprises a pulse signal generating circuit, the pulse signal generation circuit generates a plurality of pulse signals to control switching module based on the frequency signal, said switch comprising a first switching module pipe, a first charging pipe, a first discharge tube and the first anti-crosstalk;

[0036] 所述第一开关管的控制端接所述频率信号、第一连接端接所述参考电流、第二连接端接第一节点,所述充放电容一端接所述第一节点、另一端接地,所述第一充电管的控制端接脉冲信号,两连接端分别接第一节点和输出电容之间,所述第一放电管的控制端接脉冲信号,两连接端分别接地和第一节点,所述第一防串扰管的控制端接脉冲信号、两连接端连接于所述第一充电管和输出电容之间。 [0036] The control terminal of the first frequency signal switch, a first end connected to said reference current, a second end connected to a first node, one end of the capacitor charge and discharge the first node, other end, the pulse signal of the first control terminal of the charging tube, the capacitance between the first node and an output connected to two ends respectively connected, the control terminal of the first discharge pulse signal, and two ground terminals are connected a first node, a control terminal of the first pulse signal crosstalk prevention pipe, connected to the two ends connected between the first output capacitor and the charging tube.

[0037] 进一步的,所述开关模块还包括第三放电管,所述第三放电管的控制端接脉冲信号、两连接端接所述充放电容之间以对所述充电电容进行进一步放电。 [0037] Further, the switching module further comprises a third discharge tube, the discharge control terminal of the third pulse signal, said two end connected to the charge and discharge of said charging capacitor is further discharged between the capacitive .

[0038] 进一步的,所述第一开关管、第一充电管、第一放电管、第一防串扰管和第三放电管接收不同的脉冲信号,所述第一开关管、第一充电管、第一放电管、第一防串扰管和第三放电管均为M0S管。 [0038] Further, the first switch, a first charging pipe, a first discharge tube, the first tube and the crosstalk prevention receive different third discharge pulse signal, the first switch, a first charging pipe a first discharge tube, the first tube and the third anti-crosstalk are M0S discharge tube.

[0039] 进一步的,所述内置振荡电路还包括多倍分频器,所述多倍分频器设置于所述环形振荡器和频率-电压转化电路之间,所述多倍分频器对所述频率信号进行分频后,输出至所述频率-电压转化电路,以使所述频率-电压转化电路稳定工作。 [0039] Further, the built-in oscillation circuit further comprises a multiple of a frequency divider, a multiple frequency divider disposed in said ring oscillator and a frequency - voltage conversion circuit between the multiple frequency divider after dividing the frequency of the signal output to the frequency - voltage conversion circuit such that said frequency - voltage conversion circuit stability.

[0040] 进一步的,当所述频率信号稳定输出时,所述频率信号为: [0040] Further, when the stable output frequency signal, the frequency signal:

[0041] [0041]

Figure CN103066952BD00111

冲,M为所述多倍分频器的分频倍数,fout为所述内置振荡器的输出频率,Cc为第一充放电容的电容值,(Rp+Rn)为基本电流产生电路的可修调电阻的电阻值,K为比例系数。 Chong, M being a multiple of the frequency divider multiple frequency, fout is the output frequency of the internal oscillator, Cc is the capacitance of the first charge and discharge capacity, (Rp + Rn) of the current generation circuit can be substantially trim resistance of the resistor, K is a proportionality factor.

[0042] 进一步的,所述多倍分频器包括多个级联的两倍分频器。 [0042] Further, the multiple double frequency divider comprises a plurality of cascaded frequency dividers.

[0043] 进一步的,所述差分放大电路包括第二运算放大器、电阻和电容,所述第二运算放大器的一输入端分别接所述参考电压、另一输入端通过所述电阻接所述反馈电压之间、输出端接所述环形振荡器,所述电容一端连接于所述第一运算放大器和所述电阻之间,另一端连接于所述第一运算放大器和所述环形振荡器之间。 [0043] Further, the differential amplifying circuit comprises a second operational amplifier, a resistor and a capacitor, an input terminal of said second operational amplifier are respectively connected to the reference voltage, the other input terminal connected through the resistor of the feedback voltage between the output end of said ring oscillator, said capacitor is connected between one end of said first operational amplifier and the resistor, and the other end connected between the first operational amplifier and the ring oscillator .

[0044] 进一步的,所述内置振荡电路设置于频率范围在27MHZ~49MHZ的玩具遥控设备。 [0044] Further, the built-in oscillation circuit provided in the frequency range of the remote control device toys in 27MHZ ~ 49MHZ.

[0045] 进一步的,频率范围315MHz或433MHZ的无线控制设备。 [0045] Further, the frequency range of 315MHz or 433MHZ wireless control device.

[0046] 进一步的,频率范围在38KHz的红外遥控设备中。 [0046] Further, an infrared remote control device in a frequency range of 38KHz.

[0047] 综上所述,本发明所述内置振荡电路采用负反馈闭环路形式,利用频率-电压转化方式,使内置振荡电路能够在芯片中全部集成,省略了需要外部额外设置的晶振,节约了工艺成本,并且通过将环形振荡器产生的振荡频率转化为反馈电压,并与参考电压进行比较,然后将比较结果反馈到环形振荡器的控制端,改变环形振荡器的频率,从而通过对输出频率的偏差进行补偿,减少了参考电流接输入点的寄生电容对于频率-电压转化电路的影响,从而使环路稳定输出低温漂的工作频率,并提高了振荡器的频率精度。 [0047] In summary, the present invention is a built-in oscillation circuit using negative feedback in the form of a closed loop, with a frequency - voltage conversion mode, so that the built-in oscillation circuit can be fully integrated in a chip, the need for external crystal omitted additionally provided, saving process costs, and the oscillation frequency of the ring oscillator is generated by converting the feedback voltage, and compared with a reference voltage and the comparison result is fed back to the control terminal of the ring oscillator to change the frequency of the ring oscillator, so that by the output compensate the frequency deviation, the reference current is reduced parasitic capacitance to the input point of the frequency - voltage conversion circuit Effect of the loop so that a stable output temperature drift of the operating frequency, and improves the frequency accuracy of the oscillator.

[0048] 进一步的,通过在所述频率-电压转化电路通过引入寄生消除电路,避免了因为所述频率-电压转化电路在第一节点和第二节点处引入的引入MOS管寄生电容,故在充放电的过程中,降低了对温度的敏感性,避免了寄生电容对内置振荡电路的影响,提高了频率-电压转化电路的温度特性,进而改善了整个系统的温度特性。 [0048] Further, by the frequency - voltage conversion circuit by introducing parasitic cancellation circuit, is avoided because of the frequency - voltage conversion circuit is introduced is introduced at a first point and a second node capacitance parasitic MOS transistor, so that the during charging and discharging, less sensitive to temperature, to avoid the influence of parasitic capacitance of the built-in oscillation circuit, increases the frequency - temperature characteristic of the voltage conversion circuit, thereby improving the temperature characteristics of the entire system.

[0049] 进一步的,所述内置振荡电路中,所述基本电流产生电路通过可修调电阻的低位细调和多路可修调镜像电路的高位控制以及高位低位频率选择,从而能够通过修调位修正方法对输出频率的工艺偏差,达到〇. 1 %的频率修调精度,并且能够覆盖整个修调范围,没有断节。 [0049] Further, the built-in oscillation circuit, the base current generating circuit via a low resistance trimming fine and multiplexer control can override the upper mirror circuit and the high-low frequency selection is possible by trimming bits a method for correcting the frequency deviation of the output of the process, to achieve square. 1% accuracy frequency trim, trim and can cover the entire range, without breaking section.

[0050] 所述内置振荡电路不仅在工艺,温度偏差和电源电压偏差的情况下有较高的稳定性,输出一个稳定的时钟信号,而且其输出频率范围广。 [0050] The built-in oscillation circuit not only a higher stability, a stable clock signal output in the case of process, temperature variation and supply voltage variation, and its wide range of output frequencies.

附图说明 BRIEF DESCRIPTION

[0051] 图1为现有技术中时钟信号产生电路的结构示意图。 [0051] FIG. 1 is a schematic structure of a circuit generating a clock signal of the prior art.

[0052] 图2为本发明一实施例中内置振荡电路的示意图。 [0052] FIG. 2 is a schematic embodiment of a built-in oscillation circuit embodiment of the present invention.

[0053] 图3为本发明另一实施例中内置振荡电路的示意图。 [0053] FIG. 3 is a schematic diagram of the built-in oscillation circuit according to another embodiment of the present invention.

[0054] 图4. 1~图4. 3为本发明一实施例中内置振荡电路中基本电流产生电路的示意图。 [0054] FIG. 4.1 ~ 4.3 schematic diagram of FIG built-in oscillation circuit of a base current generating circuit embodiment of the invention.

[0055] 图5. 1~图5. 3为本发明几个实施例中内置振荡电路中频率-电压转化电路的示意图。 A schematic diagram of a voltage conversion circuit - [0055] FIG. 5.1 ~ 5.3 of the present embodiment FIG built several frequency oscillating circuit embodiment of the invention.

[0056] 图6为本发明几个实施例中频率-电压转化电路中脉冲信号产生电路的信号图。 FIG signal voltage conversion circuit, the pulse signal generating circuit - [0056] Figure 6 embodiment the frequency of several embodiments of the present invention.

[0057] 图7为本发明一实施例中频率-电压转化电路中第一寄生电容消除电路的示意图。 A first voltage conversion circuit schematic diagram of a parasitic capacitance canceling circuit - [0057] a frequency in the FIG. 7 embodiment of the present invention.

[0058] 图8为本发明一实施例中频率-电压转化电路中第二寄生电容消除电路的示意图。 A second voltage conversion circuit schematic parasitic capacitance canceling circuit - [0058] Figure 8 embodiment of the present invention a frequency.

[0059] 图9为本发明一实施例中内置振荡电路中环形振荡器的示意图。 [0059] FIG. 9 is a schematic diagram of the built-in oscillation circuit of a ring oscillator embodiment of the present invention.

[0060] 图10为本发明一实施例中内置振荡电路中多倍分频器的示意图。 [0060] FIG. 10 is a schematic diagram of the built-in oscillation circuit to a multiple of the frequency divider embodiment of the present invention.

具体实施方式 detailed description

[0061] 为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容作进一步说明。 [0061] To make the present invention more clearly understood, the following description in conjunction with the accompanying drawings, the present invention will be further described. 当然本发明并不局限于该具体实施例,本领域内的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。 Of course, the present invention is not limited to this specific example embodiments, those skilled in the art generally known alternative also encompassed within the scope of the present invention.

[0062] 其次,本发明利用示意图进行了详细的表述,在详述本发明实例时,为了便于说明,示意图不依照一般比例局部放大,不应以此作为对本发明的限定。 [0062] Next, the present invention utilizes a detailed schematic representation, in instances when the detailed description of the present invention, for convenience of explanation, a schematic partial enlarged not in accordance with the general proportion, not as limiting the present invention.

[0063] 图2为本发明一实施例中内置振荡电路的示意图。 [0063] FIG. 2 is a schematic embodiment of a built-in oscillation circuit embodiment of the present invention. 如图2所示,本发明所述内置振荡电路利用闭环结构,通过反馈控制实现稳定的输出频率。 , The present invention is the built-in output frequency oscillating circuit using a closed loop configuration, by stable feedback control 2 shown in FIG. 所述内置振荡电路包括基本电流产生电路11和环形振荡器13、频率-电压转化电路15以及差分放大电路12。 The oscillation circuit includes a built-in base current generating circuit 11 and ring oscillator 13, a frequency - voltage conversion circuit 15 and a differential amplifier circuit 12. 其中环形振荡器13、频率-电压转化电路15以及差分放大电路12构成一个负反馈校正环路。 Wherein the ring oscillator 13, a frequency - voltage conversion circuit 15 and a differential amplifier circuit 12 constitute a negative feedback correction loop.

[0064] 在本发明所述内置振荡电路中,所述基本电流产生电路11将参考电压Vref转化为参考电流Iref,在所述负反馈校正环路中,所述环形振荡器13产生频率信号fout,所述频率-电压转化电路15接收所述参考电压Vref和频率信号fout,并输出反馈电压Vout; 所述差分放大电路12接收并比较所述参考电流Iref和反馈电压Vout,并产生一个正比于所述参考电流Iref和反馈电压Vout差值的控制电压Vctr,以控制环形振荡器13的频率进行反馈校正。 [0064] In the present invention, the built-in oscillation circuit, the base current generating circuit 11 is converted to the reference voltage Vref is a reference current Iref is, in the negative feedback correction loop, the ring oscillator 13 generates a frequency signal fout , the frequency - voltage conversion circuit 15 receives the reference voltage Vref and the frequency of the FOUT signal, and outputs a feedback voltage Vout of; the differential amplifier circuit 12 receives and compares the reference current Iref and a feedback voltage Vout of, and proportional to produce a Vctr controls the voltage of the reference current Iref and the difference between the feedback voltage Vout, to control the frequency of ring oscillator 13 is feedback-corrected. 在内置振荡电路的工作过程中,环形振荡器13的输出频率的受到温度、工艺偏差和电源电压等环境的影响,例如当温度变化时,假设温度上升时,控制电压Vctr瞬间未改变,则环形振荡器13的振荡输出频率下降,故频率-电压转化电路15的反馈电压Vout 开始减小,而参考电压Vref保持不变,则差分放大电路12的控制电压Vctr减少,随后环形振荡器13的输出频率fout随控制电压Vctr的减少而增加,频率-电压转化电路15的反馈电压Vout随之增加,则负反馈调节一直进行,直到反馈电压Vout和参考电压Vref相等,即内置振荡电路的环路再次稳定为止;同样,当温度下降时,也发生相同的负反馈调节过程, 直至内置振荡电路的环路再次稳定为止。 Built-in oscillation circuit operation, the output frequency of the ring oscillator 13 is affected by the temperature, process variation, and power supply voltage environment, such as when the temperature changes, it is assumed that the temperature rises, the control voltage Vctr not instantaneously change, the annular the oscillation frequency of the oscillator output 13 drops, the frequency - voltage Vout feedback voltage conversion circuit 15 begins to decrease, and the reference voltage Vref is kept constant, the differential amplifier circuit 12 a control voltage Vctr is reduced, then the output of the ring oscillator 13 with frequency fout Vctr controls the voltage is increased to reduce the frequency - voltage Vout feedback voltage conversion circuit 15 increases, the negative feedback regulation continues until the feedback voltage is equal to Vout and reference voltage Vref, i.e., the built-in oscillation circuit loop again It is stable; loop Similarly, when the temperature decreases, the negative feedback regulation same process takes place again until the built-in oscillation circuit is stable.

[0065] 图3为本发明另一实施例中内置振荡电路的示意图,如图3所示,所述内置振荡电路还可以包括稳压产生器16和多倍分频器14,所述稳压产生器16接收一外部电源VDD,并将VDD转化为稳定输出的电源电压VDDA和参考电压Vref,所述电源电压VDDA为所述内置振荡电路中基本电流产生电路11和负反馈校正环路提供稳定的电源电压,从而保证内置振荡电路的稳定工作。 Schematic diagram of the built-in oscillation circuit [0065] Figure 3 is a further embodiment of the invention, shown in Figure 3, the oscillator circuit may further include a built-in generator 16 and regulator 14 times frequency divider, said voltage regulator generator 16 receives an external power supply VDD, and the VDD supply voltage VDDA into a stable output and a reference voltage Vref, to the supply voltage VDDA generating said oscillation circuit built in the base current circuit 11 and a negative feedback correction loop to provide a stable supply voltage, thereby ensuring stable operation of the built-in oscillation circuit. 所述多倍分频器14用于对所述环形振荡器13产生频率信号fout 进行分频,产生分频后的频率信号fb至所述频率-电压转化电路15,增加设置所述多倍分频器14能够使所述频率-电压转化电路15能够稳定工作。 The multiple frequency divider 14 for the ring oscillator 13 generates a frequency dividing signal fout, the frequency signal fb generated after frequency division to the frequency - voltage conversion circuit 15 is provided to increase the multiple points 14 can cause the frequency of the frequency - voltage conversion circuit 15 can stably work.

[0066] 图4. 1为本发明一实施例中内置振荡电路中基本电流产生电路的示意图。 [0066] FIG. 4.1 schematic diagram of the built-in oscillation circuit base current generating circuit according to an embodiment of the present invention. 在较佳的实施例中,多路可修调镜像电路可以采用共源共栅电流镜结构,从而进一步减少了镜像电流的温度系数,使得参考电流Iref的输出正比于电流II,且与温度无关。 In the preferred embodiment, multiplexing may be employed trimming mirror circuit common-source cascode current mirror configuration, thereby further reducing the temperature coefficient of the current mirror, so that the output of the reference current Iref proportional to the current II, and independent of temperature .

[0067] 如图4. 1所示,所述镜像电路为多路可修调镜像电路,所述基本电流产生电路11 包括第一运算放大器A1、第一放大管Ml(第一放大管为NM0S管)、可修调电阻(Rp+Rn)和镜像电路,所述第一运算放大器A1的输入端分别接参考电压Vref和第一放大管Ml的第一连接端、所述第一运算放大器A1的输出端接所述第一放大管Ml的控制端,所述可修调电阻(Rp+Rn)两端分别接地和所述第一放大管Ml的第一连接端,所述第一放大管Ml的第二连接端接所述电源电压VDDA,所述镜像电路包括第一镜像输出管Mpl,所述第一镜像输出管Mpl 的控制端接所述第一放大管Ml的控制端、所述第一镜像输出管Mpl的第一连接端输出所述参考电流Iref、所述第一镜像输出管Mpl第二连接端接所述电源电压VDDA。 [0067] As shown in FIG 4.1, the mirror circuit is a multiple, trimming mirror circuit, the base current generating circuit 11 includes a first operational amplifier A1, a first amplifier tube Ml (first amplification tube NM0S tube), can trim resistance (Rp + Rn) and a mirror circuit, the first input terminal of the operational amplifier A1 are respectively connected to a first terminal connected to the reference voltage Vref and the first amplifier tube Ml of the first operational amplifier A1 the output end of the first control terminal Ml of amplifier tube, said trimming resistor (Rp + Rn) and grounded at both ends respectively connected to a first end of said first amplifying Ml tube, said first tube to enlarge Ml second connecting end of said power supply voltage VDDA, the mirror circuit comprises a first mirror Mpl outlet tube, said first mirror control terminal of the first output tube amplifier tube Mpl control terminal of Ml, the a first end of a first connecting tube output mirror Mpl output the reference current Iref, the output of said first mirror end of said second connecting pipe Mpl supply voltage VDDA. 其中所述第一运算放大器A1接收一参考电压Vref,经所述可修调电阻(Rp+Rn)修调后由第一放大管A1 输出一中间电流II,所述中间电流II经所述镜像电路输出参考电流Iref。 Wherein said first operational amplifier A1 receives a reference voltage Vref, via said trimming resistor (Rp + Rn) after trimming to an intermediate output from the first current II amplifier tube A1, the intermediate II by the current mirror circuit outputs the reference current Iref.

[0068] 图4. 2为本发明另一实施例中内置振荡电路中基本电流产生电路的示意图。 Oscillation circuit schematic diagram of the built-in base current generating circuit [0068] FIG another embodiment of the present invention 4.2. 如图4. 2所示,所述基本电流产生电路11包括第一运算放大器A1、第一放大管M1、可修调电阻(Rp+Rn)和镜像电路,在实施例中镜像电路包括第一镜像输入管M3,第二镜像输入管M2、 第一镜像输出管Mnl和第二镜像输出管Mpl,所述第一镜像输入管M3的控制端接所述第一放大管Ml的第二连接端、所述第一镜像输入管M3的第一连接端接所述第二镜像输入管M2 的第二连接端、所述第一镜像输入管M3的第二连接端接一电源电压VDDA,所述第二镜像输入管M2的第二连接端接所述第一放大管Ml的第二连接端,所述第一镜像输出管Mnl的控制端接所述第一镜像输入端M3的控制端、所述第一镜像输出管Mnl的第一连接端接所述第二镜像输出管Mpl的第二连接端,所述第一镜像输出管Mnl的第二连接端接所述电源电压VDDA,所述第二镜像输出管Mpl的控制端接所述第二镜像输入管M2的控制端,所述 As shown, the base current generating circuit 11 includes a first operational amplifier A1, a first amplifier tube M1, can trim resistance (Rp + Rn) and a mirror circuit 4.2, in an embodiment comprising a first mirror circuit mirroring transistor M3 input, a second input pipe mirror M2, a first mirror and a second mirror Mnl outlet tube outlet tube Mpl, the control terminal of the first mirror input transistor M3 connected to a first end of a second pipe amplification of Ml a first end connected to said input of said first mirror transistor M3 is connected to a second input terminal of the second mirror transistor M2, a second input connected to the first mirror transistor M3 a termination power supply voltage VDDA, the second mirror M2 is a second inlet tube connected to a first end of said second enlarged end of the tube is connected Ml, the control terminal of the control terminal of the first mirror of the first mirror Mnl outlet tube input terminal of M3, the a second connection terminal connected to a first end of said output of said first mirror of the second mirror Mnl tube Mpl outlet tube, the first tube output mirror Mnl second end connected to the power supply voltage VDDA, the first said control terminal of two control terminal of the second mirror Mpl tube output transistor M2 of the input image, the 第二镜像输出管Mpl的第一连接端输出所述参考电流Ib,所述第二镜像输出管Mpl的第二连接端与一第一镜像输出管Mnl的第一连接端连接。 A first end of the second connecting tube output mirror Mpl output the reference current Ib, a second end connected to the second mirror Mpl outlet tube connected to a first end connected to a first output mirror Mnl the tube.

[0069] 图4. 3为本发明另一实施例中内置振荡电路中基本电流产生电路的示意图。 [0069] FIG. 4.3 schematic diagram of the built-in oscillation circuit base current generating circuit according to another embodiment of the present invention. 如图4. 3所示,在较佳的实施例中,所述镜像电路为多路可修调镜像电路,所述基本电流产生电路11包括第一运算放大器A1、第一放大管Ml(第一放大管为NMOS管)、可修调电阻(Rp+Rn) 和镜像电路,在实施例中镜像电路采用多路可修调镜像电路,包括第一镜像输入管M3,第二镜像输入管M2、多个第一镜像输出管Mnl~Mnn和多个第二镜像输出管Mpl~Mpn,所述第一镜像输入管M3的控制端接所述第一放大管Ml的第二连接端、所述第一镜像输入管M3的第一连接端接所述第二镜像输入管M2的第二连接端、所述第一镜像输入管M3的第二连接端接一电源电压VDDA,所述第二镜像输入管M2的第二连接端接所述第一放大管Ml的第二连接端,每一所述第一镜像输出管Mnl~Mnn的控制端均接所述第一镜像输入管M3的控制端、每一所述第一镜像输出管Mnl~Mnn的第二连接端接所述电源电压VDDA,每一所述 4. As shown in FIG. 3, in the preferred embodiment, the mirror circuit is a multiple, trimming mirror circuit, the base current generating circuit 11 includes a first operational amplifier A1, a first amplifier tube Ml (first an enlarged tube NMOS transistor), a trimming resistor (Rp + Rn) and mirror circuit mirror circuit in an embodiment using multiple, trimming mirror circuit comprises a first mirror M3 inlet tube, inlet tube second mirror M2 , the plurality of first mirror Mnl ~ Mnn outlet tube and a plurality of second mirror outlet tube Mpl ~ Mpn, input control terminal of the first mirror transistor M3 connected to the first end of the second tube Ml amplification of the connecting a first end of said first mirror transistor M3 second input terminal connected to a second input mirror transistor M2, a second input connected to the first mirror transistor M3 a termination power supply voltage VDDA, a second mirror a second input transistor M2 is connected to a first end of said second enlarged end of the tube is connected Ml, each of said first tube output mirror Mnl ~ Mnn are connected to the control terminal of the mirror control terminal of the first input transistor M3 each of said first mirror Mnl ~ Mnn outlet tube connected to a second end of said supply voltage VDDA, each of said 第二镜像输出管Mpl~Mpn的控制端均接所述第二镜像输入管M2的控制端,所述第二镜像输出管的相连后输出所述参考电流Ib,每一所述第二镜像输出管Mpl~Mpn的第二连接端与一第一镜像输出管Mnl~Mnn的第一连接端连接。 Second mirror output tube Mpl ~ Mpn control terminal connected to the control terminal of each input transistor M2 of the second mirror, the output of the reference current Ib is connected to the second mirror output pipe, each of the second output mirror a second connecting end Mpl ~ Mpn pipe connected to a first end connected to a first mirror Mnl ~ Mnn of the outlet tube. 所述基本电流发生电路11选择6位可修调电阻、6路可修调镜像电流模块和两路高频低频选择镜像电流模块进行修调,能够修调工艺偏差带来的频率偏移,达到输出频率要求的精度。 The base current generating circuit 11 can select the trimming resistors 6, 6 can override the current mirror module, and two high-frequency low-frequency image current selection module trimming can trim the frequency offset caused by the process variations to achieve output frequency accuracy requirements.

[0070] 具体地,在实际工艺生产过程中,所述内置振荡器电路的输出频率fout的温度偏差取主要决于环路锁定以后电阻和电容的温度特性。 Temperature of the output frequency fout [0070] Specifically, in the actual production process, the internal oscillator circuit is mainly dependent on the deviation takes the loop is locked after the temperature characteristics of resistance and capacitance. 在实际工艺中电容的温度系数在每摄氏度1〇_ 6次量级,而单个电阻的温度系数在10 _3次量级,所以温度系数主要由电阻温度特性决定。 Capacitance in the actual process temperature coefficient 1〇_ order of 6 per degree Celsius, and the temperature coefficient of the resistor in a single order of 10 times _3, mainly determined by the temperature coefficient of resistance-temperature characteristic. 为了达到-20°c~85°C范围1%以内偏差,需要对电阻温度系数进行补偿,因此可修调电阻选用正温度系数的电阻Rp和负温度系数的电阻Rn串联互补,使得可修调电阻不受温度的影响。 In order to achieve -20 ° c ~ 85 ° C within 1% deviation range, it is necessary to compensate for temperature coefficient of resistance, thus trimming the resistor Rn and a negative temperature coefficient of resistance Rp selected positive temperature coefficient of resistance of the complementary series, such that the trim resistance is not affected by temperature.

[0071] 以下结合图4. 3所示的基本电流产生电路进行详细说明,由于电阻和电容存在一定的工艺偏差,故为了达到我们所需要的频率,需要修调工艺偏差。 [0071] The following basic current shown in FIG binding 4.3 generation circuit described in detail, since there is a certain process variation resistance and capacitance, so we need to achieve frequency, it is necessary trimming process variations. 所述内置振荡电路输出频率的工艺偏差可以通过修调位进行修正,实现〇. 1 %的修调精度。 The output frequency of the oscillation circuit built process variation can be corrected by trimming bits, to achieve square. Trim 1% accuracy. 为达到〇. 1 %的频率修调精度,又要覆盖工艺电压温度偏差带来的频偏,假设频偏为±50%,则至少需要l〇g2(1°°Q) =lObit控制位,加上选择频率范围(例如:27M,40M还是49M或者是315M,433M),为了两者能覆盖修调范围,需要再增加2bit来保证相邻细调范围互相重叠没有断节,因此需要至少要求12bit的控制位。 To achieve square. 1% frequency precision trimming, but also covers the offset voltage of the temperature variation caused by the process, it is assumed frequency deviation ± 50%, then at least l〇g2 (1 °° Q) = lObit control bit, plus the selected frequency range (e.g.: 27M, 40M or 49M or 315M, 433M), in order to cover both the trimming range, increasing the need to fine-tune range to ensure 2bit adjacent sections overlap with each other without breaking, and therefore requires at least control bits of 12bit. 如果单一控制可调电阻R或者单一控制电流镜比例,则版图面积都将相当大;如果单一采用控制可调电阻,那么需要对的电阻,版图面积同样会相当大,对于电流也一样。 If a single control or a single adjustable resistor R ratio control current mirror, the layout area can be quite large; control if using a single adjustable resistor, the resistance, the layout area also needs to be quite large, for the same current. 因此,本发明所述内置振荡电路采用电流镜高位控制和可调电阻低位细调结合的方法节省版图面积,只需要可调电阻2 6=64对,镜像电流26=64对,总的面积远小于单一调节方式的1024对。 Accordingly, the present invention is a method of using the built-in oscillation circuit and the adjustable current mirror control high resistance lower bound fine save layout area, only an adjustable resistor 26 = 64 pairs, 64 pairs of mirror current = 26, the total area of ​​the far less than 1024 single adjustment mode pair.

[0072] 结合图3所示,所述内置振荡电路包括M个第一镜像输出管,所述基本电流产生电路接收一多位控制信号,所述多位控制信号包括频率选择位、镜像电路调节位和电阻调节位,所述频率选择位控制N个第一镜像输出管(Mnl和Mn2)与所述第一镜像输入管M3的比例值以实现频率范围选择,所述镜像电路调节位控制其余L个第一镜像输出管(Mn3~Mnn) 与所述第一镜像输入管M3的比例值以实现频率范围内粗调,所述电阻调节位控制所述可修调电阻(Rp+Rn)的电阻值以实现频率范围内精调。 [0072] in conjunction with FIG. 3, the built-in oscillation circuit comprises M first mirror output transistor, the base current generating circuit receives a multi-bit control signal, said control signal comprises a multi-bit frequency selection bits, adjusting mirror circuit bit and bit resistance adjustment, the frequency selection control bits of the N output first mirror tube (with Mnl and of Mn2) ratio value of the first input transistor M3 mirror to achieve a selected frequency range, said mirror control circuit adjusts the rest position a first mirror ratio value L outlet tube (Mn3 ~ Mnn) input to the first mirror transistor M3 to achieve coarse frequency range, the resistance adjusting said control bit trimming resistor (Rp + Rn) of the resistance value of the frequency range to achieve fine tuning. 其中,N、L及M均为正整数,所述N个第一镜像输出管和L个第一镜像输出管均为不同的第一镜像输出管,且N+L=M。 Where, N, L and M are both positive integers, the N L first mirror and a first outlet tube outlet tube are different from the mirror image of the first outlet tube, and N + L = M. 在本实施例中,以M=8,N=2为例进行说明。 In the present embodiment, at M = 8, N = 2 as an example. 一编码器18向所述基本电流产生电路产生一十四位的控制信号D〈13:0>,其中D〈13:12>为频率选择位(00、01、10、11) ;D〈11:6>为镜像电路调节位; D〈5: 0>为电阻调节位;在确定要输出的频率之后,选择D〈13:12>的值,为了要覆盖工艺电压温度偏差带来的频偏(假设±50% ),又要达到0. 1%的频率修调精度。 The encoder 18 generates a basic current to said circuit generates a control signal fourteen D <13: 0>, wherein D <13:12> to select the frequency bits (00,01,10,11); D <11 : 6> bits adjusted mirror circuit; D <5: 0> is the resistance adjustment bits; after determining the frequency to be output, selecting D <13:12> value, the process in order to cover the offset voltage caused by the temperature deviation (assuming ± 50%), but also to achieve the 0.1% precision frequency trim. 所述电路电阻实现0. 1 %的修调精度,在镜像电流处实现频率粗调达到约为0. 64%的精度。 The circuit resistance achieved 0.1 percent of trimming accuracy, achieve an accuracy of the frequency rough adjustment of about 0.64% at the mirror current. 假设要实现频率输出fout,那么多路可修调电阻(Rp+Rn)的电阻值为R,则(Rp+Rn)的调节范围为 Suppose you want to achieve frequency output fout, the multiplexer can then trimming resistor (Rp + Rn) resistance value R, the (Rp + Rn) is adjustable between

[0073] [0073]

Figure CN103066952BD00151

[0074] 电阻调节位D〈5:0>=000000111111,频率可以减小的范围为0• 1 % -6. 4%,实现精调。 [0074] The resistance adjusting bits D <5: 0> = 000000111111, the frequency can be reduced within a range of 0 • 1% -6 4%, to achieve fine adjustment. 要覆盖工艺电压温度偏差带来的频偏(假设±50% ),镜像电流的精度为要小于6. 4%,那么100% /6. 4% =15. 6〈24,可以知道至少需要4个可修调位,这里采用6位可修调电路使频率覆盖范围足够大。 Frequency offset (assuming ± 50%) to cover the temperature difference caused by voltage process, the accuracy of the current mirror is less than 6.4%, then 100% / 6.4% = 15.6 <24 can be known at least 4 a trimming position may be, may be employed herein trimming circuit 6 so that a sufficiently large frequency coverage. 假设基本镜像电流Iref=K*Il,加上粗调电流的大小,则镜像电流Iref为: Assume substantially mirror current Iref = K * Il, together with coarse magnitude of the current, the current Iref is mirrored:

[0075] [0075]

Figure CN103066952BD00152

[0076] 镜像电路调节位D〈ll:6>=100000时频率为要求的中心频率,则D〈11:6>=111111 为大与中心频率50%的频率,D〈11:6>=000000为小于中心频率50%的频率。 [0076] mirror circuit regulator bits D <ll: 6> = 100000 frequency as required by the center frequency, then D <11: 6> = 111111 50% of the frequency is large as the center, D <11: 6> = 000000 50% less than the frequency of the center frequency. 这样就可以覆盖总的工艺偏差,可以经过修调实现频率输出。 This can cover the overall process variation can be achieved through trimming frequency output.

[0077] 频率选择位(D〈13:12>)控制比例实现大的电流输出,实现范围变化较大的频率改变。 [0077] Frequency selection bits (D <13:12>) to achieve a large proportion of the control current output, the range of variation to achieve greater frequency change. 要覆盖工艺电压温度偏差带来的频偏(假设±50% ),那么总的频偏100% /212=0. 024 %远小于0. 1 %的频率修调精度。 To cover a frequency deviation caused by temperature deviation voltage process (assuming ± 50%), then the total offset of 100% / 212 = 0.024% much less than 0.1% precision trimming. 这样就可以覆盖总的工艺偏差,可以经过修调实现频率输出。 This can cover the overall process variation can be achieved through trimming frequency output.

[0078] 其中,可修调电阻(Rp+Rn)表示正温度系数的电阻和负温度系数的电阻相加,在设计相当的情况下,温度系数相互抵消。 [0078] wherein, the trimming resistor (Rp + Rn) represents the resistance of the negative temperature coefficient resistor and a positive temperature coefficient are added, in the case of comparable design, the temperature coefficients offset each other. 第一运算放大器A1根据参考电压Vref产生相应的电流11,第二镜像输入管M2的控制端的电压Vbp用以保证第二镜像输入管M2和第一镜像输入管M3工作在饱和区,第一运算放大器A1、第一放大管Ml形成负反馈,用以保证图4. 3 中P点的电压为参考电压Vref,第第二镜像输入管M2和第一镜像输入管M3与多个第一镜像输出管Mnl~Mnn和多个第二镜像输出管Mpl~Mpn为镜像关系。 A first operational amplifier A1 generates a corresponding current 11 according to the reference voltage Vref, a voltage Vbp control input terminal of the second transistor M2 mirror to ensure that the second input transistor M2 mirror input transistor M3 and the first mirror in the saturation region, the first operation amplifier A1, a first negative feedback amplifier tube Ml is formed to ensure that the voltage at point P in FIG. 4.3 is a reference voltage Vref, the second transistor M2 and the second mirror input transistor M3 and the first mirror input a plurality of first mirror output Mnl ~ Mnn tube and a plurality of second mirror Mpl ~ Mpn outlet tube is a mirror image relationship.

[0079] 由上分析可得基本电流产生电路11产生的中间电流II为:Il=Vref7(Rp+Rn); [0079] Analysis of the available base current generating circuit 11 generates intermediate current II is: Il = Vref7 (Rp + Rn);

[0080] 由镜像电路可得:Iref=K*I1 ; [0080] can be obtained by a mirror circuit: Iref = K * I1;

[0081] 其中,Vref表示所述参考电压,(Rp+Rn)为可修调电阻的电阻值,其中Rp为可修调电阻的正温度系数的电阻,Rn表示可修调电阻的负温度系数的电阻,参考电流Iref的值与II成正比,K为比例系数;则所述基本电流产生电路11产生的参考电流公式⑴: [0081] where, Vref represents the reference voltage, (Rp + Rn) to be trim resistance of the resistor, wherein the resistor Rp is a positive temperature coefficient of resistance may trimming, Rn represents a negative temperature coefficient of resistance trimming the resistance value of the reference current Iref proportional II, K is a proportionality factor; is the base current generating circuit 11 generates a reference current of the formula ⑴:

[0082]Iref=K*Vref/ (Rp+Rn)------(1) [0082] Iref = K * Vref / (Rp + Rn) ------ (1)

[0083] 图5. 1为本发明一实施例中内置振荡电路中频率-电压转化电路的示意图。 A schematic diagram of a voltage conversion circuit - [0083] Figure 5. 1 In this example a built-frequency oscillation circuit embodiment of the present invention. 如图5. 1所示,所述频率-电压转化电路15包括开关管模块、充放电容和输出电容C1,所述开关管模块接收所述参考电流Iref•和频率信号fout或分频后的频率信号fb,并在所述频率信号fout或分频后的频率信号fb的控制下,进行使所述参考电流Iref对所述充放电容进行充电、以及在充放电容和输出电容C1之间进行电荷重新分配和对所述充放电容进行放电的过程,以使所述输出电容输出反馈电压。 As shown, the frequency of 5.1 - Voltage conversion circuit 15 includes a switch module, and the output capacitor charge and discharge capacitor C1, the switch module receives the reference current Iref • and the frequency-divided frequency signal fout or after frequency signal fb, and the frequency of the control signal at fb of the frequency-division or signal fout, the reference current Iref for the charge and discharge of the capacitor is charged, and charge and discharge the capacitance between the output capacitor C1 and and the charge redistribution capacitance of said charge-discharge process of discharging, so that the output feedback voltage of the output capacitor.

[0084] 图5. 1~图5. 3为一实施例中内置振荡电路中频率-电压转化电路的示意图。 [0084] FIG. 5.1 - 5.3 FIG frequency oscillation circuit embodiment examples a built - schematic diagram of a voltage conversion circuit. 如图5. 1所示,在本实施例中,所述频率-电压转化电路15接收如图3所示的多倍分频器14 输出的频率信号fout的分频信号fb,能够使所述频率-电压转化电路15更稳定地工作,当然所述频率-电压转化电路15直接接收所述环形振荡器输出的频率信号fout同样能够实现工作过程。 As shown, in this embodiment, the frequency 5. 1-- fb divided signal voltage conversion circuit 15 receives the output 3 shown in FIG multiple of the frequency divider 14 frequency signal fout, enabling the frequency - voltage conversion circuit 15 work more stably, of course, the frequency - voltage conversion circuit 15 directly receives a frequency output signal fout of the ring oscillator to achieve the same working process. 所述频率-电压转化电路包括开关管模块、充放电容和输出电容,所述开关管模块接收所述参考电流Iref•和频率信号fout的分频信号fb,并在所述频率信号fout的分频信号fb的控制下,进行使所述参考电流Iref•对所述充放电容进行充电、以及在充放电容和输出电容之间进行电荷重新分配和对所述充放电容进行放电的过程,以使所述输出电容输出反馈电压。 The frequency - voltage conversion circuit comprises a switch module, and output capacitors charge and discharge, the switch receiving said frequency-divided signal fb and the reference current Iref • frequency signal fout tube module, and the signal fout is divided in frequency under the control of the frequency signal fb performs reference current Iref • the charge and discharge of the capacitor is charged, and the process of charge between the charge-discharge capacity and output capacitors and redistribute the charge and discharge of the capacitor is discharged, so that the output feedback voltage of the output capacitor. 所述频率-电压转化电路还包括脉冲信号产生电路和寄生电容消除电路。 The frequency - voltage conversion circuit further comprises a pulse signal generating circuit and parasitic capacitance cancellation circuit. 所述寄生消除电路包括第一寄生消除电路和第二寄生消除电路,所述充放电容包括第一充放电容Cc和第二充放电容Cc1,所述开关管模块包括第一开关管Ml1、第一充电管M19、第一放电管M13、第二开关管M12、第二充电管M14、第二放电管M16、第一防串扰管20、第二防串扰管18,其中第一开关管M11、第一充电管M19、第一放电管M13、第二开关管M12、第二充电管M14、第二放电管M16、第一防串扰管20、第二防串扰管18均为M0S管;所述脉冲信号产生电路根据所述频率信号产生多个控制开关模块的脉冲信号,所述脉冲信号产生电路根据所述频率信号的分频信号fb和分频信号的反相信号fb-产生多个脉冲信号,包括八个脉冲信号,用于产生控制第一充放电容Cc、第二充放电容Cel的脉冲信号,图6为本发明一实施例中频率-电压转化电路中脉冲信号产生电路的信号图,如图6所示,第 The parasitic cancellation circuit comprises a first and second parasitic parasitic eliminating circuit eliminating circuit, the charge and discharge capacitor comprises a first charge and discharge capacitance Cc and the capacitor Cc1 and the second charging and discharging, the switch module comprises a first switching transistor Mil, M19 first charging pipe, a first discharge M13, the second switching transistor M12, a second charging pipe M14, M16 second discharge tube, the first crosstalk prevention pipe 20, a second crosstalk prevention tube 18, wherein the first switching transistor M11 a first charging pipe M19, a first discharge M13, the second switching transistor M12, a second charging pipe M14, M16 second discharge tube, the first crosstalk prevention tube 20, second tube 18 are M0S crosstalk prevention tube; the said pulse signal generating circuit generates a plurality of pulse signals to control switching module based on the frequency signal, the pulse signal generation circuit generates a plurality of pulses in accordance with frequency-divided signal of the frequency fb of the signal and the inverted signal of the divided signal fb- the signal voltage conversion circuit, a pulse signal generating circuit - a signal, comprising eight pulse signal, for generating a first charge and discharge control capacitor Cc, a second charge and discharge the capacitor Cel of the pulse signal, the present embodiment of FIG. 6 embodiment of the invention a frequency FIG, 6, the first 至第四脉冲信号CLK1、CLK2、CLK3、CLK4以及依次与第一至第四脉冲信号的相位相应相差半个周期的第五至第八脉冲信号的CLK11、CLK21、CLK31、CLK41。 To fourth pulse signals CLK1, CLK2, CLK3, CLK4, and in turn the first to fourth phase pulse signal corresponding to the phase difference pulse signal CLK11 fifth to eighth half cycle, CLK21, CLK31, CLK41. 其中,所述第一至第四脉冲信号的脉冲信号宽度总和小于输入频率的半个周期,所述第五至第八脉冲信号的脉冲信号宽度总和小于输入频率的半个周期。 Wherein the sum of the pulse width of the first to fourth pulse signal is less than a half cycle of input frequency, the sum of the pulse widths of the fifth to eighth pulse is less than a half cycle of the input signal frequency. 所述第一开关管Mil的控制端接所述频率信号fb、第一连接端接所述参考电流Iref、第二连接端接第一节点P1,所述第二开关管M12的控制端接所述频率信号的反相信号fb-、第一连接端接所述参考电流Iref•、第二连接端接第二节点P2,所述第一充放电容Cc一端接所述第一节点P1、另一端接地,所述第二充放电容Cel一端接所述第二节点P2、另一端接地,所述第一充电管M19的控制端接脉冲信号CLK1,两连接端分别接第一节点P1和输出电容Cl之间,所述第二充电管M17的控制端接脉冲信号CLK11-,两连接端分别接第二节点P2和输出电容C1之间,所述第一放电管M13的控制端接脉冲信号CLK2,两连接端分别接地和第一节点P1,所述第二放电管M14的控制端接脉冲信号CLK21,两连接端分别接地和第二节点P2,所述第一寄生电容消除电路输入端接多个所述脉冲信号、输出端接所述第一节点P1 Said first switching transistor Mil control terminal of the frequency signal fb, a first end connected to the reference current Iref, a second end connected to a first point P1, the second switch M12 of the control terminal fb- inverted signal of said frequency signal, a first end connected to the reference current Iref •, a second end connected to the second points P2, charge and discharge said first end of said first capacitance Cc is a point P1, the other one end grounded, the charge and discharge capacitor Cel a second end of said second points P2, the other end, the first tube charging control terminal of the pulse signal CLK1 M19, two ends are connected to the first node and an output P1 between the capacitance Cl, the second charging tube between the second point P2 and the capacitor C1 the output pulse signal control terminal CLK11-, two connection terminals respectively connected M17, M13 of the first discharge control terminal of the pulse signal CLK2, and two ground terminals are connected to the first node P1, the second discharge control terminal of the pulse signal CLK21 M14, and the ground terminals are connected to two second points P2, the first input terminal of the parasitic capacitance cancellation circuit the plurality of pulse signals, the output end of said first point P1 所述第二寄生消除电路输入端接多个所述脉冲信号、输出端接所述第二节点P2,所述第一防串扰管M20的控制端接脉冲信号CLK1-、两连接端连接于所述第一充电管M19和输出电容C1之间,所述第二防串扰管M18的控制端接脉冲信号CLK11、两连接端连接于第二充电管Cel和输出电容C1之间。 Elimination of the second parasitic input terminal circuit of said plurality of pulse signals, the second output end points P2, the first anti-M20 crosstalk tube terminating control pulse signal CLK1-, connected to the two connection ends said first tube between M19 and charging the output capacitor C1, the second control pipe end crosstalk prevention pulse signal CLK11 M18, and two connection ends connected between the second output and the charging tube Cel capacitor C1. 此外,所述开关模块还包括第三放电管M15和第四放电管M16,所述第三放电管M15的控制端接脉冲信号CLK3、两连接端接所述第一充放电容Cc和地之间,所述第四放电管M16的控制端接脉冲信号CLK31、两连接端接所述第二充放电容Cc1之间,所述第三放电管M15用于进一步对所述第一充放电容进行放电,所述第四放电管M16用于进一步对所述第二充放电容进行放电,所述第三放电管M15和所述第四放电管M16均为MOS管。 Furthermore, the discharge tube switching module further comprises a third M15 and fourth M16 discharge vessel, the discharge control terminal of the third pulse signal of CLK3 is M15, a first end of said connecting two charge and discharge of the capacitance Cc and between the fourth discharge control terminal of the pulse signal CLK31 M16, the two second connection end between the capacitors Cc1 and charge-discharge, said third discharge M15 for further discharge capacity of the first charge discharging the fourth discharge M16 for further charging and discharging of the second capacitor is discharged, the third discharge tube M15 and M16 are MOS the fourth discharge tube.

[0085] 图7为本发明一实施例中频率-电压转化电路中第一寄生电容消除电路的示意图。 A first voltage conversion circuit schematic diagram of a parasitic capacitance canceling circuit - [0085] a frequency in the FIG. 7 embodiment of the present invention. 如图7所示,在优选的实施例中,所述第一寄生电容消除电路中第三节点P3的寄生电容与所述第一节点P1的寄生电容,其结构可以包括第i^一MOS管M21至第十七MOS管M27,所述第十一MOS管M21的源极和栅极相接并接所述电源电压VDDA、漏极接所述第三节点P3, 所述第十三MOS管M23的栅极接第一脉冲信号CLK2、漏极接所述第三节点P3、源极接所述第十二MOS管M22的源极,所述第十二MOS管M22的栅极接第一脉冲信号的反相信号CLK2-、 源极和漏极相接并接所述参考电压Vref,所述第十四MOS管M24和第十五MOS管M25的漏极均接所述第三节点P3、栅极和源极均接地,所述第十六MOS管M26的漏极接所述第三节点P3、栅极接第四脉冲信号CLK4、源极接所述第十七MOS管M27的源极,所述第十七MOS管M27的栅极接所述第四脉冲信号的反相信号CLK4-、源极和漏极相接并接所述第二节点P2。 As shown, in a preferred embodiment, the first parasitic capacitance 7 a third point P3 to eliminate a parasitic capacitance with the first node P1 of the parasitic capacitance of the circuit, the structure may include a first MOS transistor i ^ a seventeenth MOS transistor M21 to M27, a source and a gate of said eleventh MOS transistor M21 is connected to the supply voltage contact and VDDA, a drain connected to said third point P3, the thirteenth MOS transistor M23 is connected to the gate of the first pulse signal CLK2, a drain connected to the third node P3, a source connected to the twelfth source MOS transistor M22, the twelfth MOS transistor M22 is connected to the first gate an inverted signal of the pulse signal CLK2-, and source and drain contact connected to the reference voltage Vref, the drain of said fourteenth MOS transistor M24 and the fifteenth MOS transistor M25 are connected to the third node P3 , gate and source grounded, said sixteenth MOS transistor M26 is connected to the drain of said third point P3, the gate pulse signal CLK4, the fourth contact, a source connected to the source of the MOS transistor M27 of the seventeenth electrode, the gate of the seventeenth MOS transistor M27 is connected to the inverted signal of the fourth pulse signal CLK4-, source and drain contact and said second contact point P2. 其中,第i^一MOS管M21的寄生电容与第一开关管Ml的漏极的寄生电容相应相同,第十四MOS管M24和第十五MOS管M25与同第一节点P1点到地所接的第二放电管M3和第一放电管M5的寄生电容相应相同,第十二MOS管M22和第十三MOS管M23与同第一节点P1到反馈电压Vout之间的第一充电管M19的寄生电容相应相同,第十六MOS管M26和第十七MOS 管M27为开关控制端。 Wherein a parasitic capacitance of the i ^ and the drain of the first switching transistor Ml is a MOS transistor M21, a parasitic capacitance corresponding to the same, a fourteenth MOS transistor M24 and the fifteenth MOS transistor M25 and the point P1 with the first node to the ground and a second discharge tube connected M3 M5 parasitic capacitance corresponding to the same first discharge tube, the first tube charging MOS transistor M19 between the twelfth and the thirteenth MOS transistor M22 and M23 to the point P1 with the first feedback voltage Vout respective parasitic capacitance same, and a sixteenth MOS transistor M26 seventeenth MOS transistor M27 to the switching control terminal.

[0086] 在所述频率-电压转化电路中,所述第二寄生消除电路具有第四节点P4,所述第四节点P4的寄生电容与所述第二节点P2的寄生电容相等。 [0086] In the frequency - voltage conversion circuit, the cancellation circuit having a second parasitic fourth point P4, is equal to the parasitic capacitance of the fourth point P4 and the second node P2 of the parasitic capacitance. 图8为本发明一实施例中频率-电压转化电路中第二寄生电容消除电路的示意图。 A second voltage conversion circuit schematic parasitic capacitance canceling circuit - a frequency in the FIG. 8 embodiment of the present invention. 如图8所示,所述第二寄生消除电路包括第十八M0S管M28至第二十四M0S管M34,所述第十八M0S管M28的源极和栅极相接并接所述电源电压VDDA、漏极接所述第四节点P4,所述第二十M0S管M30的栅极接第一脉冲信号CLK21、漏极接所述第四节点P4、源极接所述第十九M0S管M29的源极,所述第十九M0S管M29的栅极接第五脉冲信号的反相信号CLK21-、源极和漏极相接并接所述参考电压Vref,所述第二^^一M0S管M31和第二十二M0S管M32的漏极均接所述第四节点P4、栅极和源极均接地GND,所述第二十三M0S管M33的漏极接所述第四节点P4、栅极接第八脉冲信号CLK41、源极接所述第二十四M0S管M34的源极,所述第二十四M0S管M34的栅极接所述第四脉冲信号的反相信号CLK41-、源极和漏极相接并接所述第二节点P2。 8, the cancellation circuit comprises a second parasitic M0S tube eighteenth through twenty-fourth M0S M28 M34 tube, the eighteenth source and the gate of M28 M0S tube and one of the power contact voltage VDDA, a drain connected to said fourth point P4, the gate of M30 twenty M0S tube connected to a first pulse signal CLK21, a drain connected to the fourth node P4, a source connected to the nineteenth M0S a source electrode of M29 tube, the inverted signal of the gate of M29 nineteenth M0S tube connected to the fifth pulse signal CLK21-, and source and drain contact connected to the reference voltage Vref, the second ^^ M0S and a twenty-second drain tube M31 M32 M0S tube connected the fourth node are P4, gate and source are grounded GND, a drain of the twenty-third M0S the fourth access tube M33 node P4, a gate connected to the eighth pulse signal CLK41, a source connected to the twenty-fourth tube M0S M34 source, a gate connected to the inverted twenty fourth tube M0S fourth pulse signal M34 signal CLK41-, source and drain contact and said second contact point P2.

[0087] 所述频率-电压转化电路采用差分结构,减少了参考电流Iref接输入节点P点的寄生电容对于频率-电压转化电路的影响,提高了振荡器的频率精度;同时,因为所述第一节点P1和第二节点P2存在较多的MOS管,会引入MOS管的寄生电容,假设第一节点P1和第二节点的电容大小均为Cpl,寄生电容对温度的敏感性较大,故在第一充放电容Cc和第二充放电容Cel充放电的过程中,MOS管的寄生电容会引起整个频率-电压转化电路的温度特性变差,因此现有技术,本发明所述频率-电压转化电路通过引入寄生消除电路,避免了寄生电容对内置振荡电路的影响,进而改善了整个系统的温度特性。 [0087] The frequency - voltage conversion circuit employs a differential configuration, the reference current Iref to reduce to the input node of the point P to the frequency of the parasitic capacitance - voltage conversion circuit Effect improve the frequency accuracy of the oscillator; Meanwhile, since the first present a node P1 and a second point P2 more MOS transistors, the parasitic capacitance will be introduced MOS transistor, assuming that the size of the capacitor and the second node of the first node P1 of Cpl are, the larger parasitic capacitance is sensitive to temperature, so in the first charge and the second charge-discharge capacitance Cc and the capacitor Cel discharge process of charging and discharging the parasitic capacitance caused by the MOS transistor entire frequency - voltage conversion circuit temperature characteristic deteriorates, and therefore the prior art, the present invention is frequency - a voltage conversion circuit is eliminated by introducing a parasitic circuit, to avoid the influence of parasitic capacitance of the built-in oscillation circuit, thereby improving the temperature characteristics of the entire system.

[0088] 此外,本发明所述频率-电压转化电路还可以采用如图5. 2及图5. 3所示的结构。 [0088] Further, the present invention is a frequency - voltage conversion circuit may also be employed in the structure shown in FIG. 5.2 and 5.3 in FIG. 如图5. 2所示,在所述频率-电压转化电路中,所述充放电容包括第一充放电容Cc,所述开关管模块包括第一开关管M11、第一充电管M19、第一放电管M13、第一防串扰管20和第一接地管M121,第一充放电容Cc,所述开关管模块包括第一开关管M11、第一充电管M19、第一放电管M13、第一防串扰管20和第一接地管M121均为MOS管;所述脉冲信号产生电路根据所述频率信号产生多个控制开关模块的脉冲信号,所述脉冲信号产生电路根据所述频率信号的分频信号fb和分频信号的反相信号fb-产生多个脉冲信号,用于产生控制第一充放电容Cc的脉冲信号,例如第一至第三脉冲信号CLK1、CLK2、CLK3。 Shown in FIG 5.2, the frequency - voltage conversion circuit, the charge and discharge capacitor comprises a first charge and discharge capacitor Cc, the switch module comprises a first switching transistor M11, a first charging pipe M19, the first a discharge M13, M121 tube 20 is first ground and a first crosstalk prevention tube, a first charge and discharge capacitor Cc, the switch module comprises a first switching transistor M11, M19 of the first charging pipe, a first discharge M13, the first and a crosstalk prevention pipe 20 are a first MOS transistor M121 ground tube; said pulse signal generating circuit generates a plurality of pulse signals to control switching module based on the frequency signal, the pulse signal of the divided frequency signal generating circuit in accordance with fb fb- inverted signal of the pilot signal and the frequency-divided signal generated plurality of pulse signals, for generating a first control capacitance Cc charge and discharge pulse signals, for example, the first to third pulse signals CLK1, CLK2, CLK3. 其中,所述脉冲信号的宽度的总和要小于输入频率的半个周期。 Wherein the sum of the widths of the pulse signal to be less than a half period of the input frequency. 所述第一开关管Mil的控制端接所述频率信号fb、 第一连接端接所述参考电流Iref、第二连接端接第一节点P1,所述第一充放电容Cc一端接所述第一节点P1、另一端接地,所述第一充电管M19的控制端接脉冲信号CLK1,两连接端分别接第一节点P1和输出电容C1之间,所述第一放电管M13的控制端接脉冲信号CLK2,两连接端分别接地和第一节点P1,所述第一防串扰管M20的控制端接脉冲信号CLK1-、两连接端连接于所述第一充电管M19和输出电容C1之间,第一接地管M121控制端接收所述频率信号的分频信号fb、第一连接端接所述参考电流、第二连接端Iref接地。 The first control terminal of the switching transistor Mil frequency signal fb, a first end connected to the reference current Iref, a second end connected to a first point P1, the first charge and a discharge end of said capacitor Cc the first point P1, the other end, the first tube charging control terminal of the pulse signal CLK1 M19, between the first point P1 and the output capacitor C1 are respectively connected to two connection terminals, the control terminal M13 of the first discharge tube then the pulse signal CLK2, and two ground terminals are connected to the first node P1, the first anti-M20 crosstalk tube terminating control pulse signal CLK1-, two connection ends connected to the first pipe charging the output capacitor C1 and M19 between the first ground pipe M121 control terminal for receiving said frequency divided signal fb signal, a first end connected to the reference current, a second terminal of Iref is connected to ground. 第一充电管、第一放电管、第一防串扰管和第一接地管均为MOS管。 A first charging pipe, a first discharge tube, the first tube and the first ground crosstalk prevention transistor are MOS transistors. 如图5. 3所示,在图5. 2所示的所述频率-电压转化电路的基础上,所述频率-电压转化电路还包括第三放电管M15,所述第三放电管M15的控制端接脉冲信号CLK2、两连接端接所述第一充放电容Cc和地之间,用于进一步对所述第一充放电容进行放电,所述第三放电管M15为MOS管。 Shown in FIG 5.3, the frequency shown in FIG. 5.2 - voltage conversion circuit based on the frequency - voltage conversion circuit further comprises a third discharge tube M15, M15 of the third discharge tube pulse signal CLK2 control terminal, a first end of said two connecting between the capacitance Cc and the charge and discharge, the discharge capacity for further discharging the first charge, the third MOS transistor to discharge M15.

[0089] 以下以图5. 1所示的较佳的所述频率-电压转化电路结构为例,说明所述频率-电压转化电路的工作过程,具体包括四个阶段:充电阶段、电荷重新分配、放电阶段和预充电过程。 [0089] In the following the preferred frequency shown in FIG. 5.1 - voltage conversion circuit structure as an example, description of the frequency - voltage conversion circuit during operation, comprises four stages: a charging phase, the charge redistribution , precharge and discharge phase. 为描述方便,描述中将所述频率-电压转化电路分为如图5. 1所示的第一转化电路151和第二转化电路152,当分频信号fb为低电平,分频信号的反相信号fb-为高电平时,第一转化电路151处于充电阶段,第二转化电路152处于电荷重新分配、放电阶段和预充电过程。 For ease of description, the description of the frequency - converted into a first voltage conversion circuit shown in FIG. 5.1 second conversion circuit 151 and circuit 152, when the frequency-divided signal fb is low, the frequency-divided signal fb- inverted signal is high, the first conversion circuit 151 in a charging phase, a second conversion circuit 152 in the charge redistribution, and precharge discharge phase.

[0090] 以频率-电压转化电路的第一转化电路151的工作过程为例。 [0090] frequency - a first conversion circuit 151 during operation of the voltage conversion circuit as an example. 在充电阶段中:在分频信号fb为低电平的时候,第一开关管Mil导通,参考电流Iref对第一充放电容Cc进行充电,第一节点P1点存在的寄生电容总和为Cpl(包括第一放电管M13、第三放电管M15、 第一充电管M19以及第一开关管Ml在第一节点P1产生的寄生电容),那么第一节点P1点存在的电容和为(Cc+Cpl),因此在对第一充放电容Cc进行充电的同时,也会对第一节点P1 的寄生电容Cpl进行充电。 In the charge phase: is at low level, the first switching transistor Mil is turned on, the reference current Iref to the first charge and discharge the capacitor Cc is charged in the divided signal FB, the sum of the parasitic capacitance of the node point P1 is present Cpl (including parasitic capacitance of the first discharge tube M13, a third discharge M15, M19 and the first tube first charging switch Ml generated at a first point P1), the first point P1 and point to the presence of capacitors (Cc + Cpl), and therefore the first charge and discharge at the same time charging the capacitor Cc, also the parasitic capacitance Cpl node P1 will be charged.

[0091] 当分频信号fb转为高电平,充电完成,第一开关管Ml截止,所以第一节点P1处的电平在充电周期结束后的电压Vpl为公式(2); [0091] When the frequency-divided signal fb goes high, the charging is completed, the first switching transistor Ml is turned off, the level of the first point P1 of the voltage Vpl the charge cycle as Equation (2);

[0092] [0092]

Figure CN103066952BD00191

[0093] 式中,Iref为参考电流,Tb为频率信号的分频信号fb的周期,Cc为第一充放电电容,Cpl为第一节点的寄生电容。 [0093] wherein, Iref is a reference current, Tb is the period of the frequency-divided signal fb frequency signal, Cc is the capacitance of the first charge and discharge, Cpl the parasitic capacitance of the first node.

[0094] 在电荷重新分配阶段中:在下一个充电阶段到来之前,脉冲信号CLK1进入高电平,使得第一充电管M19导通,第一充放电容Cc所充的电荷在第一充放电容Cc和输出电容C1之间重新分配,其中,第一防串扰管M20的主要作用是为了降低第一充电管M19的电荷注入效应,抑制时钟馈通效应。 [0094] In the charge redistribution stages: a charging stage before the arrival of the next pulse signal CLK1 goes high, the charging tube such that the first M19 is turned on, the first charge and discharge electric charge charged in the capacitance Cc discharge capacity in the first charge Cc and output redistributed between capacitor C1, wherein the first major role in preventing crosstalk tube M20 is to reduce the effect of the first charge injection charging tube M19 to suppress the clock feed-through.

[0095]在放电阶段中:第一脉冲信号CLK1触发产生第二脉冲信号CLK2进入高电平,使得第一放电管M13导通,P1点电荷通过第一放电管M13放电,为了将第一充放电容Cc彻底放电,脉冲信号CLK2触发脉冲信号CLK3,从而将P1点的残留电荷通过第三放电管M15再次放掉,之后P1点的电荷降为零。 [0095] In the discharge phase: generating a first pulse of the second pulse signal CLK1 triggers signal CLK2 goes high, M13 is turned on so that the first discharge, charges through the first discharge point Pl M13 discharge, to the first charge the discharge capacitance Cc is completely discharged, the trigger pulse signal CLK2 CLK3 is a pulse signal, so that the residual charge point P1 through the third discharge M15 let go again, after zero charge point P1.

[0096] 在预充电阶段中:第三脉冲信号CLK3触发产生脉冲信号CLK4,第一寄生电容消除电路中P3在脉冲信号CLK2为高电平时将P点预先充电到参考电压Vref,P3点的寄生电容等于P1点的寄生电容,即为Cpl,则P3点的电荷为Vref*Cpl。 [0096] In the pre-charge phase: generating a third pulse signal CLK3 pulse trigger signal CLK4, the first parasitic capacitance cancellation circuit in the pulse signal P3 is high CLK2 point P to the precharge reference voltage Vref, the parasitic point P3 a parasitic capacitance equal to the capacitance of the point P1, is the charge of Cpl, the point P3 is Vref * Cpl. 脉冲信号CLK4使得第十六充放MOS管M16导通,P3点的电荷通过第十六充放MOS管M26在Cc和寄生电容之间重新分配,得到寄生电容产生的低电压Vcpl: CLK4 pulse signal such that the charge and discharge sixteenth MOS transistor M16 is turned on, charge redistribution point P3 between the parasitic capacitance Cc and the discharge by a sixteenth MOS transistor M26 charge, to obtain a low voltage Vcpl parasitic capacitance generated:

[0097] [0097]

Figure CN103066952BD00192

[0098] 那么,在下一个脉冲信号低电平到来时,P1点的电压已经充电到Vcpl,这样,在相同的频率下,P1点在每次完成充电后的电压为: [0098] Then, when the arrival of the next pulse signal is low, the charging voltage of the point P1 has to Vcpl, so that, at the same frequency, the voltage at the point P1 after the completion of each charge:

[0099] [0099]

Figure CN103066952BD00193

[0100] 同样,第二转化电路151具有相同的工作过程,也可以得到,则P2点在每次充电完成后的电压为Vp2 : [0100] Also, the second conversion circuit 151 have the same working process can be obtained, then the voltage at the point P2 after completion of each charge Vp2:

[0101] [0101]

Figure CN103066952BD00194

[0102] 由于第一充放电容Cc和第二充放电容Cel的电容相同,故P1点和P2点的寄生电容相同,而Vpl和Vp2为两个相位相反的信号。 [0102] Since the first and second charge and discharge capacitance Cc same charging and discharging the capacitance Cel of the capacitor, and therefore the same parasitic capacitance and the point P2 to P1, and Vpl and Vp2 of two opposite phase signals.

[0103] 上述充电-电荷转移-放电过程-预充电经过M个周期后,M为正整数,频率-电压转化电路输出的反馈电压Vout: [0103] The charge - transferring charge - discharge process - after a precharge cycle of M, M is a positive integer, the frequency - converted feedback voltage Vout of the voltage output circuit:

[0104] [0104]

Figure CN103066952BD00195

[0105]此外,在第一节点P1和第二节点P2充电后,输出电平与其电压的最大误差为: [0105] Further, after the first point P1 and second point P2 charge, the maximum output level of the error voltage therewith to:

[0106] [0106]

Figure CN103066952BD00196

[0107] 因此,当M足够大时,S卩可以认为最终实现Vout=Vpl,那么则反馈电压Vout如公式(7)所示: [0107] Thus, when a sufficiently large M, S can be considered ultimately Jie Vout = Vpl, then the feedback voltage Vout as shown in equation (7):

[0108] [0108]

[0109] 当差分放大电路12的增益足够大,环路稳定时,则Vout=Vref。 [0109] When the gain of differential amplifying circuit 12 is sufficiently large loop stability, the Vout = Vref. ronoi由公才 ronoi only by the public

Figure CN103066952BD00201

锃.由孤右枯术没有消除寄生电容时, Zeng. Right from the lone dry when surgery does not eliminate the parasitic capacitance,

[0113] 由式(1)、⑵可得, [0113] by the formula (1), ⑵ available,

[0114] [0114]

Figure CN103066952BD00202

卩内置振荡电路的频率输出跟电阻(Rp+Pn)、第一充放电容Cc以及寄生电容Cpl相关,输出频率的温度特性相关,不仅跟电阻(Rp+Pn)和电容Cc相关,而且受寄生电容Cpl的温度特性的影响,因此稳定性较差。 Jie output frequency oscillation circuit with a built-resistance (Rp + Pn), and a first charge and discharge the parasitic capacitance Cpl capacitance Cc correlation, the temperature characteristic of the output frequency associated, not only with the resistance (Rp + Pn) and capacitance Cc relevant, but also by the parasitic Effect of temperature characteristics of capacitance Cpl therefore less stable.

[0115] 相比于现有技术,本发明所述内置振荡电路增加了第一寄生电容消除电路和第二寄生电容消除电路之后, [0115] Compared to the prior art, the present invention is to increase the built-in oscillation circuit parasitic capacitance cancellation circuit of the first and second parasitic capacitances canceling circuit after

Figure CN103066952BD00203

[0122] 又fout=M*fb,贝丨」输出频率 [0122] and fout = M * fb, Tony Shu "output frequency

[0123] [0123]

Figure CN103066952BD00204

当所述频率-电压转化电路15接收的为多倍分频器14的分频信号时,则M为所述多倍分频器的分频倍数,当所述频率-电压转化电路15直接接收所述环形振荡器13的频率信号时,则公式中M=l,即 When the frequency - voltage conversion circuit 15 is a multiple of the received pilot signal frequency divider 14, a multiple of the frequency of said M multiple frequency divider when the frequency - voltage conversion circuit 15 directly receives when the frequency of the ring oscillator 13 signal, the equation M = l, i.e.,

Figure CN103066952BD00205

[0124] 由此分析可见,本发明所述内置振荡电路的输出频率fout与电源电压变化无关, 输出频率fout的温度电压工艺(PVT)特性由电阻(Rp+Pn)和电容Cc的PVT特性决定。 [0124] Accordingly analysis shows that, irrespective of the output frequency fout of the present invention, the power supply voltage of the built-in oscillation circuit, the output frequency fout of the voltage process temperature (PVT) characteristics of (Rp + Pn) PVT properties and resistance determined by the capacitance Cc . 因此,如果电阻(Rp+Rn)和Cc都有较小的温度系数,则环形振荡器VC0的输出信号频率也将具有较小的温度系数。 Therefore, if the resistance (Rp + Rn) and has a small temperature coefficient Cc, the output signal frequency of the ring oscillator VC0 will also have a small temperature coefficient.

[0125] 图9为本发明一实施例中内置振荡电路中环形振荡器的示意图。 [0125] FIG. 9 is a schematic diagram of the built-in oscillation circuit of a ring oscillator embodiment of the present invention. 如图9所示,所述环形振荡器包括多级压控振荡器(VC0),形成级联的差分电路,在本实施例中,包括4级压控振荡器形成4级级联差分电路,所述控制电压Vctr控制4个压控振荡器控制整个环形振荡器的输出频率fout。 9, the multi-stage ring oscillator comprises a voltage controlled oscillator (VC0), cascaded differential circuits are formed, in the present embodiment, the voltage controlled oscillator comprising four differential circuit formed 4-tiered cascade, Vctr controls the control voltage VCO 4 controls the output frequency fout of the entire ring oscillator. 本发明所述环形振荡器13是便于集成的环形振荡器,其输出频率fout受控制电压Vctr控制,随着控制电压Vctr的减少频率增加。 The ring oscillator 13 of the present invention is to facilitate the integration of the ring oscillator, the output frequency fout is controlled by a control voltage Vctr, reduce the frequency as the control voltage increases Vctr. 从而通过选择环形振荡器结构和通过适当的参数设计,环形振荡器13在不同温度下具有可能工作在相同的频率。 So that by proper design parameters, the ring oscillator 13 may work with different temperatures by selecting a ring oscillator structure and at the same frequency. 其中,环形振荡器13的延时单元采用正反馈技术来调节延迟单元的延迟时间,从而改变电路的输出频率。 Wherein, the ring oscillator unit 13 uses the delay time of the delay positive feedback techniques to adjust the delay unit so as to change the output frequency of the circuit.

[0126] 图10为本发明一实施例中内置振荡电路中多倍分频器的示意图。 [0126] FIG. 10 is a schematic diagram of the built-in oscillation circuit to a multiple of the frequency divider embodiment of the present invention. 如图10所示, 所述多倍分频器12将环形振荡器13的输出频率fout进行分频,并产生占空比为50 %的输出分频后的频率信号fb。 10, the frequency divider 12 times the ring oscillator output frequency fout 13 is divided down, and the duty cycle is generated after a frequency signal fb 50% of the output divider. 在特定的工艺下,要得到较高的输出频率,频率_电压转化电路15中的充放电容充放电的电路性能会受到影响,所以通过在负反馈校正环路中增加多倍分频器12,使得频率-电压转化电路15中的充放电容的开关工作频率工作在分频后的频率信号fb之后,从而保证频率-电压转化电路15的性能。 Under certain process, to obtain higher output frequencies, a frequency voltage conversion circuit 15 _ the charge and discharge of capacitor charge and discharge circuit performance will be affected, so by increasing the negative feedback correction loop divider 12 times , so that the frequency - voltage conversion circuit 15 in the charging and discharging of capacitor switching operation frequencies after the frequency fb after the frequency division signal, thereby ensuring a frequency - voltage conversion circuit 15 of the performance. 在本实施例中,多倍分频器12包括多个级联的两倍分频器,例如包括n个2分频器,则M=2n,其中M为多倍分频器12的分频倍数。 In the present embodiment, a multiple of the frequency divider 12 comprises a plurality of cascaded frequency dividers twice, for example, includes n frequency divider 2, then M = 2n, where M is a sub-multiple of a frequency divider 12 multiple. 其中,所述两倍分频器可以由一个D触发器和一个反相器。 Wherein, the two times the frequency divider may consist of a D flip-flops and an inverter.

[0127] 此外,结合图3所示,所述差分放大电路12包括第一运算放大器A1、电阻R1和电容C0,所述电阻R1和电容C0主要用于去除耦合噪声,并提高环路的稳定性。 [0127] Further, in conjunction with FIG. 3, the differential amplifier circuit 12 includes a first operational amplifier A1, resistor R1 and capacitor C0, capacitor C0 and the resistor R1 is coupled mainly used to remove noise, and improve the stability of the loop sex. 第一运算放大器A1的正向输入端接参考电压Vref,电阻R1的一端接反馈电压Vout,另一端接第一运算放大器A1的负相输入端和电容C0的一端,电容C0的另一端接第一运算放大器A1的输出端。 A first operational amplifier A1, the positive input terminal of the reference voltage Vref, the resistor R1 is a feedback voltage Vout of termination, the other end of the negative first operational amplifier A1 and the inverting input terminal of one end of the capacitor C0 and the other end of the capacitor C0 an output terminal of the operational amplifier A1. 第一运算放大器A1的输出端输出控制电压Vctr至环形振荡器13的输入端。 A first output terminal of the operational amplifier A1 Vctr control voltage to the input of the ring oscillator 13.

[0128] 此外,现有技术中的晶振产生电路需要在片外设置晶振,并利用晶振产生振荡,因此成本较高,并且现有技术的晶振产生电路的频率精度虽然可以达到lppm~lOOppm,但其频率范围只能在lKHz~100MHz。 [0128] In addition, the prior art oscillator generating circuit needs to be provided off-chip crystal, using the crystal oscillation, and therefore high cost, the prior art crystal and produce a frequency accuracy of the circuit can be achieved while lppm ~ lOOppm, but only in the frequency range 100MHz lKHz ~. 相比于现有技术,本发明所述的内置振荡器可以全部设置在片上,采用环形振荡器控制产生频率,因此其大大节约了成本,并且通过设置多倍分频器可以大大提高频率范围,达到10KHz-450MHz广泛适用于各种产品例如,频率范围在27MHZ~40MHZ的玩具遥控设备,频率范围315MHz或433MHZ的无线控制设备以及频率范围在38KHz的红外遥控设备等设备中。 Compared to the prior art, the internal oscillator of the present invention may all be provided on the sheet, using the ring oscillator generates a frequency control, so that significant cost savings, and the frequency range can be greatly improved by providing a multiple frequency divider, reaches 10KHz-450MHz widely applied to various products e.g., a frequency range 27MHZ ~ 40MHZ toy remote control device, the control apparatus and the radio frequency range of the frequency range of 315MHz or 433MHZ 38KHz infrared remote control devices and the like in the apparatus.

[0129] 综上所述,本发明所述内置振荡电路采用负反馈闭环路形式,利用频率-电压转化方式,使内置振荡电路能够在芯片中全部集成,省略了需要外部额外设置的晶振,节约了工艺成本,并且通过将环形振荡器产生的振荡频率转化为反馈电压,并与所述参考电压进行比较,然后将比较结果反馈到环形振荡器的控制端,改变环形振荡器的频率,从而通过对输出频率的偏差进行补偿,减少了参考电流接输入点的寄生电容对于频率-电压转化电路的影响,从而使环路稳定输出低温漂的工作频率,并提高了振荡器的频率精度。 [0129] In summary, the present invention is a built-in oscillation circuit using negative feedback in the form of a closed loop, with a frequency - voltage conversion mode, so that the built-in oscillation circuit can be fully integrated in a chip, the need for external crystal omitted additionally provided, saving process costs, and the oscillation frequency of the ring oscillator is generated by converting the feedback voltage, and compared with the reference voltage, then the comparison result fed back to the control terminal of the ring oscillator to change the frequency of the ring oscillator, so that by output frequency deviation is compensated, the reference current is reduced parasitic capacitance to the input point of the frequency - voltage conversion circuit Effect of the loop so that a stable output temperature drift of the operating frequency, and improves the frequency accuracy of the oscillator.

[0130] 进一步的,通过在所述频率-电压转化电路通过引入寄生消除电路,避免了因为所述频率-电压转化电路在第一节点和第二节点处引入的引入M0S管寄生电容,故在充放电的过程中,降低了对温度的敏感性,避免了寄生电容对内置振荡电路的影响,提高了频率-电压转化电路的温度特性,进而改善了整个系统的温度特性。 [0130] Further, by the frequency - voltage conversion circuit by introducing parasitic cancellation circuit, is avoided because of the frequency - voltage conversion circuit is introduced is introduced at a first point and a second point M0S tube parasitic capacitance, so in during charging and discharging, less sensitive to temperature, to avoid the influence of parasitic capacitance of the built-in oscillation circuit, increases the frequency - temperature characteristic of the voltage conversion circuit, thereby improving the temperature characteristics of the entire system.

[0131] 进一步的,所述内置振荡电路中,所述基本电流产生电路通过可修调电阻的低位细调和多路可修调镜像电路的高位控制以及高位低位频率选择,从而能够通过修调位修正方法对输出频率的工艺偏差,达到〇. 1 %的频率修调精度,并且能够覆盖整个修调范围,没有断节。 [0131] Further, the built-in oscillation circuit, the base current generating circuit via a low resistance trimming fine and multiplexer control can override the upper mirror circuit and the high-low frequency selection is possible by trimming bits a method for correcting the frequency deviation of the output of the process, to achieve square. 1% accuracy frequency trim, trim and can cover the entire range, without breaking section.

[0132] 所述内置振荡电路不仅在工艺,温度偏差和电源电压偏差的情况下有较高的稳定性,输出一个稳定的时钟信号,而且其输出频率范围广。 [0132] The built-in oscillation circuit not only a higher stability, a stable clock signal output in the case of process, temperature variation and supply voltage variation, and its wide range of output frequencies.

[0133]虽然本发明已以较佳实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,因此本发明的保护范围当视权利要求书所界定者为准。 [0133] While the present invention has been disclosed above by the preferred embodiments, they are not intended to limit the present invention, any skilled in the art having ordinary knowledge in the present invention without departing from the spirit and scope, it is intended that the alterations and modifications, and therefore the scope of the invention as defined by the appended claims will their equivalents.

Claims (41)

  1. 1. 一种内置振荡电路,包括基本电流产生电路、环形振荡器、频率-电压转化电路以及差分放大电路; 所述基本电流产生电路包括第一运算放大器、第一放大管、可修调电阻和镜像电路,所述第一运算放大器接收一参考电压,经所述可修调电阻修调后由第一放大管输出一中间电流,所述中间电流经所述镜像电路输出参考电流; 所述环形振荡器产生频率信号; 所述频率-电压转化电路包括开关管模块、充放电容和输出电容,所述开关管模块接收所述参考电流和频率信号,并在所述频率信号的控制下,进行使所述参考电流对所述充放电容进行充电、以及在充放电容和输出电容之间进行电荷重新分配和对所述充放电容进行放电的过程,以使所述输出电容输出反馈电压; 所述差分放大电路比较所述反馈电压和所述参考电压并产生控制电压,所述控制电压对 A built-in oscillation circuit, comprising a base current generating circuit, a ring oscillator, the frequency - voltage conversion circuit and a differential amplifier circuit; said base current generating circuit includes a first operational amplifier, a first amplifier tube, can trim resistance and mirror circuit, the first operational amplifier receives a reference voltage, the resistance after the trimming can trim output by the first amplifying an intermediate tube current, the current through said intermediate reference current mirror circuit output; the ring the oscillator generates a frequency signal; a frequency - voltage conversion circuit comprises a switch module, and output capacitors charge and discharge, receiving the reference frequency signal and a tube current of the switching module, and under the control of the frequency signal, for the reference current to charge and discharge the capacitor to charge and discharge electric charge between the charge redistribution and output capacitors and the charge-discharge process of discharging the capacitor, the output capacitor so that the output voltage feedback; the differential amplifying circuit compares the feedback voltage and the reference voltage and generates a control voltage, the control voltage 述环形振荡器的频率信号进行反馈校正,直至频率信号稳定输出; 其特征在于,所述频率-电压转化电路还包括脉冲信号产生电路和寄生电容消除电路,所述脉冲信号产生电路根据所述频率信号产生多个控制开关管模块的脉冲信号,所述寄生消除电路包括第一寄生消除电路和第二寄生消除电路,所述充放电容包括第一充放电容和第二充放电容,所述开关管模块包括第一开关管、第一充电管、第一放电管、第二开关管、第二充电管、第二放电管、第一防串扰管和第二防串扰管; 所述第一开关管的控制端接所述频率信号、第一连接端接所述参考电流、第二连接端接第一节点,所述第二开关管的控制端接所述频率信号的反相信号、第一连接端接所述参考电流、第二连接端接第二节点, 所述第一充放电容一端接所述第一节点、另一端接地,所述第二充放 Said ring oscillator frequency signal feedback correction until a stable output frequency signal; wherein said frequency - voltage conversion circuit further comprises a pulse signal generating circuit and parasitic capacitance cancellation circuit, the pulse signal generating circuit according to the frequency signal generating a plurality of pulse signals control switch module, the parasitic cancellation circuit comprises a first and second parasitic parasitic eliminating circuit eliminating circuit, the charge and discharge capacitor comprises a first capacitor and a second charge and discharge capacitor charging and discharging, the a first switch module comprises a switch, a first charging pipe, a first discharge tube, a second switch, a second charging pipe, a second discharge tube, the first tube and the second cross-talk preventing crosstalk prevention tube; the first switch control terminal of the frequency signal, a first end connected to said reference current, a second end connected to a first node, said second switch control terminal inverted signal of said frequency, the first a connecting end of said reference current, a second end connected to the second node, a capacitor charge and discharge said first end of said first node, the other end, the second charge-discharge 容一端接所述第二节点、另一端接地, 所述第一充电管的控制端接脉冲信号,两连接端分别接第一节点和输出电容之间,所述第二充电管的控制端接脉冲信号,两连接端分别接第二节点和输出电容之间,所述第一放电管的控制端接脉冲信号,两连接端分别接地和第一节点,所述第二放电管的控制端接脉冲信号,两连接端分别接地和第二节点, 所述第一寄生电容消除电路输入端接所述脉冲信号、输出端接所述第一节点,所述第二寄生消除电路输入端接所述脉冲信号、输出端接所述第二节点; 所述第一防串扰管的控制端接脉冲信号、两连接端连接于所述第一充电管和输出电容之间,所述第二防串扰管的控制端接脉冲信号、两连接端连接于第二充电管和输出电容之间。 Receiving one end of said second node, the other end, the pulse signal of the first control terminal of the charging tube, the capacitance between the first node and the output terminals are connected to two connections, the control terminal of the second charge tube pulse signal, two connection terminals respectively connected between the second node and the output capacitor, the discharge control terminal of the first pulse signal, and two ground terminals are connected to a first node, a control terminal of the second discharge tube pulse signal, and two ground terminals are connected to the second node, the first parasitic capacitance cancellation circuit the pulse signal input terminal, an output end of said first node, said second input terminal of said parasitic cancellation circuit pulse signal output end of said second node; said control terminal of the first pulse signal crosstalk prevention pipe, two connecting terminal connected between the first output capacitor and the charging tube, the second tube preventing crosstalk the pulse signal control terminal, two connecting terminal connected between the second output capacitor and the charging tube.
  2. 2. 如权利要求1所述的内置振荡电路,其特征在于,所述环形振荡器的频率信号稳定输出时,所述频率信号的值与修调电阻的电阻值和充放电容的电容值有关。 2. Built-in oscillation circuit according to claim 1, wherein the frequency of the signal of the ring oscillator is stable output, the frequency and the resistance value of resistor trimming signal and the capacitance of the capacitor charge and discharge of the relevant .
  3. 3. 如权利要求2所述的内置振荡电路,其特征在于,所述内置振荡器的输出频率为: 3. The built-in oscillation circuit according to claim 2, characterized in that the output frequency of the oscillator is built:
    Figure CN103066952BC00021
    其中,fout为所述环形振荡器的输出频率,Cc为所述充放电容的电容值,(Rp+Rn)为所述可修调电阻的电阻值,K为比例系数。 Wherein, fout is the output frequency of the ring oscillator, Cc is the capacitance value of the charge and the discharge capacity, (Rp + Rn) of said trim resistance of the resistor, K is a proportionality factor.
  4. 4. 如权利要求1所述的内置振荡电路,其特征在于,在所述基本电流产生电路中,所述第一运算放大器的两输入端分别接所述参考电压和第一放大管的第一连接端、输出端接所述第一放大管的控制端;所述可修调电阻一端接地、另一端接所述第一放大管的第一连接端,所述镜像电路的输入端接所述第一放大管的第二连接端、输出端输出所述参考电流。 4. The first built-in oscillation circuit according to claim 1, characterized in that said base current generating circuit, two input terminals of said first operational amplifier are respectively connected to the reference voltage and the first amplifier tube connecting end, an output end of said control terminal of the first amplifier tube; said trimming resistor is grounded at one end, a first end connected to the other end of the first amplifier tube, said input terminal of said mirror circuit amplifying the first tube second connecting end, an output terminal of the reference current.
  5. 5. 如权利要求4所述的内置振荡电路,其特征在于,所述镜像电路包括第一镜像输出管,所述第一镜像输出管的控制端接所述第一放大管的控制端、所述第一镜像输出管的第一连接端输出所述参考电流、所述第一镜像输出管的第二连接端接一电源电压。 5. Built-in oscillation circuit according to claim 4, characterized in that said mirror circuit comprises a first mirror output transistor, the control terminal of the first mirror control terminal of the first outlet tube amplifier tube, the a first end of said first connecting tube output mirror the reference current output, a second output connected to the first mirror tube end a supply voltage.
  6. 6. 如权利要求4所述的内置振荡电路,其特征在于,所述镜像电路包括第一镜像输入管、第二镜像输入管、第一镜像输出管和第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、所述第一镜像输入管的第二连接端接一电源电压,所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,所述第一镜像输出管的控制端接所述第一镜像输入端的控制端、所述第一镜像输出管的第一连接端接所述第二镜像输出管的第二连接端,所述第一镜像输出管的第二连接端接所述电源电压,所述第二镜像输出管的控制端接所述第二镜像输入管的控制端,所述第二镜像输出管的第一连接端输出所述参考电流、所述第二镜像输出管的第二连接端与一第一镜像输出管 6. The oscillator circuit of claim 4, wherein the built-in second mirror inlet tube, outlet tube first mirror and second mirror output tube, characterized in that said mirror circuit comprises a first input mirror tube, said first mirror control terminal of the second amplifying a first input connected to the tube end of the tube, a second connection terminal connected to a first end of the first mirror of the second mirror input tube inlet tube, said first mirror a second inlet tube connected to a termination power supply voltage, a second connection terminal connected to a second end of said second tube of the first input image amplifier tube, the control terminal of the first output mirror tube a second end connected to said second power supply terminal connected to a control terminal of the first mirror input terminal, a first end connected to said output of said first mirror of the second mirror tube of the outlet tube, the outlet tube of the first mirror a first end connected to the mirror control terminal of the second voltage input end of said tube, said second mirror output tube, said second tube output mirror the reference current output, the second output mirror tube connecting a second end of the first output mirror tube 的第一连接端连接。 A first connector terminal.
  7. 7. 如权利要求4所述的内置振荡电路,其特征在于,所述镜像电路为多路可修调镜像电路,所述可修调电阻对所述参考电流实现低位频率偏差调节,所述多路可修调镜像电路实现高位低位频率选择以及所述参考电流实现高位频率偏差调节。 7. Built-in oscillation circuit according to claim 4, characterized in that said mirror circuit is a multiple, trimming mirror circuit, said trimming resistor of the reference current is adjusted to achieve the low frequency deviation, the plurality trimming mirror circuit path can achieve high low frequency selector and said reference current is adjusted to achieve high frequency deviation.
  8. 8. 如权利要求7所述的内置振荡电路,其特征在于,所述可修调镜像电路为共源共栅电流镜结构。 The oscillation circuit built as claimed in claim 7, wherein said trimming circuit is a common image source cascode current mirror configuration.
  9. 9. 如权利要求8所述的内置振荡电路,其特征在于,所述多路可修调镜像电路包括第一镜像输入管、第二镜像输入管、多个第一镜像输出管和多个第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、所述第一镜像输入管的第二连接端接一电源电压,所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,每一所述第一镜像输出管的控制端均接所述第一镜像输入管的控制端、每一所述第一镜像输出管的第二连接端接所述电源电压,每一所述第二镜像输出管的控制端均接所述第二镜像输入管的控制端,所述第二镜像输出管的第一连接端相连后输出所述参考电流,每一所述第二镜像输出管的第二连接端与一第一镜像输出管的第一连接端连接。 9. Built-in oscillating circuit according to claim 8, wherein said multiplexer circuit may include a first trimming image tube input image, a second image inlet tube, a plurality of first mirror and a plurality of outlet tube a second control terminal connected to a first end of two mirror outlet tube, the inlet tube of the first mirror of the first amplifier tube, a first end connected to the first mirror of the second mirror input tube inlet tube two connecting end, a second input connected to the first mirror tube of a termination power supply voltage, a second connection terminal connected to a second end of said second tube of the first input mirror amplifier tube, each of said the mirror control terminal of the first outlet tube are connected to the control terminal of the first mirror input tube, each of said first mirror tube output end of said second supply voltage connection, each of the second output mirror tube are connected to a control terminal of the control input terminal of the second mirror tube, said first end connected to the reference current output is connected to the second mirror output pipes, each of the second connection end of the outlet tube of the second mirror a first connecting terminal connected to the first mirror output tube.
  10. 10. 如权利要求9所述的内置振荡电路,其特征在于,所述内置振荡电路包括M个第一镜像输出管,所述基本电流产生电路接收一多位控制信号,所述多位控制信号包括频率选择位、镜像电路调节位和电阻调节位,所述频率选择位控制N个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围选择,所述镜像电路调节位控制L个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围内粗调,所述电阻调节位控制所述可修调电阻的电阻值以实现频率范围内精调,其中,N、L及M均为正整数,所述N个第一镜像输出管和L个第一镜像输出管均为不同的第一镜像输出管,且N+L = M。 10. The built-in oscillation circuit according to claim 9, wherein said built-in oscillation circuit comprises M first mirror output transistor, the base current generating circuit receives a multi-bit control signal, the multi-bit control signal includes a frequency select bits, adjusting the mirror circuit and resistance adjustment bit position, the bit frequency selection control of the proportional value of the N output first mirror tube and the first tube to achieve a mirror image input selected frequency range, said mirror circuit adjusting the proportion of the L-bit control value of the first output mirror tube and the first tube to achieve a mirror image input coarse frequency range, the control bit of said resistance adjusting trim resistance of the resistor to achieve frequency range the fine adjustment, where, N, L and M are both positive integers, and the L output of the first mirror of the first mirror transistor are different from said N output first mirror tube outlet tube, and N + L = M.
  11. 11. 如权利要求1所述的内置振荡电路,其特征在于,所述开关管模块还包括第三放电管和第四放电管,所述第三放电管的控制端接脉冲信号、两连接端接所述第一充放电容和地之间,所述第四放电管的控制端接脉冲信号、两连接端接所述第二充放电容和地之间。 11. Built-in oscillation circuit according to claim 1, wherein the switch module further comprises a third tube and a fourth discharge tube discharge, the discharge control terminal of the third pulse signal, the two connecting ends connected between the first charge and discharge capacity, the discharge control terminal of the fourth pulse signal, a second end of said two charging and discharging are connected between the capacitor and ground.
  12. 12. 如权利要求11所述的内置振荡电路,其特征在于,所述第一开关管、第一充电管、 第一放电管、第二开关管、第二充电管、第二放电管、第一防串扰管、第二防串扰管、第三放电管和第四放电管接收不同的脉冲信号,所述第一开关管、第一充电管、第一放电管、第二开关管、第二充电管、第二放电管、第一防串扰管、第二防串扰管、第三放电管和第四放电管均为MOS管。 12. The built-in oscillation circuit according to claim 11, wherein said first switch, a first charging pipe, a first discharge tube, a second switch, a second charging pipe, a second discharge tube, the first a crosstalk prevention tube, a second tube preventing crosstalk, the third and fourth discharge different pulse discharge signal reception, the first switch, a first charging pipe, a first discharge tube, a second switch, a second the charging tube, a second discharge tube, the first crosstalk prevention tube, a second tube preventing crosstalk, the third and fourth discharge are discharge MOS transistor.
  13. 13. 如权利要求1所述的内置振荡电路,其特征在于,所述第一寄生消除电路和所述第二寄生消除电路的结构相同。 13. Built-in oscillation circuit according to claim 1, wherein said first and said second cancellation circuit parasitic eliminate parasitic same circuit configuration.
  14. 14. 如权利要求13所述的内置振荡电路,其特征在于,所述第一寄生消除电路具有第三节点,所述第三节点的寄生电容与所述第一节点的寄生电容相等;所述第一寄生消除电路包括第十一MOS管至第十七MOS管,所述第十一MOS管的源极和栅极相接、漏极接所述第三节点,所述第十三MOS管的栅极接脉冲信号、漏极接所述第三节点、源极接所述第十二MOS管的源极,所述第十二MOS管的栅极接脉冲信号、源极和漏极相接并接所述参考电压, 所述第十四MOS管和第十五MOS管的漏极均接所述第三节点、栅极和源极均接地,所述第十六MOS管的漏极接所述第三节点、栅极接脉冲信号、源极接所述第十七MOS管的源极,所述第十七MOS管的栅极接所述脉冲信号、源极和漏极相接并接所述第二节点。 14. The built-in oscillating circuit according to claim 13, wherein said first cancellation circuit having a parasitic third node, a parasitic capacitance and a parasitic capacitance equal to the first node of the third node; the a first cancellation circuit comprises a parasitic MOS transistor of the eleventh to seventeenth MOS transistor, the source and gate contact, a drain connected to said third node, said eleventh MOS transistor and said thirteenth MOS transistor a gate connected to a pulse signal, a drain connected to the third node, a source connected to the source of the twelfth MOS transistor, a gate of the twelfth MOS transistor is connected to a pulse signal, a source and a drain phase and a drain connected to the reference voltage connected to the drain of the fourteenth and fifteenth MOS transistors each MOS transistor is connected to the third node, a source grounded and a gate, said sixteenth MOS transistor said third contact point, then a gate pulse signal, a source connected to the source of the seventeenth MOS transistor, a gate connected to said pulse signal seventeenth MOS transistor, the source and drain contact and access the second node.
  15. 15. 如权利要求13所述的内置振荡电路,其特征在于,在所述频率-电压转化电路中, 所述第二寄生消除电路具有第四节点,所述第四节点的寄生电容与所述第二节点的寄生电容相等;所述第二寄生消除电路包括第十八MOS管至第二十四MOS管,所述第十八MOS管的源极和栅极相接、漏极接所述第四节点,所述第二十MOS管的栅极接脉冲信号、漏极接所述第四节点、源极接所述第十九MOS管的源极,所述第十九MOS管的栅极接脉冲信号、源极和漏极相接并接所述参考电压,所述第二十一MOS管和第二十二MOS管的漏极均接所述第四节点、栅极和源极均接地,所述第二十三MOS管的漏极接所述第四节点、栅极接脉冲信号、 源极接所述第二十四MOS管的源极,所述第二十四MOS管的栅极接所述脉冲信号、源极和漏极相接并接所述第二节点。 15. Built-in oscillating circuit according to claim 13, wherein, in the frequency - voltage conversion circuit, the cancellation circuit having a second parasitic fourth node, the fourth node and the parasitic capacitance is equal to the parasitic capacitance of the second node; said second cancellation circuit comprises a parasitic MOS transistor eighteenth through twenty-fourth MOS transistor, the source of the eighteenth MOS transistor and a gate contact, said drain contact a fourth node, a gate connected to the pulse signal twentieth MOS transistor, a drain connected to the fourth node, a source connected to the source of the nineteenth MOS transistor, the gate of the MOS transistor nineteenth electrode connected to a pulse signal, and the source and drain contact connected to the reference voltage, the twenty-first and twenty-second MOS drain tube MOS transistor are connected to the fourth node, the gate and source are grounded, a drain connected to the fourth node of the twenty third MOS transistor, a gate connected to a pulse signal, a source connected to the source electrode of the twenty-fourth MOS transistor, the twenty-fourth MOS transistor a gate connected to said pulse signal, and the source and drain contact connected to the second node.
  16. 16. 如权利要求1所述的内置振荡电路,其特征在于,所述内置振荡电路还包括多倍分频器,所述多倍分频器设置于所述环形振荡器和频率_电压转化电路之间,所述多倍分频器对所述频率信号进行分频后,输出至所述频率-电压转化电路,以使所述频率-电压转化电路稳定工作。 16. Built-in oscillation circuit according to claim 1, wherein said oscillation circuit further comprises a multiple built-in frequency divider, a multiple frequency divider disposed in said ring oscillator and a voltage conversion circuit _ after between, the multiple of the frequency divider for dividing the frequency signal output to the frequency - voltage conversion circuit such that said frequency - voltage conversion circuit stability.
  17. 17. 如权利要求16所述的内置振荡电路,其特征在于,当所述频率信号稳定输出时,所述频率信号为: 17. The built-in oscillating circuit according to claim 16, wherein, when the stable output frequency signal, the frequency signal:
    Figure CN103066952BC00041
    其中,M为所述多倍分频器的分频倍数,fout为所述内置振荡器的输出频率,Cc为第一充放电容的电容值,(Rp+Rn)为基本电流产生电路的可修调电阻的电阻值,K为比例系数。 Wherein the circuit may be generated, M being a multiple of the frequency division multiple divider, fout is the output frequency of the oscillator built, Cc is the capacitance of the first charge and discharge capacity, (Rp + Rn) of the basic current trim resistance of the resistor, K is a proportionality factor.
  18. 18. 如权利要求16所述的内置振荡电路,其特征在于,所述多倍分频器包括多个级联的两倍分频器。 18. The built-in oscillating circuit according to claim 16, wherein said divider comprises a plurality of cascaded multiple times frequency divider.
  19. 19. 如权利要求1所述的内置振荡电路,其特征在于,所述差分放大电路包括第二运算放大器、电阻和电容,所述第二运算放大器的一输入端接所述参考电压、另一输入端通过所述电阻接所述反馈电压、输出端接所述环形振荡器,所述电容一端连接于所述第一运算放大器和所述电阻之间,另一端连接于所述第一运算放大器和所述环形振荡器之间。 19. The built-in oscillation circuit according to claim 1, wherein said differential amplifier circuit comprises a second operational amplifier, resistors and capacitors, said operational amplifier is an input end of said second reference voltage, the other between the voltage input terminal, an output end of said ring oscillator, said first operational amplifier is connected to one end of the capacitor and the resistor connected to the feedback via the resistor, and the other end connected to the first operational amplifier and between the ring oscillator.
  20. 20. 如权利要求1至19中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围在27MHZ~49MHZ的玩具遥控设备中。 20. Built-in oscillation circuit 1 to 19 according to any one of the preceding claims, characterized in that the built-in oscillation circuit is provided in the frequency range of the remote control device toys in the 27MHZ ~ 49MHZ.
  21. 21. 如权利要求1至19中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围在315MHz或433MHZ的无线控制设备中。 21. The built-in oscillation circuit 1 to 19 according to any one of the preceding claims, characterized in that the built-in oscillation circuit is provided in the frequency range of the radio control apparatus in the 315MHz or 433MHZ.
  22. 22. 如权利要求1至19中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围在38KHz的红外遥控设备中。 22. The built-in oscillation circuit 1 to 19 according to any one of the preceding claims, characterized in that the built-in oscillation circuit is provided in the frequency range of 38KHz infrared remote control device.
  23. 23. -种内置振荡电路,包括基本电流产生电路、环形振荡器、频率-电压转化电路以及差分放大电路; 所述基本电流产生电路包括第一运算放大器、第一放大管、可修调电阻和镜像电路,所述第一运算放大器接收一参考电压,经所述可修调电阻修调后由第一放大管输出一中间电流,所述中间电流经所述镜像电路输出参考电流; 所述环形振荡器产生频率信号; 所述频率-电压转化电路包括开关管模块、充放电容和输出电容,所述开关管模块接收所述参考电流和频率信号,并在所述频率信号的控制下,进行使所述参考电流对所述充放电容进行充电、以及在充放电容和输出电容之间进行电荷重新分配和对所述充放电容进行放电的过程,以使所述输出电容输出反馈电压; 所述差分放大电路比较所述反馈电压和所述参考电压并产生控制电压,所述控制电压对 23. - built-oscillation circuit, substantially comprising a current generating circuit, a ring oscillator, the frequency - voltage conversion circuit and a differential amplifier circuit; said base current generating circuit includes a first operational amplifier, a first amplifier tube, can trim resistance and mirror circuit, the first operational amplifier receives a reference voltage, the resistance after the trimming can trim output by the first amplifying an intermediate tube current, the current through said intermediate reference current mirror circuit output; the ring the oscillator generates a frequency signal; a frequency - voltage conversion circuit comprises a switch module, and output capacitors charge and discharge, receiving the reference frequency signal and a tube current of the switching module, and under the control of the frequency signal, for the reference current to charge and discharge the capacitor to charge and discharge electric charge between the charge redistribution and output capacitors and the charge-discharge process of discharging the capacitor, the output capacitor so that the output voltage feedback; the differential amplifying circuit compares the feedback voltage and the reference voltage and generates a control voltage, the control voltage 述环形振荡器的频率信号进行反馈校正,直至频率信号稳定输出; 其特征在于,所述频率-电压转化电路还包括脉冲信号产生电路,所述脉冲信号产生电路根据所述频率信号产生多个控制开关管模块的脉冲信号,所述开关管模块包括第一开关管、第一充电管、第一放电管和第一防串扰管;所述第一开关管的控制端接所述频率信号、第一连接端接所述参考电流、第二连接端接第一节点,所述充放电容一端接所述第一节点、另一端接地,所述第一充电管的控制端接脉冲信号,两连接端分别接第一节点和输出电容之间,所述第一放电管的控制端接脉冲信号,两连接端分别接地和第一节点,所述第一防串扰管的控制端接脉冲信号、两连接端连接于所述第一充电管和输出电容之间。 Said ring oscillator frequency signal feedback correction until a stable output frequency signal; wherein said frequency - voltage conversion circuit further comprises a pulse signal generating circuit, the pulse signal generation circuit generates a plurality of control signals based on the frequency pulse signal switch module, the switch module comprises a first switching transistor, a first charging pipe, a first discharge tube and the first anti-crosstalk; the first switch control terminal of the frequency signal, the first a connecting end of said reference current, a second end connected to a first node, one end of the capacitor charge and discharge the first node, the other end of the control pulse signal is terminated, the first charging pipe, connected to two ends respectively connected between the first node and the output capacitor, the discharge control terminal of the first pulse signal, and two ground terminals are connected to a first node, a control terminal of the first pulse signal crosstalk prevention pipe, two connecting terminal connected between the first output capacitor and the charging tube.
  24. 24. 如权利要求23所述的内置振荡电路,其特征在于,所述开关管模块还包括第三放电管,所述第三放电管的控制端接脉冲信号、两连接端接所述充放电容和地之间以对所述充电电容进行进一步放电。 24. The built-in oscillating circuit according to claim 23, wherein the switch module further includes a third discharge tube, the discharge control terminal of the third pulse signal, the charge and discharge the two connecting end in the further charging capacitor discharge between the capacitor and ground.
  25. 25. 如权利要求24所述的内置振荡电路,其特征在于,所述第一开关管、第一充电管、 第一放电管、第一防串扰管和第三放电管接收不同的脉冲信号,所述第一开关管、第一充电管、第一放电管、第一防串扰管和第三放电管均为MOS管。 25. The built-in oscillation circuit according to claim 24, wherein said first switch, a first charging pipe, a first discharge tube, the first tube and the third discharge preventing crosstalk receive different pulse signals, the first switch, a first charging pipe, a first discharge tube, the first tube and the third discharge preventing crosstalk are MOS transistor.
  26. 26. 如权利要求23所述的内置振荡电路,其特征在于,所述环形振荡器的频率信号稳定输出时,所述频率信号的值与修调电阻的电阻值和充放电容的电容值有关。 26. The built-in oscillating circuit according to claim 23, wherein the frequency of the signal of the ring oscillator is stable output, the frequency and the resistance value of resistor trimming signal and the capacitance of the capacitor charge and discharge of the relevant .
  27. 27. 如权利要求26所述的内置振荡电路,其特征在于,所述内置振荡器的输出频率为: 27. The built-in oscillating circuit according to claim 26, characterized in that the output frequency of the oscillator is:
    Figure CN103066952BC00051
    其中,fout为所述环形振荡器的输出频率,Cc为所述充放电容的电容值,(Rp+Rn)为所述可修调电阻的电阻值,K为比例系数。 Wherein, fout is the output frequency of the ring oscillator, Cc is the capacitance value of the charge and the discharge capacity, (Rp + Rn) of said trim resistance of the resistor, K is a proportionality factor.
  28. 28. 如权利要求23所述的内置振荡电路,其特征在于,在所述基本电流产生电路中,所述第一运算放大器的两输入端分别接所述参考电压和第一放大管的第一连接端、输出端接所述第一放大管的控制端;所述可修调电阻一端接地、另一端接所述第一放大管的第一连接端,所述镜像电路的输入端接所述第一放大管的第二连接端、输出端输出所述参考电流。 28. The built-in oscillating circuit according to claim 23, wherein said base current generating circuit, two input terminals of said first operational amplifier are respectively connected to said first reference voltage and a first amplifier tube connecting end, an output end of said control terminal of the first amplifier tube; said trimming resistor is grounded at one end, a first end connected to the other end of the first amplifier tube, said input terminal of said mirror circuit amplifying the first tube second connecting end, an output terminal of the reference current.
  29. 29. 如权利要求28所述的内置振荡电路,其特征在于,所述镜像电路包括第一镜像输出管,所述第一镜像输出管的控制端接所述第一放大管的控制端、所述第一镜像输出管的第一连接端输出所述参考电流、所述第一镜像输出管的第二连接端接一电源电压。 29. The built-in oscillating circuit according to claim 28, characterized in that said mirror circuit comprises a first mirror output transistor, the control terminal of the first mirror control terminal of the first outlet tube amplifier tube, the a first end of said first connecting tube output mirror the reference current output, a second output connected to the first mirror tube end a supply voltage.
  30. 30. 如权利要求28所述的内置振荡电路,其特征在于,所述镜像电路包括第一镜像输入管、第二镜像输入管、第一镜像输出管和第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、所述第一镜像输入管的第二连接端接一电源电压,所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,所述第一镜像输出管的控制端接所述第一镜像输入端的控制端、所述第一镜像输出管的第一连接端接所述第二镜像输出管的第二连接端,所述第一镜像输出管的第二连接端接所述电源电压,所述第二镜像输出管的控制端接所述第二镜像输入管的控制端,所述第二镜像输出管的第一连接端输出所述参考电流、 所述第二镜像输出管的第二连接端与一第一镜像输出 30. The built-in oscillating circuit according to claim 28, wherein said input mirror circuit comprises a first mirror transistor, the second image input pipe, first mirror and second mirror output pipe outlet tube, said first mirror control terminal of the second amplifying a first input connected to the tube end of the tube, a second connection terminal connected to a first end of the first mirror of the second mirror input tube inlet tube, said first mirror a second inlet tube connected to a termination power supply voltage, a second connection terminal connected to a second end of said second tube of the first input image amplifier tube, the control terminal of the first output mirror tube a second end connected to said second power supply terminal connected to a control terminal of the first mirror input terminal, a first end connected to said output of said first mirror of the second mirror tube of the outlet tube, the outlet tube of the first mirror a first end connected to the mirror control terminal of the second voltage input end of said tube, said second mirror output tube, said second tube output mirror the reference current output, the second output mirror tube connecting a second end of the first output mirror 管的第一连接端连接。 Connecting a first end of the tube is connected.
  31. 31. 如权利要求28所述的内置振荡电路,其特征在于,所述镜像电路为多路可修调镜像电路,所述可修调电阻对所述参考电流实现低位频率偏差调节,所述多路可修调镜像电路实现高位低位频率选择以及所述参考电流实现高位频率偏差调节。 31. The built-in oscillating circuit according to claim 28, characterized in that said mirror circuit is a multiple, trimming mirror circuit, said trimming resistor of the reference current is adjusted to achieve the low frequency deviation, the plurality trimming mirror circuit path can achieve high low frequency selector and said reference current is adjusted to achieve high frequency deviation.
  32. 32. 如权利要求31所述的内置振荡电路,其特征在于,所述可修调镜像电路为共源共栅电流镜结构。 Built-in 32. The oscillating circuit according to claim 31, wherein said trimming circuit is a common image source cascode current mirror configuration.
  33. 33. 如权利要求32所述的内置振荡电路,其特征在于,所述多路可修调镜像电路包括第一镜像输入管、第二镜像输入管、多个第一镜像输出管和多个第二镜像输出管,所述第一镜像输入管的控制端接所述第一放大管的第二连接端、所述第一镜像输入管的第一连接端接所述第二镜像输入管的第二连接端、所述第一镜像输入管的第二连接端接一电源电压, 所述第二镜像输入管的第二连接端接所述第一放大管的第二连接端,每一所述第一镜像输出管的控制端均接所述第一镜像输入管的控制端、每一所述第一镜像输出管的第二连接端接所述电源电压,每一所述第二镜像输出管的控制端均接所述第二镜像输入管的控制端, 所述第二镜像输出管的第一连接端相连后输出所述参考电流,每一所述第二镜像输出管的第二连接端与一第一镜像输出管的第一连接端连接 33. The built-in oscillation circuit 32 of the second mirror inlet tube, a plurality of first mirror and a plurality of outlet tube, characterized in that, the multiplexer may trimming circuit comprises a first mirror image input tube, a second control terminal connected to a first end of two mirror outlet tube, the inlet tube of the first mirror of the first amplifier tube, a first end connected to the first mirror of the second mirror input tube inlet tube two connecting end, a second input connected to the first mirror tube of a termination power supply voltage, a second connection terminal connected to a second end of said second tube of the first input mirror amplifier tube, each of said the mirror control terminal of the first outlet tube are connected to the control terminal of the first mirror input tube, each of said first mirror tube output end of said second supply voltage connection, each of the second output mirror tube are connected to a control terminal of the control input terminal of the second mirror tube, said first end connected to the reference current output is connected to the second mirror output pipes, each of the second connection end of the outlet tube of the second mirror a first connecting terminal connected to the output of a first mirror tube
  34. 34. 如权利要求33所述的内置振荡电路,其特征在于,所述内置振荡电路包括M个第一镜像输出管,所述基本电流产生电路接收一多位控制信号,所述多位控制信号包括频率选择位、镜像电路调节位和电阻调节位,所述频率选择位控制N个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围选择,所述镜像电路调节位控制L个所述第一镜像输出管与所述第一镜像输入管的比例值以实现频率范围内粗调,所述电阻调节位控制所述可修调电阻的电阻值以实现频率范围内精调,其中,N、L及M均为正整数,所述N个第一镜像输出管和L个第一镜像输出管均为不同的第一镜像输出管,且N+L = M。 34. The built-in oscillation circuit according to claim 33, wherein said built-in oscillation circuit comprises M first mirror output transistor, the base current generating circuit receives a multi-bit control signal, the multi-bit control signal includes a frequency select bits, adjusting the mirror circuit and resistance adjustment bit position, the bit frequency selection control of the proportional value of the N output first mirror tube and the first tube to achieve a mirror image input selected frequency range, said mirror circuit adjusting the proportion of the L-bit control value of the first output mirror tube and the first tube to achieve a mirror image input coarse frequency range, the control bit of said resistance adjusting trim resistance of the resistor to achieve frequency range the fine adjustment, where, N, L and M are both positive integers, and the L output of the first mirror of the first mirror transistor are different from said N output first mirror tube outlet tube, and N + L = M.
  35. 35. 如权利要求23所述的内置振荡电路,其特征在于,所述内置振荡电路还包括多倍分频器,所述多倍分频器设置于所述环形振荡器和频率-电压转化电路之间,所述多倍分频器对所述频率信号进行分频后,输出至所述频率-电压转化电路,以使所述频率-电压转化电路稳定工作。 35. The built-in oscillating circuit according to claim 23, characterized in that said oscillation circuit further comprises a multiple built-in frequency divider, a multiple frequency divider disposed in said ring oscillator and a frequency - voltage conversion circuit after between, the multiple of the frequency divider for dividing the frequency signal output to the frequency - voltage conversion circuit such that said frequency - voltage conversion circuit stability.
  36. 36. 如权利要求35所述的内置振荡电路,其特征在于,当所述频率信号稳定输出时,所述频率信号为: 36. The built-in oscillation circuit according to claim 35, wherein, when the stable output frequency signal, the frequency signal:
    Figure CN103066952BC00071
    其中,M为所述多倍分频器的分频倍数,fout为所述内置振荡器的输出频率,Cc为第一充放电容的电容值,(Rp+Rn)为基本电流产生电路的可修调电阻的电阻值,K为比例系数。 Wherein the circuit may be generated, M being a multiple of the frequency division multiple divider, fout is the output frequency of the oscillator built, Cc is the capacitance of the first charge and discharge capacity, (Rp + Rn) of the basic current trim resistance of the resistor, K is a proportionality factor.
  37. 37. 如权利要求35所述的内置振荡电路,其特征在于,所述多倍分频器包括多个级联的两倍分频器。 Built-in oscillation circuit according to claim 37. 35, characterized in that said divider comprises a plurality of cascaded multiple times frequency divider.
  38. 38. 如权利要求23所述的内置振荡电路,其特征在于,所述差分放大电路包括第二运算放大器、电阻和电容,所述第二运算放大器的一输入端接所述参考电压、另一输入端通过所述电阻接所述反馈电压、输出端接所述环形振荡器,所述电容一端连接于所述第一运算放大器和所述电阻之间,另一端连接于所述第一运算放大器和所述环形振荡器之间。 38. The built-in oscillating circuit according to claim 23, wherein said differential amplifier circuit comprises a second operational amplifier, resistors and capacitors, said operational amplifier is an input end of said second reference voltage, the other between the voltage input terminal, an output end of said ring oscillator, said first operational amplifier is connected to one end of the capacitor and the resistor connected to the feedback via the resistor, and the other end connected to the first operational amplifier and between the ring oscillator.
  39. 39. 如权利要求23至38中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围在27MHZ~49MHZ的玩具遥控设备中。 Built-in oscillation circuit to any one of claims 23 to 38 as claimed in claim 39, wherein said built-in oscillation circuit provided in the frequency range of the remote control device toys in the 27MHZ ~ 49MHZ.
  40. 40. 如权利要求23至38中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围315MHz或433MHZ的无线控制设备中。 40. The built-in oscillation circuit to any one of claims 23-38, wherein said built-in oscillation circuit provided in the frequency range of 433MHZ or 315MHz radio control apparatus.
  41. 41. 如权利要求23至38中任意一项所述的内置振荡电路,其特征在于,所述内置振荡电路设置于频率范围在38KHz的红外遥控设备中。 41. The built-in oscillation circuit to any one of claims 23-38, wherein said built-in oscillation circuit is provided in the frequency range of 38KHz infrared remote control device.
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CN103236871A (en) * 2013-05-10 2013-08-07 武汉光华芯科技有限公司 Novel receiving and transmitting system for control of wireless remote control vehicle
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CN104143968B (en) * 2014-07-30 2017-08-22 深圳市芯海科技有限公司 Elimination of on-chip oscillator circuit delay control logic
CN106033970A (en) * 2015-03-11 2016-10-19 中芯国际集成电路制造(上海)有限公司 Trimming circuit for oscillator
CN104836578A (en) * 2015-05-22 2015-08-12 成都西蒙电子技术有限公司 Device and method for improving long-term stability of crystal oscillator

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