CN102420591B - Oscillator - Google Patents

Abstract

The invention discloses an oscillator, which comprises a first capacitor having a cathode thereof grounded; a current source circuit being used for providing a reference current, wherein an output end of the current source circuit is connected to an anode of the first capacitor to charge the first capacitor; a discharge circuit having an output end thereof connected to the anode of the first capacitor and being used for discharging the first capacitor; and an offset comparer having a positive input end thereof connected to the anode of the first capacitor and an output end thereof connected to an input end of the discharge circuit. When a voltage of the anode of the first capacitor is higher than an offset voltage, the state of the output end of the offset comparer is turned over, and the discharge circuit is driven to start discharging the first capacitor; and when the voltage of the anode of the first capacitor is lower than the offset voltage, the state of the output end of the offset comparer is turned over again, the discharge circuit is driven to stop discharging the first capacitor, and the current source circuit recharges the first capacitor. The oscillator provided by the invention has advantages of low power consumption and high precision.

Description

Oscillator

Technical field

The present invention relates to technical field of integrated circuits, relate in particular to a kind of oscillator.

Background technology

Oscillator is widely used in various electronic products, and particularly in integrated circuit, oscillator provides clock signal for the various digital signal processing modules in integrated circuit.But in integrated circuit, the output frequency of the simple annular oscillator based on inverter can have huge fluctuation with supply voltage, is not suitable for the applied environment that clock frequency is had relatively high expectations.

In the prior art, notification number is that the Chinese patent of CN201222719Y discloses a kind of high-precision ring oscillator, shown in figure 1, comprise at least one ring oscillator stage 2 and the current source 1 being electrically connected with it, wherein: described ring oscillator stage 2 comprises the inverter that the metal-oxide-semiconductor field effect transistor of two kinds of different conduction-types forms and the metal-oxide-semiconductor field effect transistor being electrically connected with described inverter; Described current source 1 comprises metal-oxide-semiconductor field effect transistor and the adjustable resistance that the threshold voltage of the metal-oxide-semiconductor field effect transistor in threshold voltage and ring oscillator stage 2 compensates mutually; Fout is ring oscillator signal output part.

The gate source voltage V of above-mentioned technology field-effect transistors _gSit is V that voltage and adjustable resistance R produce a size _gSthe electric current of/R or its multiple.In the time adopting above-mentioned electric current to charge to electric capacity, once the voltage at electric capacity two ends reaches V _gStime, the output state of oscillator just overturns.Control metal-oxide-semiconductor field effect transistor discharges to electric capacity simultaneously.Then carry out charging-discharge process of next time cycle.

But the gate source voltage V that the reference voltage of its generation current is metal-oxide-semiconductor field effect transistor _gS, the gate source voltage V of general metal-oxide-semiconductor field effect transistor _gSfor 0.7V, this magnitude of voltage is higher, therefore makes the oscillator of this structure not too be applicable to the application scenario of low-power consumption.

In addition, the Chinese patent application that publication number is CN101286733A discloses a kind of oscillator with low voltage and low power consumption, shown in Figure 2, comprising:

Capacitor C 1;

Electric current source generating circuit, comprising: start-up circuit, the current mirror being made up of a PMOS transistor MP1 and the 2nd PMOS transistor MP2, the amplifying circuit and the resistance R 1 that are made up of the first nmos pass transistor MN1 and the second nmos pass transistor MN2;

The charging circuit being formed by the 4th PMOS transistor MP4;

The comparison circuit being formed by the 4th nmos pass transistor MN4;

The discharge circuit being formed by the 3rd nmos pass transistor MN3;

The delay circuit being formed by the first inverter U1 and the second inverter U2.

Above-mentioned technology is utilized the gate source voltage V of a PMOS transistor MP1 _gS1gate source voltage V with the 2nd PMOS transistor MP2 _gS2between voltage difference delta V _gSwith resistance R 1 generation current, capacitor C 1 is charged, when the voltage at capacitor C 1 two ends reaches Δ V _gStime, the output state flip of oscillator, the electric charge in capacitor C 1 is released; Then enter next cycle charging-discharge time.

But in above-mentioned oscillator, judge whether the voltage of capacitor C 1 is charged to Δ V _gScomparison circuit (i.e. the 4th nmos pass transistor MN4) and charging circuit (i.e. the 4th PMOS transistor MP4) composition single-stage inverting amplifier, its gain amplifier is limited, and response speed is slower, thereby directly affects the precision of clock frequency.

Summary of the invention

The problem that the present invention solves is to provide a kind of height oscillator accurately.

For addressing the above problem, the invention provides a kind of oscillator, comprising:

The first electric capacity, the minus earth of described the first electric capacity;

Current source circuit, for reference current is provided, described reference current is I=nMV _t, wherein: I is reference current, n is the constant relevant to technique, V _tfor thermal voltage, M is the parameter relevant to device size in current source circuit, and the output of described current source circuit connects the positive pole of described the first electric capacity, for described the first electric capacity is charged;

Discharge circuit, its output connects the positive pole of described the first electric capacity, for described the first electric capacity is discharged;

Imbalance comparator, its positive input terminal connects the positive pole of described the first electric capacity, its output connects the input of described discharge circuit, in the time that the voltage of described the first capacitance cathode is greater than offset voltage, the state output terminal of described imbalance comparator overturns, and drives described discharge circuit to start described the first electric capacity to discharge; In the time that the voltage of described the first capacitance cathode is less than offset voltage, the state output terminal of described imbalance comparator overturns again, drive described discharge circuit to stop described the first electric capacity to discharge, described current source circuit charges to described the first electric capacity again; Described offset voltage is V _tH=nlnkV _t, wherein: V _tHfor offset voltage, n is the constant relevant to technique, V _tfor thermal voltage, k is the parameter relevant to the device size of imbalance comparator.

Alternatively, described oscillator also comprises: start-up circuit, its output connects described current source circuit, works for starting current source circuit.

Alternatively, described start-up circuit comprises: a PMOS transistor, the first nmos pass transistor, the 2nd PMOS transistor and the second electric capacity, wherein: the transistorized source electrode of a PMOS connects supply voltage, the grid of the transistorized grid of a PMOS, the first nmos pass transistor, the transistorized source electrode of the 2nd PMOS are connected with the positive pole of the second electric capacity and as the output of start-up circuit; Transistorized drain electrode is connected with the 2nd PMOS for the drain electrode of the transistorized drain electrode of the one PMOS, the first nmos pass transistor, the transistorized grid of the 2nd PMOS, the source ground of the first nmos pass transistor; The minus earth of the second electric capacity.

Alternatively, described current source circuit comprises: the 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 5th PMOS transistor and resistance, wherein: the transistorized source electrode of the 3rd PMOS connects supply voltage, and the grid of the transistorized drain electrode of the 3rd PMOS, the second nmos pass transistor, the drain electrode of the second nmos pass transistor are connected with the grid of the 3rd nmos pass transistor; The source ground of the second nmos pass transistor; The transistorized source electrode of the 4th PMOS connects supply voltage; The transistorized source electrode of the 5th PMOS connects supply voltage; The drain electrode of output, the transistorized grid of the 3rd PMOS, the transistorized grid of the 4th PMOS, the transistorized drain electrode of the 4th PMOS and the 3rd nmos pass transistor of described start-up circuit is connected with the transistorized grid of the 5th PMOS; The transistorized drain electrode of the 5th PMOS is as the output of described current source circuit, and it connects the positive pole of described the first electric capacity; One end of the source electrode contact resistance of the 3rd nmos pass transistor, the other end ground connection of resistance.

Alternatively, described the 3rd nmos pass transistor and the second nmos pass transistor are all operated in sub-threshold region, and described in wherein: m is the ratio of the breadth length ratio of the 3rd nmos pass transistor and the second nmos pass transistor, the resistance value that R is described resistance.

Alternatively, the temperature coefficient of described resistance is less than or equal to 400ppm/ DEG C.

Alternatively, described discharge circuit comprises: the 4th nmos pass transistor, wherein: the source electrode of the 4th nmos pass transistor connects the positive pole of electric capacity, and the grounded drain of the 4th nmos pass transistor, the grid of the 4th nmos pass transistor connects the output of imbalance comparator.

Alternatively, described imbalance comparator also comprises offset side, and its offset side connects the transistorized grid of described the 5th PMOS.

Alternatively, described imbalance comparator comprises: the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the 5th nmos pass transistor, the 6th nmos pass transistor and the 7th nmos pass transistor, wherein: the transistorized grid of the 8th PMOS is connected with the transistorized grid of the 9th PMOS as the offset side of imbalance comparator, the transistorized source electrode of the 8th PMOS connects supply voltage, and the transistorized source electrode of the 9th PMOS connects supply voltage; The transistorized grid of the 6th PMOS connects the positive pole of the first electric capacity, the transistorized grounded-grid of the 7th PMOS; The transistorized drain electrode of the 8th PMOS, the transistorized source electrode of the 6th PMOS and the transistorized source electrode of the 7th PMOS are connected; The grid of the drain electrode of the transistorized drain electrode of the 6th PMOS, the 5th nmos pass transistor, the grid of the 5th nmos pass transistor, the 6th nmos pass transistor is connected with the grid of the 7th nmos pass transistor; The source ground of the 5th nmos pass transistor, the source ground of the 6th nmos pass transistor; The source ground of the 7th nmos pass transistor; The drain electrode of the transistorized drain electrode of the 9th PMOS and the 7th nmos pass transistor is connected and is connected the input of described discharge circuit.

Alternatively, described the 6th PMOS transistor and the 7th PMOS transistor are all operated in sub-threshold region, and described k is the ratio of the transistorized breadth length ratio of the 6th PMOS and the transistorized breadth length ratio of the 7th PMOS.

Alternatively, the gain of described imbalance comparator is more than or equal to 60dB.

Compared with prior art, the present invention has the following advantages:

1) reference current that current source circuit provides and the offset voltage that provides of imbalance comparator be the Size dependence of main and device all, thereby the time cycle of oscillator is not subject to the impact of integrated circuit technology, and the offset voltage of imbalance comparator is less to the Accuracy of oscillator, finally improve the precision of oscillator.

2) in possibility, the 3rd nmos pass transistor and the second nmos pass transistor in described current source circuit are all operated in sub-threshold region, the 6th PMOS transistor and the 7th PMOS transistor in described imbalance comparator are all operated in sub-threshold region, therefore oscillator can be worked under extremely low electric current, has reduced the power consumption of oscillator.

3), in possibility, the gain of described imbalance comparator is more than or equal to 60dB, thus the impact of the finite gain that has reduced imbalance comparator on clock frequency.

4), in possibility, the temperature coefficient of described resistance is less than or equal to 10 ^-4ppm/ DEG C (being 10E-6 DEG C), thus make the frequency of oscillator be subject to the impact of temperature smaller, further improve the precision of oscillator.

Brief description of the drawings

Fig. 1 is the structural representation of a kind of high-precision ring oscillator of prior art;

Fig. 2 is the structural representation of a kind of oscillator with low voltage and low power consumption of prior art;

Fig. 3 is the structural representation of oscillator in embodiment of the present invention;

Fig. 4 is the structural representation of oscillator in the embodiment of the present invention;

Fig. 5 is the structural representation of comparator of lacking of proper care in Fig. 4.

Embodiment

For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.

Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.

Just as described in the background section, in prior art there is the defect that power consumption is higher or precision is lower in oscillator, therefore how to realize low-power consumption and height accurately oscillator just become those skilled in the art's problem demanding prompt solution.

In order to overcome above-mentioned defect, the invention provides a kind of oscillator, shown in figure 3, comprising:

Current source circuit 11, for reference current is provided, described reference current is I=nMV _t, wherein: I is reference current, n is the constant relevant to technique, V _tfor thermal voltage, M is the parameter relevant to device size in current source circuit 11, the output of described current source circuit 11 connect the positive pole of the first capacitor C+, for described the first capacitor C is charged;

The first capacitor C, negative pole-ground connection GND of described the first capacitor C;

Discharge circuit 13, its output connect the positive pole of described the first capacitor C+, for described the first capacitor C is discharged;

Imbalance comparator U, the positive pole of described the first capacitor C of its positive input terminal+connect+, its output OUT connects the input of described discharge circuit 13, when described the first capacitor C positive pole+voltage while being greater than offset voltage, the output OUT state of described imbalance comparator U overturns, and drives described discharge circuit 13 to start described the first capacitor C to discharge; When described the first capacitor C positive pole+voltage while being less than offset voltage, the state output terminal of described imbalance comparator U overturns again, drive described discharge circuit 13 to stop described the first capacitor C to discharge, described current source circuit 11 charges to described the first capacitor C again; Described offset voltage is V _tH=nln kV _t, wherein: V _tHfor offset voltage, n is the constant relevant to technique, V _tfor thermal voltage, k is the parameter relevant to the device size of imbalance comparator U.

Described thermal voltage V _trefer to the potential difference that exists the temperature difference to occur due to point-to-point transmission in closed circuit, it is known for those skilled in the art, does not repeat them here.

Be elaborated below in conjunction with accompanying drawing.

Shown in figure 4, the present embodiment provides a kind of oscillator, comprising:

Start-up circuit 14, comprising: a PMOS transistor MP1, the first nmos pass transistor MN1, the 2nd PMOS transistor MP2 and the second capacitor C 2.Wherein: the source electrode of a PMOS transistor MP1 meets supply voltage VDD, the source electrode of the grid of a PMOS transistor MP1, the grid of the first nmos pass transistor MN1, the 2nd PMOS transistor MP2 is connected with the positive pole of the second capacitor C 2 and as the output of start-up circuit 14.The grid of the drain electrode of the one PMOS transistor MP1, the drain electrode of the first nmos pass transistor MN1, the 2nd PMOS transistor MP2 is connected with the drain electrode of the 2nd PMOS transistor MP2, the source ground GND of the first nmos pass transistor MN1.The minus earth GND of the second capacitor C 2.

Current source circuit 11, comprising: the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the second nmos pass transistor MN2, the 3rd nmos pass transistor MN3, the 5th PMOS transistor MP5 and resistance R.Wherein: the source electrode of the 3rd PMOS transistor MP3 connects supply voltage VDD, and the drain electrode of the drain electrode of the 3rd PMOS transistor MP3, the grid of the second nmos pass transistor MN2, the second nmos pass transistor MN2 is connected with the grid of the 3rd nmos pass transistor MN3.The source ground GND of the second nmos pass transistor MN2.The source electrode of the 4th PMOS transistor MP4 connects supply voltage VDD.The source electrode of the 5th PMOS transistor MP5 connects supply voltage VDD.The grid of the output of start-up circuit 14, the grid of the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the drain electrode of the 4th PMOS transistor MP4, the grid of the 5th PMOS transistor MP5 are connected with the drain electrode of the 3rd nmos pass transistor MN3.The drain electrode of the 5th PMOS transistor MP5 connects the positive pole of the first capacitor C, and the drain electrode of the 5th PMOS transistor MP5 is as the output of current source circuit 11.One end of the source electrode contact resistance R of the 3rd nmos pass transistor MN3, the other end ground connection GND of resistance R.

The first capacitor C, the output of positive pole+connection current source circuit 11 of described the first capacitor C, negative pole-ground connection GND of described the first capacitor C.

Discharge circuit 13, comprising: the 4th nmos pass transistor MN4.Wherein: the source electrode of the 4th nmos pass transistor MN4 is as the output of discharge circuit 13, connect the positive pole of the first capacitor C+, the grounded drain GND of the 4th nmos pass transistor MN4, the grid of the 4th nmos pass transistor MN4, as the input of discharge circuit 13, connects the output OUT of imbalance comparator U.

Imbalance comparator U, comprising: positive input terminal+, negative input end-, output OUT and offset side bias.Wherein: the positive pole of positive input terminal+connection the first capacitor C+, negative input end-ground connection GND, output OUT connects the input of discharge circuit 13, and offset side bias connects bias voltage source.The bias of offset side described in the present embodiment can directly connect the grid of the 5th PMOS transistor MP5.The effect of the offset side bias of described imbalance comparator U is to provide work needed bias voltage for imbalance comparator U; it should be noted that; in other embodiments of the invention; described offset side bias can also connect other can provide the device of bias voltage (i.e. a fixed-bias transistor circuit), and it should not limit the scope of the invention.

The output OUT of comparator U of lacking of proper care described in the present embodiment can be used as the output of oscillator, for clock signal.

Wherein, described start-up circuit 14 is when ensureing that supply voltage VDD powers on, and current source circuit 11 can normally be worked.In the present embodiment, a PMOS transistor MP1 and the first nmos pass transistor MN1 are connected into inverter form, and described the 2nd PMOS transistor MP2 is connected into diode form.Inverter input terminating diode negative terminal, inverter output connects diode anode; The positive pole of the second capacitor C 2 connects diode negative terminal, the minus earth GND of the second capacitor C 2.The current potential of inverter input starts to keep supply voltage after powering on like this, thereby the output voltage of inverter equals zero.But along with the rising of supply voltage VDD, in the time that supply voltage VDD is greater than the threshold voltage of a PMOS transistor MP1 and the threshold voltage sum of the 2nd PMOS transistor MP2, form current path through the 4th PMOS transistor MP4, the 2nd PMOS transistor MP2 and the first nmos pass transistor MN1 from supply voltage VDD successively to ground GND, also form current path from a PMOS transistor MP1 to the first nmos pass transistor simultaneously, thereby can starting current source circuit 11, break away from the operating state of zero current.After the lower voltage of inverter input, inverter output voltage uprises simultaneously, and because diode is reverse-biased, the current potential of inverter input can not return to supply voltage again.

It should be noted that, the present invention can also adopt the start-up circuit 14 of other structures, and it is known for those skilled in the art, does not repeat them here.

Wherein, in described current source circuit 11, the second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 are all operated in sub-threshold region, and the ratio of the breadth length ratio of the breadth length ratio of the second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 is 1: m, m is greater than 1.The size of described the 3rd PMOS transistor MP3 and the 4th PMOS transistor MP4 can be identical, and composition current lens unit, identical with the input current of the 3rd nmos pass transistor MN3 to ensure the second nmos pass transistor MN2.

The reference current that in the present embodiment, current source circuit 11 is exported is:

$I=\frac{\mathrm{\Δ}{V}_{\mathrm{GS}}}{R}=\frac{n\·\ln m}{R}\·V_T$

Wherein: n is the constant relevant to technique, m is the ratio of the breadth length ratio of the 3rd nmos pass transistor MN3 and the second nmos pass transistor MN2, V _tfor thermal voltage (being 26mV under normal temperature), the resistance value that R is resistance R.

Because the second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 are all operated in sub-threshold region, therefore it doesn't matter for the reference current that described current source circuit 11 provides and supply voltage VDD, and the current source circuit 11 required electric current of working is smaller, thereby reduce the power consumption of oscillator.

It should be noted that, in other embodiments of the invention, can also adopt the current source circuit 11 of other structures, as long as its reference current providing is I=nMV _t, wherein: described in all within protection scope of the present invention.

Wherein, described current source circuit 11 charges to the first capacitor C.In the present embodiment, the size of the 5th PMOS transistor MP5, the 4th PMOS transistor MP4 and the 3rd PMOS transistor MP3 can equate, and the 5th PMOS transistor MP5, the 4th PMOS transistor MP4 and the 3rd PMOS transistor MP3 form respectively current mirror.Because the gate source voltage of the 5th PMOS transistor MP5 equates with the gate source voltage of the 4th PMOS transistor MP4, and the size of the 5th PMOS transistor MP5 and the 4th PMOS transistor MP4 is equal, and therefore the drain current of the 4th PMOS transistor MP4 is identical with the drain current of the 5th PMOS transistor MP5.Consider that again the 5th PMOS transistor MP5 is voltage control device, its grid current very little (can be approximated to be 0), therefore the drain current of the 5th PMOS transistor MP5 also can be expressed as

Correspondingly, after t after a while, the first capacitor C positive pole+voltage v _cfor:

$v_c=\frac{I\·t}{C}=\frac{n\·\ln m}{\mathrm{RC}}\·V_t\·t,$

Wherein: C is the capacitance of the first capacitor C.

Wherein, described imbalance comparator U has positive offset voltage, when imbalance comparator U positive input terminal+voltage be greater than negative input end-offset voltage time, the state of the output OUT of imbalance comparator U just overturns.

The gain of described imbalance comparator U can be more than or equal to 60dB, thus the impact of the finite gain that has reduced imbalance comparator on clock frequency, particularly, and as: 60dB, 70dB or 80dB.

As an object lesson, shown in figure 5, described imbalance comparator U comprises: the 6th PMOS transistor MP6, the 7th PMOS transistor MP7, the 8th PMOS transistor MP8, the 9th PMOS transistor MP9, the 5th nmos pass transistor MN5, the 6th nmos pass transistor MN6 and the 7th nmos pass transistor MN7.Wherein: the grid of the 8th PMOS transistor MP8 is connected with the grid of the 9th PMOS transistor MP9 as the offset side bias of imbalance comparator U.The source electrode of the 8th PMOS transistor MP8 connects supply voltage VDD, and the source electrode of the 9th PMOS transistor MP9 connects supply voltage VDD.The grid of the 6th PMOS transistor MP6 as the positive input terminal of imbalance comparator U+, the grid of the 7th PMOS transistor MP7 as the negative input end of imbalance comparator U-.The drain electrode of the 8th PMOS transistor MP8, the source electrode of the 6th PMOS transistor MP6 are connected with the source electrode of the 7th PMOS transistor MP7.The grid of the drain electrode of the 6th PMOS transistor MP6, the drain electrode of the 5th nmos pass transistor MN5, the 5th nmos pass transistor MN5, the grid of the 6th nmos pass transistor MN6 are connected with the grid of the 7th nmos pass transistor MN7.The source ground GND of the 5th nmos pass transistor MN5, the source ground GND of the 6th nmos pass transistor MN6.The drain electrode of the 7th PMOS transistor MP7 connects the drain electrode of the 6th MNOS transistor MN6.The source ground GND of the 7th nmos pass transistor MN7.The drain electrode of the 9th PMOS transistor MP9 is connected with the drain electrode of the 7th nmos pass transistor MN7 and as the output OUT of imbalance comparator U.

The structure of comparator U of lacking of proper care described in the present embodiment is identical with differential amplifier, but different from conventional difference amplifier is the size difference of its two input pipes (i.e. the 6th PMOS transistor MP6 and the 7th PMOS transistor MP7), thereby can produce offset voltage.

The breadth length ratio of the 6th PMOS transistor MP6 in comparator U of lacking of proper care described in the present embodiment is different with the breadth length ratio of the 7th PMOS transistor MP7, and the 6th PMOS transistor MP6 and the 7th PMOS transistor MP7 are operated in sub-threshold region.

In the time that the ratio of the breadth length ratio of the 6th PMOS transistor MP6 and the breadth length ratio of the 7th PMOS transistor MP7 is k:1, the negative input end of imbalance comparator U-offset voltage V _tHfor:

V _TH＝ΔV _GS＝n·lnk·V _T，

Wherein: n is the constant relevant to technique, V _tfor thermal voltage (being 26mV under normal temperature), Δ V _gSbe the voltage difference between the gate source voltage of the 6th PMOS transistor MP6 and the gate source voltage of the 7th PMOS transistor MP7, k is greater than 1.

Because the 6th PMOS transistor MP6 and the 7th PMOS transistor MP7 are operated in sub-threshold region, the therefore negative input end of described imbalance comparator U-offset voltage V _tHirrelevant with supply voltage VDD, and the imbalance comparator U required electric current of working is also smaller, thus further reduce the power consumption of oscillator.

In addition, what the comparator U that lacks of proper care described in the present embodiment adopted is the structure of two stage amplifer, thereby the gain of the comparator U that makes to lack of proper care is higher, and response speed is faster, the impact of the finite gain that has greatly reduced imbalance comparator U on clock frequency.It should be noted that, in other embodiments of the invention, can also adopt three grades of amplifiers and three grades of structures more than amplifier, it does not limit the scope of the invention.

The course of work of the present embodiment oscillator comprises:

1) for oscillator powers on, start-up circuit 14 ensures that current source circuit 11 normally works, and current source circuit 11 is for reference current is provided, and the first capacitor C is charged.

2) when the charging interval more in short-term, the positive pole+voltage of the first capacitor C is less than offset voltage V _tHtime, the output of imbalance comparator U is low level, discharge circuit 13 do not work (the 4th nmos pass transistor MN4 is in cut-off state).

3) after charging after a while, the positive pole+voltage of the first capacitor C is greater than offset voltage V _tHthe output upset of comparator U of now lacking of proper care is high level, discharge circuit 13 starts the first capacitor C discharge (the 4th nmos pass transistor MN4 is in conducting state), although now current source circuit 11 is still charging to the first capacitor C, but because the electric current of charging is much smaller than the electric current of electric discharge, therefore charging is now negligible.

4) along with the electric discharge of discharge circuit 13 to capacitor C, positive pole+the voltage of capacitor C constantly reduces, thereby positive input terminal+voltage step-down of imbalance comparator U, in the time that positive input terminal+voltage of imbalance comparator U is less than offset voltage, the output OUT of comparator U of making to lack of proper care is low level, now discharge circuit 13 quits work (the 5th nmos pass transistor MN5 is again in cut-off state), and the first capacitor C restarts charging.

In order to ensure the precision of oscillator, in the present embodiment, discharge circuit 13 is to being less than the response time of imbalance comparator U the discharge time of the first capacitor C, to ensure that the electric charge in the first capacitor C is once thoroughly discharged before charging upper.

The response time t of imbalance comparator U _pcan be expressed as:

$t_p=\frac{\mathrm{vdd}/2}{\mathrm{SR}}$

In formula, SR is the Slew Rate (slew rate) (described Slew Rate is the imbalance comparator U speed that output end voltage changes in the time that input applies large-signal voltage, and unit is V/us) of imbalance comparator U.

The voltage at the first capacitor C two ends can be expressed as with the relation of t discharge time:

$U\left(t\right)=U_0\·e^{-\frac{t}{{\mathrm{\τ}}_d}},$

Wherein: U (t) is the transient voltage value at the first capacitor C two ends in discharge process, U ₀it is the initial state of voltage in the first capacitor C.τ _dfor the time constant of discharge circuit 13, i.e. τ _d=R _oNc, R _oNfor the conducting resistance of discharge circuit 13, C is the capacitance of the first capacitor C.T discharge time that the voltage drop that can establish the first capacitor C two ends in discharge process in the present embodiment is electric capacity to 1/10000 of initial value required time _d, $t_d=(-{\mathrm{\τ}}_d)\·\ln \left(\frac{1}{10000}\right)=9.21\·{\mathrm{\τ}}_d=9.21\·R_{\mathrm{ON}}C.$

In order to ensure the precision of oscillator, require to be less than or equal to the discharge time of the first capacitor C the propagation delay time t of imbalance comparator U _p, that is:

t _d≤t _p。

By τ discharge time _dwith propagation delay time τ _pbringing above formula into can obtain:

$9.21\·R_{\mathrm{ON}}C\≤\frac{\mathrm{VDD}}{2\·\mathrm{SR}}$

That is: $R_{\mathrm{on}}\≤0.054\frac{\mathrm{VDD}}{\mathrm{SR}\·C}.$

In the present embodiment, discharge circuit 13 is very short to the discharge time of the first capacitor C, it is negligible to the charging interval of the first capacitor C with respect to current source circuit 11, therefore the time that in the present embodiment, the first capacitor C is once charged is as the time cycle of oscillator, when the positive pole of the first capacitor C+charging interval of experiencing while equaling to lack of proper care the offset voltage of comparator U of voltage be exactly the time cycle of oscillator, thereby in the present embodiment, the period of time T of oscillator is:

$T=\frac{\ln k}{\ln m}\·R\·C,$

Wherein: m is the ratio of the breadth length ratio of the 3rd nmos pass transistor and the second nmos pass transistor in current source circuit 11, k is the ratio of the transistorized breadth length ratio of the 6th PMOS and the transistorized breadth length ratio of the 7th PMOS in imbalance comparator U, m is greater than 1, k is greater than 1, R is the resistance value of resistance R in current source circuit 11, and C is the capacitance of the first capacitor C.

Analyze above-mentioned formula known: the period of time T of oscillator and n in the present embodiment (with technique relevant constant) and V _t(being thermal voltage) all it doesn't matter, and oscillator is not subject to the impact of integrated circuit technology, thereby further ensured the precision of oscillator.M, k, R and C are the physical parameters of device, irrelevant with the bias voltage of imbalance comparator U.

In the present embodiment, the clock cycle of oscillator not only can realize by the capacitance of the resistance value of adjusting resistance R and the first capacitor C, can also by adjust the breadth length ratio of the 3rd nmos pass transistor MN3 and the second nmos pass transistor MN2 in current source circuit 11 ratio or/and in imbalance comparator U the ratio of the breadth length ratio of the 6th PMOS transistor MP6 and the breadth length ratio of the 7th PMOS transistor MP7 realize.

In the application scenario of low frequency, can reduce resistance R and the first capacitor C shared area on chip.

The temperature coefficient of described resistance R can be less than or equal to 400ppm/ DEG C.Particularly, can adopt the method for positive temperature coefficient and negative temperature coefficient combination, it is known for those skilled in the art, does not repeat them here.

In the time that the temperature coefficient of resistance R is smaller, the resistance value of resistance R is not just subject to the impact of temperature, thereby the period of time T of oscillator is subject to the impact of temperature just very little, and the precision of final oscillator can be higher.

Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (10)

1. an oscillator, is characterized in that, comprising:

The first electric capacity, the minus earth of described the first electric capacity;

Current source circuit, for reference current is provided, described reference current is I=nMV _t, wherein: I is reference current, n is the constant relevant to technique, V _tfor thermal voltage, M is the parameter relevant to device size in current source circuit, and the output of described current source circuit connects the positive pole of described the first electric capacity, for described the first electric capacity is charged;

Discharge circuit, its output connects the positive pole of described the first electric capacity, for described the first electric capacity is discharged;

Imbalance comparator, its positive input terminal connects the positive pole of described the first electric capacity, its output connects the input of described discharge circuit, in the time that the voltage of described the first capacitance cathode is greater than offset voltage, the state output terminal of described imbalance comparator overturns, and drives described discharge circuit to start described the first electric capacity to discharge; In the time that the voltage of described the first capacitance cathode is less than offset voltage, the state output terminal of described imbalance comparator overturns again, drive described discharge circuit to stop described the first electric capacity to discharge, described current source circuit charges to described the first electric capacity again; Described offset voltage is V _tH=nlnkV _t, wherein: V _tHfor offset voltage, n is the constant relevant to technique, V _tfor thermal voltage, the positive input terminal PMOS transistor of described imbalance comparator is different with the transistorized size of negative input end PMOS and be all operated in sub-threshold region, and k is the ratio of the transistorized breadth length ratio of described positive input terminal PMOS and the transistorized breadth length ratio of negative input end PMOS.

2. oscillator as claimed in claim 1, is characterized in that, also comprises: start-up circuit, its output connects described current source circuit, works for starting current source circuit.

3. oscillator as claimed in claim 2, it is characterized in that, described start-up circuit comprises: a PMOS transistor, the first nmos pass transistor, the 2nd PMOS transistor and the second electric capacity, wherein: the transistorized source electrode of a PMOS connects supply voltage, the grid of the transistorized grid of a PMOS, the first nmos pass transistor, the transistorized source electrode of the 2nd PMOS are connected with the positive pole of the second electric capacity and as the output of start-up circuit; Transistorized drain electrode is connected with the 2nd PMOS for the drain electrode of the transistorized drain electrode of the one PMOS, the first nmos pass transistor, the transistorized grid of the 2nd PMOS, the source ground of the first nmos pass transistor; The minus earth of the second electric capacity.

4. oscillator as claimed in claim 2, it is characterized in that, described current source circuit comprises: the 3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 5th PMOS transistor and resistance, wherein: the transistorized source electrode of the 3rd PMOS connects supply voltage, and the grid of the transistorized drain electrode of the 3rd PMOS, the second nmos pass transistor, the drain electrode of the second nmos pass transistor are connected with the grid of the 3rd nmos pass transistor; The source ground of the second nmos pass transistor; The transistorized source electrode of the 4th PMOS connects supply voltage; The transistorized source electrode of the 5th PMOS connects supply voltage; The drain electrode of output, the transistorized grid of the 3rd PMOS, the transistorized grid of the 4th PMOS, the transistorized drain electrode of the 4th PMOS and the 3rd nmos pass transistor of described start-up circuit is connected with the transistorized grid of the 5th PMOS; The transistorized drain electrode of the 5th PMOS is as the output of described current source circuit, and it connects the positive pole of described the first electric capacity; One end of the source electrode contact resistance of the 3rd nmos pass transistor, the other end ground connection of resistance.

5. oscillator as claimed in claim 4, is characterized in that, described the 3rd nmos pass transistor and the second nmos pass transistor are all operated in sub-threshold region, and described in wherein: m is the ratio of the breadth length ratio of the 3rd nmos pass transistor and the second nmos pass transistor, the resistance value that R is described resistance.

6. oscillator as claimed in claim 4, is characterized in that, the temperature coefficient of described resistance is less than or equal to 400ppm/ DEG C.

7. oscillator as claimed in claim 1, it is characterized in that, described discharge circuit comprises: the 4th nmos pass transistor, wherein: the source electrode of the 4th nmos pass transistor connects the positive pole of electric capacity, the grounded drain of the 4th nmos pass transistor, the grid of the 4th nmos pass transistor connects the output of described imbalance comparator.

8. oscillator as claimed in claim 4, is characterized in that, described imbalance comparator also comprises offset side, and its offset side connects the transistorized grid of described the 5th PMOS.

9. oscillator as claimed in claim 8, it is characterized in that, described imbalance comparator comprises: the 6th PMOS transistor, the 7th PMOS transistor, the 8th PMOS transistor, the 9th PMOS transistor, the 5th nmos pass transistor, the 6th nmos pass transistor and the 7th nmos pass transistor, wherein: the transistorized grid of the 8th PMOS is connected as the offset side of described imbalance comparator with the transistorized grid of the 9th PMOS, the transistorized source electrode of the 8th PMOS connects supply voltage, and the transistorized source electrode of the 9th PMOS connects supply voltage; The transistorized grid of the 6th PMOS connects the positive pole of the first electric capacity, the transistorized grounded-grid of the 7th PMOS; The transistorized drain electrode of the 8th PMOS, the transistorized source electrode of the 6th PMOS and the transistorized source electrode of the 7th PMOS are connected; The grid of the drain electrode of the transistorized drain electrode of the 6th PMOS, the 5th nmos pass transistor, the grid of the 5th nmos pass transistor, the 6th nmos pass transistor is connected with the grid of the 7th nmos pass transistor; The source ground of the 5th nmos pass transistor, the source ground of the 6th nmos pass transistor; The source ground of the 7th nmos pass transistor; The drain electrode of the transistorized drain electrode of the 9th PMOS and the 7th nmos pass transistor is connected and is connected the input of described discharge circuit.

10. oscillator as claimed in claim 1, is characterized in that, the gain of described imbalance comparator is more than or equal to 60dB.