CN108429548A - A kind of relaxor and electronic device - Google Patents
A kind of relaxor and electronic device Download PDFInfo
- Publication number
- CN108429548A CN108429548A CN201710078531.6A CN201710078531A CN108429548A CN 108429548 A CN108429548 A CN 108429548A CN 201710078531 A CN201710078531 A CN 201710078531A CN 108429548 A CN108429548 A CN 108429548A
- Authority
- CN
- China
- Prior art keywords
- transistor
- comparator
- capacitance
- flop
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0231—Astable circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/02—Constructional features of telephone sets
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
Abstract
A kind of relaxor of present invention offer and electronic device.The relaxor includes：Charge/discharge unit；Switch unit, the charge/discharge unit carries out periodical charge and discharge in order to control for the switch unit configuration；Comparator unit, the comparator unit be configured to on the charge/discharge unit voltage and reference voltage be compared；Flip-flop element, the output signal that the flip-flop element is configured to the comparator unit generate oscillator signal and export to the switch unit, and periodical charge and discharge are carried out to control the charge/discharge unit；Wherein, comparator unit uses hysteresis comparator, reaction time t of the hysteresis voltage Vh of hysteresis comparator, the amplitude of oscillation voltage Vs of voltage signal on charge/discharge unit, cycle T when relaxor works, flip-flop element to meet：Vh ﹥ 2Vs × t/T.The relaxor can eliminate the self-excitation of potential fast feedback loop, to improve the stability of relaxor.The electronic device has the advantages that similar.
Description
Technical field
The present invention relates to semiconductor integrated circuit technology fields, are filled in particular to a kind of relaxor and electronics
It sets.
Background technology
In many Application of integrated circuit, clock generation circuit is an essential module, according to different applications
Scene demand, there are many kinds of the clock generation circuits of type.Fig. 1 shows a kind of common clock generation circuit：Relaxor.
As shown in Figure 1, relaxor 100 includes capacitance C1, C2, four metal-oxide-semiconductor M1~M4, comparator 101 and 102 and RS are touched
The oscillating circuit that device 103 forms is sent out, current source and voltage source 104 provide reference current Ir and reference voltage for the oscillating circuit
Vr, latch 103 include two phase inverters 1030 and 1031.Relaxor 100 shown in FIG. 1 gives capacitance C1 using current source
Output frequency is determined with the periodic charge and discharge of C2, and the output frequency of relaxor shown in Fig. 1 is by capacitance C1, C2, benchmark
Electric current Ir and reference voltage V r determines, when normal work, M1~M4 is used as switch, and C1 and C2 are alternately electric from 0 voltage to Vr
The electric current of charge and discharge between pressure, charge and discharge is Ir, so final clock output frequency is Fclock=Ir/Vr/C/2 (C1 and C2 electricity
Hold equal).
However, there are a potential rapid feedback accesses for this relaxation oscillator circuit structure：Va nodes are by comparing device
101, phase inverter 1030, phase inverter M1 and M3 return Va, when the reaction speed of comparator 101 is faster than the speed of rest-set flip-flop 103
It just will appear the high frequency output determined by the high-speed feedback channel when spending, at Qa, which is determined by the delay of high-speed feedback loop
It is fixed, and with the capacitance current voltage inside above-mentioned formula all unrelated (similarly, Vb, comparator 102, phase inverter 1031, phase inverter
M2 and M4 returns Vb also potential rapid feedback accesses).In order to avoid there is such case, general simple way is exactly to pass through
Reduce the gain of comparator either bandwidth or directly comparator behind again plus some phase inverters are delayed and reach reduction ratio
Compared with the purpose of device reaction speed.It is done so that at least there are two disadvantages：1) when working normally, comparator reacted slow introduced
Delay to calculate in total output, which influences bigger when high frequency clock exports.2) it does not completely eliminate this
Phenomenon, the probability for only this phenomenon occur reduce.
Therefore, it is necessary to a kind of relaxor be proposed, to solve the above problems.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are one aspect of the present invention provides a kind of relaxor comprising：
Charge/discharge unit；
Switch unit, the charge/discharge unit carries out periodical charge and discharge in order to control for the switch unit configuration；
Comparator unit, the comparator unit be configured to on the charge/discharge unit voltage and reference voltage carry out
Compare；
Flip-flop element, the output signal that the flip-flop element is configured to the comparator unit generate oscillation letter
Number and export to the switch unit, carry out periodical charge and discharge to control the charge/discharge unit；
Wherein, the comparator unit uses hysteresis comparator, the hysteresis voltage Vh of the hysteresis comparator, the charge and discharge
The amplitude of oscillation voltage Vs of voltage signal, the cycle T when relaxor works, the reaction of the flip-flop element on electric unit
Time t meets：Vh ﹥ 2Vs × t/T.
Further, the charge/discharge unit includes the first capacitance and the second capacitance, and the switch unit is opened including first
It includes first comparator and the second comparator, the flip-flop element to close unit and second switch unit, the comparator unit
For rest-set flip-flop；
First capacitance carries out periodical charge and discharge under the control of the first switch unit；
Second capacitance carries out periodical charge and discharge under the control of the second switch unit；
The first comparator be configured to on first capacitance voltage and reference voltage be compared, and will compare
As a result it exports to the first input end of the rest-set flip-flop；
Second comparator arrangement be on second capacitance voltage and reference voltage be compared, and will compare
As a result it exports to the second input terminal of the rest-set flip-flop；
The first output end and second output terminal outputting oscillation signal of the rest-set flip-flop, and the of the rest-set flip-flop
One output end and second output terminal are respectively connected to the first switch unit and second switch unit, to control first electricity
Hold and the second capacitance carries out periodical charge and discharge.
Further, the first switch unit includes first switching element and second switch element, and described first
Switch unit be configured to when the first switching element is connected described in the first capacitance charge, in the second switch element
First capacitance described in when conducting discharges；
The second switch unit includes third switch element and the 4th switch element, and the second switch unit is configured to
The second capacitance charges described in the third switching elements conductive, in four switching elements conductive described in second
Capacitance discharges；
The first input end of the first comparator is connect with the first end of first capacitance, the first comparator
Second input terminal is connect with reference voltage；
The first input end of second comparator is connect with the first end of second capacitance, second comparator
Second input terminal is connect with reference voltage；
The control terminal of the first output end and the first switching element and the second switch element of the rest-set flip-flop
Connection, to control the conducting of the first switching element and the second switch element, the second output terminal of the rest-set flip-flop
It is connect with the control terminal of the third switch element and the 4th switch element, to control the third switch element and described
The conducting of 4th switch element.
Further, the first switching element and the third switch element are PMOS transistor；
The drain electrode of the first switching element is connect with the first end of first capacitance, the grid of the first switching element
Pole is connect with the first output end of the rest-set flip-flop；
The drain electrode of the third switch element is connect with the first end of second capacitance, the grid of the third switch element
Pole is connect with the second output terminal of the rest-set flip-flop.
Further, the second switch element and the 4th switch element are NMOS transistor；
The drain electrode of the second switch element connect the grid of the second switch element with the first end of first capacitance
Pole is connect with the first output end of the rest-set flip-flop；
The drain electrode of 4th switch element is connect with the first end of second capacitance, the grid of the 4th switch element
Pole is connect with the second output terminal of the rest-set flip-flop.
Further, the rest-set flip-flop includes the first phase inverter and the second phase inverter；
The input terminal of first phase inverter and the output end of the first comparator and first phase inverter it is defeated
Outlet connects；
The output end of the input terminal of second phase inverter and second comparator and first phase inverter it is defeated
Outlet connects.
Further, the hysteresis comparator includes comparator module and positive feedback module, the positive feedback module setting
Between the input terminal and output end of the comparator module positive feedback is provided for the comparator module.
Further, the comparator module includes differential comparator, the differential comparator include the first transistor extremely
The grid of 5th transistor, the first transistor and second transistor is used as two input terminals of the differential comparator, institute
It states third transistor and provides tail current for the difference amplifier, the 4th transistor and the 5th transistor are as the difference
The load of amplifier；
The positive feedback module includes the 6th transistor and the 7th transistor, the 6th transistor and the 4th crystal
Pipe is for forming current mirror, and the drain electrode of the 6th transistor is connect with the drain electrode of the second transistor, and the described 7th
Transistor is with the 5th transistor for forming current mirror, and the drain electrode of the 7th transistor and the first transistor
Drain electrode connection, the 6th transistor and the 7th transistor are used to provide positive feedback for the differential comparator.
Further, the breadth length ratio of the 6th transistor is 2 times of the 4th transistor breadth length ratio；Described 7th is brilliant
The breadth length ratio of body pipe is 2 times of the 5th transistor breadth length ratio.
Further, the hysteresis comparator further includes output driving module,
The output driving module include the 8th transistor to the 11st transistor, the 8th transistor and with the tenth crystalline substance
Body pipe is connected in series with, and the 8th transistor is used to form current mirror, the 9th transistor with the 4th transistor
It is connected in series with the 11st transistor, and the 9th transistor is used to form current mirror with the 5th transistor, it is described
11st transistor forms current mirror with the tenth transistor, and the drain electrode of the 9th transistor and the 11st transistor is used as
The output end of the hysteresis comparator.
Further, described first, second, third, the ten, the 11st transistors are NMOS transistor, the described 4th to
9th transistor is PMOS transistor.
Relaxor according to the present invention with hysteresis comparator by replacing common continuous comparator, relatively using sluggishness
Equivalent gain eliminates the self-excitation of potential fast feedback loop for 0 property when device is near hysteresis voltage, to improving relaxation
The stability of oscillator.
Further aspect of the present invention provides a kind of electronic device comprising relaxor proposed by the present invention and with it is described
The electronic building brick of relaxor connection.
Electronic device proposed by the present invention since its relaxor having can eliminate self-excitation phenomena, thus does not have to
The gain for reducing comparator will not increase oscillator and always export delay, thus the electronic device have the advantages that it is similar.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 shows a kind of current circuit diagram of relaxor；
Fig. 2 shows the illustrative circuitry structure charts of relaxor according to an embodiment of the invention；
Fig. 3 shows the input and output exemplary comparative figure of continuous comparator and hysteresis comparator；
Fig. 4 shows the exemplary input curve of output of hysteresis comparator；
Fig. 5 shows the illustrative circuitry structure chart of hysteresis comparator according to the ... of the embodiment of the present invention；
Fig. 6 shows the structural schematic diagram of electronic device according to an embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated phase from beginning to end
Identical element is indicated with reference numeral.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " is directly connected to
To " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.Art can be used although should be understood that
Language first, second, third, etc. describes various component, assembly units, area, floor and/or part, these component, assembly units, area, floor and/or portion
Dividing should not be limited by these terms.These terms are used merely to distinguish a component, assembly unit, area, floor or part and another
Component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, component, area,
Floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and being used describe an elements or features shown in figure with it is other
The relationship of elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further include using and
The different orientation of device in operation.For example, if the device in attached drawing is overturn, then, it is described as " below other elements "
Or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
As described in the background art, with reference to figure 1, the relaxor of the prior art makes there are potential fast feedback loop
The frequency of oscillator determines by the delay of the high-speed feedback loop, and independent of the capacitance, reference current and benchmark of oscillator
Voltage.The present invention be directed to as relaxor such as shown in FIG. 1 there are the problem of, improved, propose that a kind of relaxation is shaken
Device is swung, including：Charge/discharge unit, charge/discharge unit, comparator unit and flip-flop element.
Wherein, the charge/discharge unit is arranged between current source and ground voltage.Illustratively, the charge/discharge unit example
Such as include the first capacitance and the second capacitance, first capacitance is arranged between current source and ground voltage, and second capacitance is set
It sets between current source and ground voltage.
The charge/discharge unit carries out periodical charge and discharge in order to control for the switch unit configuration.Illustratively, described to open
Unit is closed for example including first switch unit and second switch unit, and the first switch unit controls first capacitance and carries out
Periodical charge and discharge, the second switch unit control second capacitance and carry out periodical charge and discharge.
The comparator unit be configured to on the charge/discharge unit voltage and reference voltage be compared.It is exemplary
Ground, the comparator unit include first comparator and the second comparator, and the first comparator is configured to first electricity
Voltage and reference voltage in appearance are compared, and comparison result is exported to the first input end of the rest-set flip-flop；It is described
Second comparator arrangement be on second capacitance voltage and reference voltage be compared, and comparison result is exported to institute
State the second input terminal of rest-set flip-flop.
The output signal that the flip-flop element is configured to the comparator unit generates oscillator signal and exports extremely
The switch unit carries out periodical charge and discharge to control the charge/discharge unit, and illustratively, the flip-flop element is RS
The of trigger, the first output end and second output terminal outputting oscillation signal of the rest-set flip-flop, and the rest-set flip-flop
One output end and second output terminal are respectively connected to the first switch unit and second switch unit, to control first electricity
Hold and the second capacitance carries out periodical charge and discharge.
Wherein, the comparator unit uses hysteresis comparator, the hysteresis voltage Vh of the hysteresis comparator, the charge and discharge
The amplitude of oscillation voltage Vs of voltage signal on electric unit, the cycle T when relaxor work, when the reaction of the rest-set flip-flop
Between t meet：Vh ﹥ 2Vs × t/T.
Relaxor proposed by the present invention with hysteresis comparator by replacing common continuous comparator, relatively using sluggishness
Equivalent gain eliminates the self-excitation of potential fast feedback loop for 0 property when device is near hysteresis voltage, to improving relaxation
The stability of oscillator.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to illustrate this hair
The technical solution of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
Fig. 2 shows the illustrative circuitry structure charts of relaxor according to the present invention；Fig. 3 shows continuous comparator
It is illustrated with the input and output exemplary comparative of hysteresis comparator；Fig. 4 shows the exemplary input curve of output of hysteresis comparator；
Fig. 5 shows the meaning circuit structure diagram of hysteresis comparator according to the ... of the embodiment of the present invention.
Fig. 2 is please referred to, the relaxor 200 of the present embodiment includes：First capacitance C1, the second capacitance C2, first switch
Element N1, second switch element P1, third switch element N2, the 4th switch element P2, first comparator 201, the second comparator
202, rest-set flip-flop 203, current source and voltage source 204.
The first end of first capacitance C1 is connect by first switching element P1 with current source and voltage source 204, and described first
The second end of capacitance C1 is grounded GND, and second switch element is provided between the first end and second end of the first capacitance C1
N1.When the first switching element P1 is connected, the current source and voltage source 204 provide charging electricity for the first capacitance C1
Ir is flowed, the first capacitance C1 charges.When the second switch element N1 is connected, the first capacitance C1 discharges.
The first end of second capacitance C2 is connect by third switch element P2 with current source and voltage source 204, and described second
The second end of capacitance C2 is grounded GND, and the 4th switch element is provided between the first end and second end of the second capacitance C2
N2.When the third switch element P2 is connected, the current source and voltage source 204 provide charging electricity for the second capacitance C2
Ir is flowed, the second capacitance C2 charges.When the 4th switch element N2 is connected, the second capacitance C2 discharges.
Illustratively, in the present embodiment, first switching element P1 and third switch element P2 be PMOS transistor, second
Switch element N1 and the 4th switch element N2 is NMOS transistor.
The first input end (that is, inverting input) of first comparator 201 is connect with the first end of the first capacitance C1,
The second input terminal (that is, in-phase input end) of the first comparator 201 is connect with current source and voltage source 204.Current source and
Voltage source 204 is that first comparator 201 provides the voltage on reference voltage V r, the first capacitance C1, the i.e. voltage and base of node Va
Quasi- voltage Vr is compared, and comparison result is exported to the first input end of rest-set flip-flop 203.
The first input end (that is, inverting input) of second comparator 202 is connect with the first end of the second capacitance C2,
The second input terminal (that is, in-phase input end) of second comparator 202 is connect with current source and voltage source 204.Current source and
Voltage source 204 is that the second comparator 202 provides the voltage on reference voltage V r, the second capacitance C2, the i.e. voltage and base of node Vb
Quasi- voltage Vr is compared, and comparison result is exported to the second input terminal of rest-set flip-flop 203.
Rest-set flip-flop 203 includes illustratively the first phase inverter 2030 and the second phase inverter 2031, the first phase inverter 2030
Input terminal connect with the output end of the second phase inverter 2031, the input terminal of the second phase inverter 2031 and the first phase inverter 2030
Output end connects.The input terminal of first phase inverter 2030 is used as the first input end of rest-set flip-flop 203, the first phase inverter 2030
Output end is used as the first output end Qa of rest-set flip-flop 203, and the input terminal of the second phase inverter 2031 is used as rest-set flip-flop 2031
Second input terminal, the output end of the second phase inverter 2031 are used as the second output terminal Qb of rest-set flip-flop 203.
In the present embodiment, the first input end of rest-set flip-flop 203 and the second input terminal respectively with the first comparator
201 connect with the output end of the second comparator 202, and the first output end Qa and second output terminal Qb of the rest-set flip-flop 203 are used
In outputting oscillation signal, the first output end Qa and the first switching element P1 and the second switch member of the rest-set flip-flop 203
The control terminal (i.e. grid) of part N1 connects, described to control the conducting of the first switching element P1 and second switch element N1
The control terminal (i.e. grid) of the second output terminal Qb of rest-set flip-flop 203 and the third switch element P2 and the 4th switch element N2
Connection, to control the conducting of the third switch element P2 and the 4th switch element N2.
Current source and voltage source 204 provide charging current Ir for the first capacitance C1 and the second capacitance C2, are first comparator
201 and second comparator 202 provide the voltage of reference voltage V r, the first capacitance C1 and the second capacitance C2 and reference voltage V r is carried out
Compare, first comparator 201 and the second comparator 202 export comparison result to two input terminals of rest-set flip-flop 203, and RS is touched
Two output ends Qa and Qb for sending out device 203 are used for outputting oscillation signal, oscillator signal and the first switching element P1 of Qa outputs and
The grid of second switch element N1 connects, the grid of the oscillator signal and third switch element P2 and the 4th switch element N2 of Qb outputs
Pole connects, and realizes to the control to switch element P1, N1, P2, N2, to the charge and discharge of control the first capacitance C1 and the second capacitance C2
Electricity, to realize oscillator signal.
In the present embodiment, in order to avoid the self-excitation problem of potential fast feedback loop, the first comparator 201 and
Two comparators 202 are hysteresis comparator.Fig. 3 shows that common continuous comparator and hysteresis comparator believe identical input
Number, the comparison diagram of output signal.As soon as shown in figure 3, as input waveform Vinput, common continuous comparator is seen
Relationship between Vinput and 0 voltage, if Vinput is higher than 0, output Uo is just high；If Vinput is lower than 0, comparator is with regard to defeated
Go out low.Hysteresis comparator sees the relationship between threshold voltage u+, threshold voltage u- and Vinput, if Vinput compares threshold voltage
U- is also low, just output 0；If Vinput is also higher than threshold voltage u+, just output 1；If Vinput is in threshold voltage u- and door
Between voltage limit u+, then hold mode is constant.The maximum effect of hysteresis comparator is exactly to be used for filtering out certain input noise, no
As for allowing output saltus step back and forth near Vinput=0 of comparator.Hysteresis comparator is in threshold voltage u- and threshold voltage u+
Within when because output will not change, equivalent gain 0 does not have amplifier and acts on, and common comparator is near 0
Gain is larger.That is, as shown in figure 4, when input voltage is when hysteresis voltage model Vh encloses interior, the output of hysteresis comparator will not jump
Become.The relaxor of the present embodiment is exactly this characteristic using hysteresis comparator, and input is in threshold voltage u+ and thresholding electricity
When pressing near u-, hysteresis comparator does not have gain, so potential fast feedback loop self-excitation is not got up.
Further, in order to ensure that potential fast feedback loop does not generate self-excitation, the hysteresis voltage of the hysteresis comparator
Vh (hysteresis voltage Vh is equal to the difference of threshold voltage u+ and threshold voltage u-), the first capacitance C1 and the second capacitance C2 first ends
Signal amplitude of oscillation voltage (i.e. the amplitude of oscillation voltage of node Va and Vb) Vs, cycle T when relaxor work, the RS
Reaction time t of trigger meets：Vh ﹥ 2Vs × t/T.Wherein, the signal of the first capacitance C1 and the second capacitance C2 first ends
Amplitude of oscillation voltage (i.e. the amplitude of oscillation voltage of node Va and Vb) Vs refer to oscillator normal work when, Va and Vb place signal (generally
For triangular waveform) amplitude of oscillation voltage, relaxor normal work (do not have self-excitation problem, cycle T to depend on oscillating portion
The parameter of point device) when cycle T, the reaction time t of the rest-set flip-flop refers to that rest-set flip-flop is input to the delay of output.
In addition, various suitable circuit structures may be used in the hysteresis comparator in the present embodiment, the present invention is done not to this
Limitation, as long as its hysteresis voltage meets above-mentioned requirements.In general, hysteresis comparator includes comparator unit and positive feedback
Unit, it is that the comparator unit carries that the positive feedback unit, which is arranged between the input terminal and output end of the comparator unit,
For positive feedback, to realize hysteresis effect.
Fig. 5 shows the meaning circuit structure diagram of hysteresis comparator according to the ... of the embodiment of the present invention.As shown in figure 5, this implementation
The hysteresis comparator of example includes comparator module, positive feedback module and output driving module.
Comparator module includes differential comparator, the differential comparator include the first transistor to the 5th transistor M1~
The grid of M5, M1~M5, the first transistor M1 and second transistor M2 are used as two input terminals of the differential comparator,
Two input terminal VP and VN of the hysteresis comparator are also served as, the third transistor M3 provides tail for the difference amplifier
Electric current, loads of the 4th transistor M4 and the 5th transistor M5 as the difference amplifier.More specifically, the third is brilliant
The grid of body pipe M3 is connect with bias voltage Vbias, source electrode ground voltage Vss, and drain electrode is brilliant with the transistor M1 and second
The source electrode of body pipe M2 connects, to be that the transistor M1 and second transistor M2 provide tail under bias voltage Vbias effects
Electric current i3.The drain electrode of the one transistor M1 is connect with the drain electrode of the 4th transistor M4, the source electrode of the 4th transistor M4 and work
The drain electrode of voltage VDD connections, the two-transistor M2 is connect with the drain electrode of the 5th transistor M5, the source electrode of the 5th transistor M5 with
The drain electrode two as the differential comparator of operating voltage VDD connections, the transistor M1 and second transistor M2 are defeated
Outlet.
The positive feedback module includes the 6th and the 7th transistor M6, M7, and the positive feedback module is arranged in the difference
Between the input terminal and output end of comparator, for providing positive feedback for the differential comparator.The 6th transistor M6 with
The 4th transistor M4 is for forming current mirror, and the 7th transistor M7 and the 5th transistor M5 is for forming electric current
Mirror.Specifically, the source electrode of the 6th transistor M6 is connect with operating voltage VDD, the 6th transistor M6 and the described 4th
The grid of transistor M4 is connected to each other, the grid and drain electrode short circuit of the 4th transistor M4, and the 6th transistor M6
Drain electrode connect with the drain electrode of the second transistor M2.The source electrode of the 7th transistor M7 is connect with operating voltage VDD, institute
The grid for stating the 7th transistor M7 and the 5th transistor M5 is connected to each other, and the grid of the 5th transistor M5 and drain electrode are short
It connects, and the drain electrode of the 7th transistor M7 is connect with the drain electrode of the first transistor M1.
The output driving module includes the 8th to the 11st transistor M8~M11, the 8th transistor M8 and with the
Ten transistor M8 are connected in series between operating voltage VDD and ground voltage VSS, and the 8th transistor M8 and the described 4th
For transistor M4 for forming current mirror, the 9th transistor M9 and the 11st transistor M11 is connected in series in operating voltage VDD
Between ground voltage VSS, and the 9th transistor M 9 and the 5th transistor M 5 be for forming current mirror, and described the
11 transistor M 11 and the tenth transistor M 10 form current mirror, the leakage of the 9th M 9 and the 11st transistor M11
Pole is used as the output end vo ut of the hysteresis comparator.
Illustratively, in the present embodiment, described first, second, third, the ten, the 11st transistors are NMOS crystal
Pipe, the 4th to the 9th transistor are PMOS transistor.
The realization principle of the hysteresis comparator of the present embodiment is as follows：When the input VP of M1 is very high, when the input VN of M2 is very low,
When i.e. input difference voltage VP-VN is prodigious, M1 is opened at this time, and M2 is closed, and the tail current i3 that M3 is provided all is flowed through from M1,
Certainly the electric current i4 of M4 is same at this time, i.e. i4=i1=i3, and the electric current i6 of M6, M2, M5 and M7, i2, i5, i7 are 0.So
Afterwards as differential input voltage is gradually lifted, i.e., VP is gradually got higher, and when VN is gradually lower, the electric current of i6 slowly becomes since 0, this
I6 is equal to always i2 in the process, is all slowly becoming larger, and i5 and i7 are 0 always.When input difference voltage be lifted to one it is critical
Point, i.e., when the working condition of M6 becomes saturation region, i.e. i6=2*i4, the size of M4 and M6 have twice of relationship (the 6th crystal
Pipe the breadth length ratio of M6 is 2 times of the 4th transistor M4 breadth length ratios), it is exactly critical at this time when electric current is also 2 times of relationships
Point.When postcritical, M5 and M7 are opened rapidly, and instead of the function of M4 and M6, all micro-current i3 that M3 is provided at this time are then
M2 and M5 are all flowed through, output is reversed.
Hysteresis effect is exactly introduced by adding the positive feedback effect that two pipes of M6 and M7 generate.The ruler of M6 and M7
It is very little must must M4 and M5 it is big, otherwise just lose hysteresis effect.Exemplary, the breadth length ratio of the 6th transistor M6 is described the
2 times of four transistor M4 breadth length ratios；The breadth length ratio of the 7th transistor M7 is 2 times of the 5th transistor M5 breadth length ratios.
M8~M11 is simple current mirror, and the electric current of M4 and M5 is distinguished mirror image to M11 and M9, finally to approach electricity
The voltage vout outputs on source ground.
The dimension scale for depending mainly on the size of M4 and M6 of hysteresis voltage：Because of i1=i4, i2=i6, and i6=2*
I4, so i2=2*i1.The size of M1 and M2, all, only electric current has 2 times of relationships to VT, so according to metal-oxide-semiconductor saturation region electricity
Flow formula：I=0.5*W/L*K* (Vgs-VT) ^2, can calculate respective Vgs1 and Vgs2, at this time u+ and threshold voltage u+
As Vgs1-Vgs2.U+ and threshold voltage u- can be similarly released, because being holohedral symmetry relationship, u- and u+ are equal in magnitude, symbol
On the contrary, to obtain hysteresis voltage Vh by u+ and u-.
The relaxor that the present embodiment proposes utilizes sluggish ratio by replacing common continuous comparator with hysteresis comparator
Equivalent gain eliminates the self-excitation of potential fast feedback loop for 0 property when compared with device near hysteresis voltage, to improve
The stability of relaxation oscillator.
Embodiment two
Yet another embodiment of the present invention provides a kind of electronic device, including above-mentioned relaxor and with the relaxation
The electronic building brick of oscillator connection.
Wherein, the electronic building brick can be any electronic building bricks such as discrete device, integrated circuit.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products for including the semiconductor devices.
Wherein, Fig. 6 shows the example of mobile phone.The outside of mobile phone 600 is provided with the display portion being included in shell 601
602, operation button 603, external connection port 604, loud speaker 605, microphone 606 etc..
The electronic device of the embodiment of the present invention, since its relaxor having can eliminate self-excitation phenomena, and not
Can increase total output delay, thus the electronic device equally have the advantages that it is similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (12)
1. a kind of relaxor, which is characterized in that including：
Charge/discharge unit；
Switch unit, the charge/discharge unit carries out periodical charge and discharge in order to control for the switch unit configuration；
Comparator unit, the comparator unit be configured to on the charge/discharge unit voltage and reference voltage compare
Compared with；
Flip-flop element, the output signal that the flip-flop element is configured to the comparator unit generate oscillator signal simultaneously
Output carries out periodical charge and discharge to the switch unit, to control the charge/discharge unit；
Wherein, the comparator unit uses hysteresis comparator, the hysteresis voltage Vh of the hysteresis comparator, the charge and discharge list
The amplitude of oscillation voltage Vs of voltage signal, the cycle T when relaxor works, the reaction time of the flip-flop element in member
T meets：Vh ﹥ 2Vs × t/T.
2. relaxor according to claim 1, which is characterized in that
The charge/discharge unit includes the first capacitance and the second capacitance, and the switch unit includes that first switch unit and second open
Unit is closed, the comparator unit includes first comparator and the second comparator, and the flip-flop element is rest-set flip-flop；
First capacitance carries out periodical charge and discharge under the control of the first switch unit；
Second capacitance carries out periodical charge and discharge under the control of the second switch unit；
The first comparator be configured to on first capacitance voltage and reference voltage be compared, and by comparison result
It exports to the first input end of the rest-set flip-flop；
Second comparator arrangement be on second capacitance voltage and reference voltage be compared, and by comparison result
It exports to the second input terminal of the rest-set flip-flop；
The first output end and second output terminal outputting oscillation signal of the rest-set flip-flop, and the first of the rest-set flip-flop is defeated
Outlet and second output terminal are respectively connected to the first switch unit and second switch unit, with control first capacitance and
Second capacitance carries out periodical charge and discharge.
3. relaxor according to claim 2, which is characterized in that
The first switch unit includes first switching element and second switch element, and the first switch unit is configured to
The first capacitance charges described in when the first switching element is connected, in the second switch element conductive described in first
Capacitance discharges；
The second switch unit includes third switch element and the 4th switch element, and the second switch unit is configured in institute
Second capacitance described in when stating third switching elements conductive charges, in four switching elements conductive described in the second capacitance
It discharges；
The first input end of the first comparator is connect with the first end of first capacitance, and the second of the first comparator
Input terminal is connect with reference voltage；
The first input end of second comparator is connect with the first end of second capacitance, and the second of second comparator
Input terminal is connect with reference voltage；
First output end of the rest-set flip-flop is connect with the control terminal of the first switching element and the second switch element,
To control the conducting of the first switching element and the second switch element, the second output terminal of the rest-set flip-flop with it is described
Third switch element is connected with the control terminal of the 4th switch element, is opened with controlling the third switch element and the described 4th
Close the conducting of element.
4. relaxor according to claim 3, which is characterized in that the first switching element and third switch
Element is PMOS transistor；
The drain electrode of the first switching element is connect with the first end of first capacitance, the grid of the first switching element with
First output end of the rest-set flip-flop connects；
The drain electrode of the third switch element is connect with the first end of second capacitance, the grid of the third switch element with
The second output terminal of the rest-set flip-flop connects.
5. relaxor according to claim 3, which is characterized in that the second switch element and the 4th switch
Element is NMOS transistor；
The drain electrode of the second switch element is connect with the first end of first capacitance, the grid of the second switch element with
First output end of the rest-set flip-flop connects；
The drain electrode of 4th switch element is connect with the first end of second capacitance, the grid of the 4th switch element with
The second output terminal of the rest-set flip-flop connects.
6. relaxor according to claim 2, which is characterized in that the rest-set flip-flop includes the first phase inverter and the
Two phase inverters；
The input terminal of first phase inverter and the output end of the first comparator and the output end of first phase inverter
Connection；
The input terminal of second phase inverter and the output end of second comparator and the output end of first phase inverter
Connection.
7. according to the relaxor described in any one in claim 1-6, which is characterized in that the hysteresis comparator packet
Include comparator module and positive feedback module, the positive feedback module be arranged the comparator module input terminal and output end it
Between to provide positive feedback for the comparator module.
8. relaxor according to claim 7, which is characterized in that
The comparator module includes differential comparator, and the differential comparator includes the first transistor to the 5th transistor, institute
Two input terminals of the grid as the differential comparator of the first transistor and second transistor are stated, the third transistor is
The difference amplifier provides tail current, the load of the 4th transistor and the 5th transistor as the difference amplifier；
The positive feedback module includes the 6th transistor and the 7th transistor, and the 6th transistor and the 4th crystal are effective
In composition current mirror, and the drain electrode of the 6th transistor is connect with the drain electrode of the second transistor, the 7th crystal
Pipe is with the 5th transistor for forming current mirror, and the leakage of the drain electrode and the first transistor of the 7th transistor
Pole connects, and the 6th transistor and the 7th transistor are used to provide positive feedback for the differential comparator.
9. relaxor according to claim 8, which is characterized in that the breadth length ratio of the 6th transistor is described the
2 times of four transistor breadth length ratios；The breadth length ratio of 7th transistor is 2 times of the 5th transistor breadth length ratio.
10. relaxor according to claim 8, which is characterized in that the hysteresis comparator further includes output driving
Module,
The output driving module include the 8th transistor to the 11st transistor, the 8th transistor and with the tenth transistor
It is connected in series with, and the 8th transistor and the 4th transistor be for forming current mirror, the 9th transistor and the
11 transistors are connected in series with, and the 9th transistor and the 5th transistor be for forming current mirror, and the described tenth
With the tenth transistor for forming current mirror, the drain electrode of the 9th transistor and the 11st transistor is used as one transistor
The output end of the hysteresis comparator.
11. relaxor according to claim 10, which is characterized in that described first, second, third, the ten, the tenth
One transistor is NMOS transistor, and the 4th to the 9th transistor is PMOS transistor.
12. a kind of electronic device, which is characterized in that include the relaxor as described in any one in claim 1-11
And the electronic building brick being connect with the relaxor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710078531.6A CN108429548A (en) | 2017-02-14 | 2017-02-14 | A kind of relaxor and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710078531.6A CN108429548A (en) | 2017-02-14 | 2017-02-14 | A kind of relaxor and electronic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108429548A true CN108429548A (en) | 2018-08-21 |
Family
ID=63155232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710078531.6A Pending CN108429548A (en) | 2017-02-14 | 2017-02-14 | A kind of relaxor and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108429548A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111130534A (en) * | 2019-12-20 | 2020-05-08 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5638016A (en) * | 1995-04-18 | 1997-06-10 | Cyrix Corporation | Adjustable duty cycle clock generator |
| US7102452B1 (en) * | 2004-12-31 | 2006-09-05 | Zilog, Inc. | Temperature-compensated RC oscillator |
| US20090108948A1 (en) * | 2007-10-29 | 2009-04-30 | Samsung Electronics Co., Ltd | Relaxation oscillator for compensating system delay |
| CN202103633U (en) * | 2011-06-09 | 2012-01-04 | 东南大学 | Analog-digital mixed clock duty cycle calibration circuit |
| CN103312298A (en) * | 2013-07-05 | 2013-09-18 | 东南大学 | Relaxation oscillator for increasing frequency-control current linearity |
| CN103546123A (en) * | 2013-11-01 | 2014-01-29 | 东南大学 | High-linearity relaxation oscillator |
| CN103997317A (en) * | 2014-05-21 | 2014-08-20 | 东南大学 | Relaxation oscillator improving linearity of control current-output frequency significantly |
| CN102420591B (en) * | 2011-11-18 | 2014-08-20 | 上海复旦微电子集团股份有限公司 | Oscillator |
| CN104579254A (en) * | 2014-12-03 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Relaxation oscillator |
| CN106059538A (en) * | 2016-05-19 | 2016-10-26 | 深圳大学 | Relaxation oscillator with process deviation calibration function |
-
2017
- 2017-02-14 CN CN201710078531.6A patent/CN108429548A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5638016A (en) * | 1995-04-18 | 1997-06-10 | Cyrix Corporation | Adjustable duty cycle clock generator |
| US7102452B1 (en) * | 2004-12-31 | 2006-09-05 | Zilog, Inc. | Temperature-compensated RC oscillator |
| US20090108948A1 (en) * | 2007-10-29 | 2009-04-30 | Samsung Electronics Co., Ltd | Relaxation oscillator for compensating system delay |
| CN202103633U (en) * | 2011-06-09 | 2012-01-04 | 东南大学 | Analog-digital mixed clock duty cycle calibration circuit |
| CN102420591B (en) * | 2011-11-18 | 2014-08-20 | 上海复旦微电子集团股份有限公司 | Oscillator |
| CN103312298A (en) * | 2013-07-05 | 2013-09-18 | 东南大学 | Relaxation oscillator for increasing frequency-control current linearity |
| CN103546123A (en) * | 2013-11-01 | 2014-01-29 | 东南大学 | High-linearity relaxation oscillator |
| CN103997317A (en) * | 2014-05-21 | 2014-08-20 | 东南大学 | Relaxation oscillator improving linearity of control current-output frequency significantly |
| CN104579254A (en) * | 2014-12-03 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Relaxation oscillator |
| CN106059538A (en) * | 2016-05-19 | 2016-10-26 | 深圳大学 | Relaxation oscillator with process deviation calibration function |
Non-Patent Citations (3)
| Title |
|---|
| N. SOLTANI AND FEI YUAN: "《Remote frequency calibration of passive wireless microsensors and transponders using injection-locked phase-locked loop》", 《2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
| 苏文平: "《电子技术实践与制作教程》", 31 January 2007, 国防工业出版社 * |
| 高艳丽: "《一种DC-DC升压转换器的设计》", 《西北工业大学》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111130534A (en) * | 2019-12-20 | 2020-05-08 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
| CN111130534B (en) * | 2019-12-20 | 2024-03-01 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10425065B2 (en) | High-speed low-power-consumption trigger | |
| CN105391444B (en) | A kind of frequency dividing circuit and electronic device | |
| JPH08335873A (en) | Thermal insulation logic circuit | |
| CN205249160U (en) | Electronic equipment | |
| Mahato | Ultra low frequency CMOS ring oscillator design | |
| US9197198B2 (en) | Latch comparator circuits and methods | |
| CN108429548A (en) | A kind of relaxor and electronic device | |
| US8947146B2 (en) | Pulse-based flip flop | |
| CN101814907B (en) | Signal delay circuit and oscillator using signal delay circuit | |
| CN106612119A (en) | Comparator and analog-to-digital converter | |
| CN108736890A (en) | A kind of gradual approaching A/D converter and electronic device | |
| JPS5997220A (en) | Voltage comparing circuit | |
| CN113094022A (en) | Analog multiplier | |
| WO2019036177A1 (en) | Low-power low-duty-cycle switched-capacitor voltage divider | |
| US9679623B2 (en) | Stacked clock-generation circuit | |
| CN108494406A (en) | A kind of high speed dynamic latch type comparator, chip and communication terminal | |
| CN108649929A (en) | The Schmidt trigger of clock control and its application in latch | |
| US8975974B2 (en) | Low voltage, wide frequency range oscillator | |
| CN109285572A (en) | A kind of negative booster circuit, semiconductor devices and electronic device | |
| Wang et al. | Understanding dynamic behavior of mm-wave CML divider with injection-locking concept | |
| US20070241796A1 (en) | D-type static latch for high frequency circuit | |
| US6943608B2 (en) | Wide frequency range voltage-controlled oscillators (VCO) | |
| KR100384203B1 (en) | Ring Oscillator and Oscillation Method | |
| US20240072728A1 (en) | Oscillator circuit arrangement | |
| US6339346B1 (en) | Low skew signal generation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180821 |
|
| RJ01 | Rejection of invention patent application after publication |