CN211018782U

CN211018782U - Starting reset circuit for carrier band chip

Info

Publication number: CN211018782U
Application number: CN201921116575.4U
Authority: CN
Inventors: 蔡水河
Original assignee: Changzhou Xinsheng Semiconductor Technology Co ltd
Current assignee: Changzhou Xinsheng Semiconductor Technology Co ltd
Priority date: 2019-07-16
Filing date: 2019-07-16
Publication date: 2020-07-14
Anticipated expiration: 2029-07-16

Abstract

The utility model provides a carrier band chip is with start reset circuit, include: the device comprises a voltage division module, a primary voltage regulation module, an energy storage module and a secondary module; the voltage division module is suitable for dividing the voltage of the power supply and transmitting the voltage of the first node to the primary voltage regulation module; one end of the energy storage module is connected with the power supply, and the other end of the energy storage module is connected with a second node voltage between the primary voltage regulating module and the secondary module; when the power supply is started, the voltage of the first node rises along with the rise of the power supply so as to trigger the forward conduction of the primary voltage regulating module; after the primary voltage regulating module is conducted in the forward direction, the energy storage module starts to store energy, so that the voltage of the second node is gradually reduced to trigger the secondary module to be conducted in the reverse direction to output the power-on reset voltage.

Description

Starting reset circuit for carrier band chip

Technical Field

The utility model relates to a circuit design technical field especially relates to carrier band chip is with start reset circuit technical field.

Background

In the integrated circuit design, in order to avoid the power on reset signal (power on reset) from entering an unknown state (unknown state) in the circuit node (node) during the power on operation to cause malfunction or leakage, the internal node needs to be maintained at a predetermined voltage to enable the circuit to enter a predetermined state.

The conventional power-on reset circuit generates a power-on reset signal through two stages of inverters by using RC charging and discharging. As shown in the second diagram, which is a timing diagram of the conventional power-on reset circuit, when the power-on is started, the point V2 transits to ground due to the high input level (Vih) of the first stage flip-flop (formed by MP1 and MN 1) charged by the RC, and then the power-on reset signal (power on reset) can be generated by the first stage flip-flop (formed by MP2 and MN 2). However, the resistance value variation in the semiconductor process is quite large, which easily causes the initial voltage and reset time generated by the power-on reset signal to be inconsistent with the simulation (simulation). The high input level (Vih) of a general flip-flop depends on the threshold voltage (Vth) of a transistor, and the threshold voltage adjustable range of the transistor is too small to adjust the threshold voltage of the reset signal.

SUMMERY OF THE UTILITY MODEL

In order to overcome the problem that the threshold voltage of the transistor is too small to adjust the initial voltage of the reset signal, the present invention provides a power-on reset circuit for a carrier tape chip.

In order to solve the technical problem, the utility model provides a carrier band chip is with start reset circuit, include: the device comprises a voltage division module, a primary voltage regulation module, an energy storage module and a secondary module; the voltage division module is suitable for dividing the voltage of a power supply and transmitting the voltage of a first node to the primary voltage regulation module; one end of the energy storage module is connected with a power supply, and the other end of the energy storage module is connected with a second node voltage between the primary voltage regulating module and the secondary module; when the power supply is started, the voltage of the first node is suitable for rising along with the rising of the power supply so as to trigger the conduction of the first-stage voltage regulation module; after the first-level voltage regulating module is conducted, the energy storage module starts to store energy, so that the voltage of the second node is gradually reduced to trigger the second-level module to conduct and output the power-on reset voltage.

Further, the voltage dividing module includes: a resistor R1 and a resistor R2; the power supply is grounded through a resistor R1 and a resistor R2 in sequence, and the voltage between the resistor R1 and the resistor R2 is taken as the first node voltage.

Further, the primary voltage regulation module includes: a third NMOS transistor MN12, a fourth NMOS transistor MN11, and a fifth NMOS transistor MN 13; the grid electrode of the third NMOS tube MN12 is connected to the first node voltage, and the drain electrode of the third NMOS tube MN12 is connected to the secondary module; the grid electrode of the fourth NMOS transistor MN11 is connected to the first node voltage, and the source electrode of the fourth NMOS transistor MN11 is grounded; the source electrode of the third NMOS transistor MN12 is connected with the drain electrode of the fourth NMOS transistor MN11 and then is connected to the source electrode of the fifth NMOS transistor MN 13; and the drain electrode of the fifth NMOS tube MN13 is connected with a power supply, and the grid electrode of the fifth NMOS tube MN13 is connected with the secondary module.

Further, the secondary module comprises: a second PMOS transistor MP2 and a second NMOS transistor MN 2; the grid electrode of the second PMOS tube MP2 is connected to the output of the primary voltage regulation module, and the source electrode of the second PMOS tube MP2 is connected with a power supply; the grid electrode of the second NMOS transistor MN2 is connected to the output of the primary voltage regulation module, and the source electrode of the second NMOS transistor MN2 is grounded; and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the voltage between the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 is used as the power-on reset voltage or the power-off reset voltage.

Further, the tank circuit includes: an electrolytic capacitor; one end of the electrolytic capacitor is connected with a power supply, and the other end of the electrolytic capacitor is connected with the second node voltage.

Compared with the prior art, the beneficial effects of the utility model are that:

when the utility model is started, the first node voltage rises along with the rise of the power supply to trigger the forward conduction of the primary voltage adjusting module, and after the forward conduction of the primary voltage adjusting module, the energy storage module starts to store energy to gradually reduce the second node voltage so as to trigger the reverse conduction of the secondary module to output the power-on reset voltage; the energy storage module is set as an electrolytic capacitor, and the reset time can be set by adjusting the size of the electrolytic capacitance value; the utility model discloses set up resistance R1 and resistance R2 and carry out the partial pressure to power supply, and then can adjust the magnitude of voltage of input through the resistance size that changes resistance R1 and resistance R2, the utility model discloses a set up one-level voltage control module into first PMOS pipe MP1, third NMOS pipe MN12, fourth NMOS pipe MN11 and fifth NMOS pipe MN13, can heighten reset voltage, and not be limited to the influence of the transistor characteristic in the semiconductor processing procedure.

Drawings

FIG. 1 is a diagram of a conventional power-on reset circuit;

FIG. 2 is a timing diagram of a conventional power-on reset circuit;

fig. 3 is a circuit diagram of the power-on reset circuit of the present invention;

fig. 4 is a timing diagram of the power-on reset circuit of the present invention;

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

As shown in fig. 3-4, the present invention schematically shows a power-on reset circuit for a carrier tape chip, comprising: the device comprises a voltage division module, a primary voltage regulation module, an energy storage module and a secondary module; the voltage division module is suitable for dividing the voltage of a power supply and transmitting the voltage of a first node to the primary voltage regulation module; one end of the energy storage module is connected with a power supply, and the other end of the energy storage module is connected with a second node voltage between the primary voltage regulating module and the secondary module; when the power supply is started, the voltage of the first node is suitable for rising along with the rising of the power supply so as to trigger the conduction of the first-stage voltage regulation module; after the first-level voltage regulating module is conducted, the energy storage module starts to store energy, so that the voltage of the second node is gradually reduced to trigger the second-level module to conduct and output the power-on reset voltage.

The voltage division module includes: a resistor R1 and a resistor R2; the power supply is grounded through a resistor R1 and a resistor R2 in sequence, and the voltage between the resistor R1 and the resistor R2 is taken as the first node voltage.

The primary voltage regulation module includes: a first PMOS transistor MP1, a third NMOS transistor MN12, a fourth NMOS transistor MN11 and a fifth NMOS transistor MN 13; the grid electrode of the first PMOS pipe MP1 is connected to the first node voltage, and the source electrode of the first PMOS pipe MP1 is connected with a power supply; the grid electrode of the third NMOS tube MN12 is connected to the first node voltage, and the drain electrode of the third NMOS tube MN12 is connected to the secondary module; the grid electrode of the fourth NMOS transistor MN11 is connected to the first node voltage, and the source electrode of the fourth NMOS transistor MN11 is grounded; the source electrode of the third NMOS transistor MN12 is connected with the drain electrode of the fourth NMOS transistor MN11 and then is connected to the source electrode of the fifth NMOS transistor MN 13; the drain electrode of the fifth NMOS tube MN13 is connected with a power supply, and the grid electrode of the fifth NMOS tube MN13 is connected with the secondary module; the drain electrode of the first PMOS pipe MP1 and the drain electrode of the third NMOS pipe MN12 are both connected to the secondary module.

The secondary module comprises: a second PMOS transistor MP2 and a second NMOS transistor MN 2; the grid electrode of the second PMOS tube MP2 is connected to the output of the primary voltage regulation module, and the source electrode of the second PMOS tube MP2 is connected with a power supply; the grid electrode of the second NMOS transistor MN2 is connected to the output of the primary voltage regulation module, and the source electrode of the second NMOS transistor MN2 is grounded; and the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the voltage between the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 is used as the power-on reset voltage or the power-off reset voltage.

The tank circuit includes: an electrolytic capacitor; one end of the electrolytic capacitor is connected with a power supply, and the other end of the electrolytic capacitor is connected with the second node voltage.

The resistor R1 and the resistor R2 are not limited to passive resistors, but may be equivalent resistors of transistors.

As shown in fig. 3 and 4, a voltage dividing function of the resistor R2 and the electric group R1 is used to generate a required first voltage node V1, where V1 ═ VDD (R2/(R1+ R2)). When the power supply is turned on, when the voltage of the power supply VDD rises, the first voltage node V1 rises along with the rising of the power supply VDD, before the reset signal is not transited, the voltage of the second voltage node V2 is VDD, at this time, the fifth NMOS transistor MN13 is turned on, and the voltage of the voltage node VB is VDD-Vthmn 13. When the power supply VDD continues to rise and the voltage of the first voltage node V1 is greater than Vthmn12+ VB, the third NMOS transistor MN12 can turn on and turn to the ground, and the second voltage node V2 becomes the ground. Then passes through a second PMOS transistor MP2 in the secondary module (composed of a second PMOS transistor MP2 and a second NMOS transistor MN 2), and a power-on reset signal is generated. Therefore, by the utility model, we can change the high input level Vih of the reset circuit to Vthmn12+ VB, and the reset voltage can be adjusted high again by this method without being limited by the influence of the transistor characteristic Vth in the semiconductor process. When the high input level Vih is set higher, the reset time is also increased, and at this time, by reducing the capacitance of the electrolytic capacitor at the point of the second voltage node V2, the area of the integrated circuit can be effectively reduced, and the effect of reducing the cost is achieved.

When the utility model is started, the first node voltage rises along with the rise of the power supply to trigger the forward conduction of the primary voltage adjusting module, and after the forward conduction of the primary voltage adjusting module, the energy storage module starts to store energy to gradually reduce the second node voltage so as to trigger the reverse conduction of the secondary module to output the power-on reset voltage; the energy storage module is set as an electrolytic capacitor, and the reset time can be set by adjusting the size of the electrolytic capacitance value; the utility model discloses set up resistance R1 and resistance R2 and carry out the partial pressure to power supply, and then can adjust the voltage value of input through the resistance size that changes resistance R1 and resistance R2.

While the foregoing description shows and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not intended to be exhaustive or to exclude other embodiments and may be used in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.

Claims

1. A power-on reset circuit, comprising:

the device comprises a voltage division module, a primary voltage regulation module, an energy storage module and a secondary module; wherein

The voltage division module is suitable for dividing the voltage of a power supply and transmitting the voltage of a first node to the primary voltage regulation module;

one end of the energy storage module is connected with a power supply, and the other end of the energy storage module is connected with a second node voltage between the primary voltage regulating module and the secondary module;

when the power supply is started, the voltage of the first node is suitable for rising along with the rising of the power supply so as to trigger the conduction of the first-stage voltage regulation module;

after the primary voltage regulating module is conducted, the energy storage module starts to store energy, so that the voltage of the second node is gradually reduced to trigger the secondary module to conduct and output a power-on reset voltage;

the voltage division module includes: a resistor R1 and a resistor R2;

the power supply is grounded through a resistor R1 and a resistor R2 in sequence, and the voltage between the resistor R1 and the resistor R2 is used as the first node voltage;

the primary voltage regulation module includes: a third NMOS transistor MN12, a fourth NMOS transistor MN11, and a fifth NMOS transistor MN 13;

the grid electrode of the third NMOS tube MN12 is connected to the first node voltage, and the drain electrode of the third NMOS tube MN12 is connected to the secondary module;

the grid electrode of the fourth NMOS transistor MN11 is connected to the first node voltage, and the source electrode of the fourth NMOS transistor MN11 is grounded;

the source electrode of the third NMOS transistor MN12 is connected with the drain electrode of the fourth NMOS transistor MN11 and then is connected to the source electrode of the fifth NMOS transistor MN 13; and

the drain electrode of the fifth NMOS transistor MN13 is connected with the power supply, and the grid electrode of the fifth NMOS transistor MN13 is connected with the secondary module.

2. The power-on reset circuit of claim 1,

the secondary module comprises: a second PMOS transistor MP2 and a second NMOS transistor MN 2;

the grid electrode of the second PMOS tube MP2 is connected to the output of the primary voltage regulation module, and the source electrode of the second PMOS tube MP2 is connected with a power supply;

the grid electrode of the second NMOS transistor MN2 is connected to the output of the primary voltage regulation module, and the source electrode of the second NMOS transistor MN2 is grounded; and

the drain of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2, and the voltage between the drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 is used as a power-on reset voltage or a power-off reset voltage.

3. The power-on reset circuit of claim 2,

the energy storage module includes: an electrolytic capacitor;

one end of the electrolytic capacitor is connected with a power supply, and the other end of the electrolytic capacitor is connected with the second node voltage.