CN110189786B - Booster circuit applied to flash memory - Google Patents
Booster circuit applied to flash memory Download PDFInfo
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- CN110189786B CN110189786B CN201910311226.6A CN201910311226A CN110189786B CN 110189786 B CN110189786 B CN 110189786B CN 201910311226 A CN201910311226 A CN 201910311226A CN 110189786 B CN110189786 B CN 110189786B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention relates to a booster circuit applied to a flash memory, which relates to the design of a memory circuit, and is characterized in that a logic control module in the booster circuit generates a first control signal and a second control signal, and the first control signal and the second control signal control the booster circuit module to output a voltage of 3VDD-VTH, thereby meeting the requirement of the memory on higher driving voltage and improving the specification requirement on the reading speed of the memory.
Description
Technical Field
The present invention relates to memory circuit design, and more particularly, to a voltage boosting circuit applied to a flash memory.
Background
In today's System on a chip (SOC), non-volatile memory plays an important role, such as basic System memory requirements, sensor sensing, biomedical detection, touch applications, and so on. Common features of these product applications are extremely low operating frequencies and low power consumption targets for product standby mode (stand-by mode), and such a system will help reduce product demand for battery capacity and also help reduce product module size. In the design of a nonvolatile flash memory circuit, when the operating condition of a memory cell (bitcell) is higher than the potential of a power supply Voltage (VDD), a charge pump is a commonly used circuit type, and for example, a boost (boost) circuit is required to generate the potential when the high voltage requirement is applied to a word line (word-line) of the memory.
Referring to fig. 1, fig. 1 is a schematic diagram of a voltage boosting circuit applied to a flash memory voltage according to the prior art, as shown in fig. 1, the voltage boosting circuit includes a coupling capacitor CAP, and the capacitor CAP can charge a fixed voltage in the circuit to achieve the effect of boosting. The voltage of the conventional voltage boosting circuit can only be boosted to about 2 times of VDD, however, a memory cell (bitcell) in a memory generally needs a higher operating voltage, for example, a voltage higher than 2 times of VDD is needed.
Disclosure of Invention
The invention aims to provide a booster circuit applied to a flash memory, so as to meet the requirement of the memory on higher driving voltage and improve the specification requirement on the reading speed of the memory.
The invention provides a booster circuit applied to a flash memory, comprising: a logic control module, including an Enable signal terminal, a first clock signal terminal, a second clock signal terminal and a system Reset signal terminal, respectively for receiving an Enable signal Enable, a first clock signal Clk1, a second clock signal Clk2 and a system Reset signal Reset, and including a first control signal terminal for outputting a first control signal In and a second control signal terminal for outputting a second control signal Inb; and a boost circuit module, including a third P-type power switch MP3, a source terminal S of the third P-type power switch MP3 being connected to the supply voltage VDD, a drain terminal D of the third P-type power switch MP3 being connected to the first terminal of the first capacitor CAP1 and to the gate terminal G of the third P-type power switch MP3, a second terminal of the first capacitor CAP1 being connected to the second control signal terminal Inb of the logic control module, a first terminal of the first capacitor CAP1 being further connected to the drain terminal D of the fourth P-type power switch MP4, the second control signal terminal Inb being further connected to the gate terminal G of the first N-type power switch MN1 and the gate terminal G of the first P-type power switch MP1, the source terminal S of the first P-type power switch MP1 being connected to the supply voltage VDD, the drain terminal S of the first N-type power switch MN1 being grounded, the drain terminal D of the first N-type power switch MN1 being connected to the drain terminal MP 56D of the first N-type power switch MP1, so that the first N-type power switch MN1 and the first P-type power switch MP1 form a first inverter, the gate G of the first N-type power switch MN1 and the gate G of the first P-type power switch MP1 form the input terminal of the first inverter to receive the second control signal Inb, the drain D of the first N-type power switch MN1 and the drain D of the first P-type power switch MP1 form the output terminal of the first inverter to output the control signal Pull _ down, the output terminal of the first inverter is connected to the gate G of the fourth P-type power switch MP4 and the gate G of the third N-type power switch MN3, so that the fourth P-type power switch MP4 and the third N-type power switch MN3 receive the control signal Pull _ down, the S of the third N-type power switch MN3 is grounded, the drain source terminal of the third N-type power switch MN 3D is connected to the drain source terminal of the fourth N-type power switch MP4, and connected to the first terminal of the second capacitor CAP2, the first control signal terminal In of the logic control module is connected to the gate terminal G of the second N-type power switch MN2 and the gate terminal G of the second P-type power switch MP2, the source terminal S of the second P-type power switch MP2 is connected to the second terminal of the second capacitor CAP2, the source terminal S of the second N-type power switch MN2 is grounded, the drain terminal D of the second N-type power switch MN2 is connected to the drain terminal D of the second P-type power switch MP2, so that the second N-type power switch MN2 and the second P-type power switch MP2 form a second inverter, the gate terminal G of the second N-type power switch MN2 and the gate terminal G of the second P-type power switch MP2 form an input terminal of the second inverter to receive the first control signal In, the drain terminal D of the second N-type power switch MN2 and the gate terminal P-type power switch MP2 form a drain terminal Ctrl _ P _ signal output terminal of the second inverter 2, the output end of the second inverter is connected to the gate G of the fifth P-type power switch MP5, so that the fifth P-type power switch MP5 receives the control signal Ctrl _ P, the source end S of the fifth P-type power switch MP5 is connected to the power supply voltage VDD, the drain end D of the fifth P-type power switch MP5 is connected to the second end of the second capacitor CAP2, and the second end of the second capacitor CAP2 constitutes the output end of the boost circuit applied to the flash memory.
Furthermore, the second N-type power switch MN2, the second P-type power switch MP2, the fifth P-type power switch MP5 and the fourth P-type power switch MP4 are high voltage pass transistors.
Furthermore, the withstand voltage of the high-voltage transmission transistor is larger than the power supply voltage VDD.
Furthermore, the withstand voltage of the high-voltage transmission transistor is less than 10V.
Furthermore, the withstand voltage of the first N-type power switch MN1, the third N-type power switch MN3, the first P-type power switch MP1 and the third P-type power switch MP3 is between 0V and the power supply voltage VDD.
Furthermore, the first P-type power switch MP1, the second P-type power switch MP2, the third P-type power switch MP3, the fourth P-type power switch MP4 and the fifth P-type power switch MP5 are PMOS.
Furthermore, the first N-type power switch MN1, the second N-type power switch MN2, and the third N-type power switch MN3 are NMOS.
Furthermore, the boosting circuit applied to the flash memory is integrated in a semiconductor substrate.
Furthermore, the boost circuit applied to the flash memory is integrated in a semiconductor substrate by applying a CMOS process.
Further, the logic control module comprises: a first not gate and a second not gate, wherein the input end of the first not gate receives an Enable signal Enable, the output end of the first not gate is connected with the input end of the second not gate, the output end of the second not gate is connected with the first input end of the first NAND gate, the NAND gate further comprises a first NOR gate, the first input end of the first NOR gate receives a second clock signal Clk2, the second input end of the first NOR gate receives a system Reset signal Reset, the NAND gate further comprises a second NAND gate and a third NAND gate, the first input end of the second NAND gate receives a first clock signal Clk1, the first input end of the third NAND gate is connected with the output end of the first NOR gate, the second input end of the third NAND gate is connected with the output end of the second NAND gate, the output end of the second NAND gate is connected with the second input end of the first NAND gate, and the output end of the first NAND gate outputs a first control signal In, and the output end of the first NAND gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected with the input end of the fifth NOT gate, and the output end of the fifth NOT gate outputs a second control signal Inb.
According to the booster circuit applied to the flash memory, the logic control module in the booster circuit generates the first control signal and the second control signal, and the booster circuit module outputs the voltage of 3VDD-VTH under the control of the first control signal and the second control signal, so that the requirement of the memory on higher driving voltage is met, and the specification requirement on the reading speed of the memory can be improved.
Drawings
FIG. 1 is a schematic diagram of a prior art boosting circuit applied to a flash memory.
Fig. 2 is a schematic diagram of a boosting circuit applied to a flash memory according to an embodiment of the invention.
Fig. 3 is an internal schematic diagram of the logic control module shown in fig. 2.
Fig. 4 is a waveform diagram illustrating an operation of the boosting circuit applied to the flash memory shown in fig. 2.
Fig. 5 is a schematic view of a load for simulation.
The reference symbols used in the drawings are explained below:
100. a logic control module; 200. and a booster circuit module.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a voltage boosting circuit applied to a flash memory is provided. Specifically, referring to fig. 2, fig. 2 is a schematic diagram of a voltage boosting circuit applied to a flash memory according to an embodiment of the present invention. As shown in fig. 2, the boosting circuit applied to the flash memory includes: logic Control module (Logic Control)100 and boost circuit module 200, wherein Logic Control module 100 includes: an Enable signal terminal (Enable), a first clock signal terminal Clk1, a second clock signal terminal Clk2 and a system Reset signal terminal Reset for receiving the Enable signal Enable, the first clock signal Clk1, the second clock signal Clk2 and the system Reset signal Reset, respectively, and including a first control signal terminal In for outputting a first control signal In and a second control signal terminal Inb for outputting a second control signal Inb; the booster circuit module 200 includes: a third P-type power switch tube MP3, a source terminal S of the third P-type power switch tube MP3 is connected to the power supply voltage VDD, a drain terminal D of the third P-type power switch tube MP3 is connected to the first terminal of the first capacitor CAP1 and is connected to the gate terminal G of the third P-type power switch tube MP3, a second terminal of the first capacitor CAP1 is connected to the second control signal terminal Inb of the logic control module 100, the first terminal of the first capacitor CAP1 is further connected to the drain terminal D of the fourth P-type power switch tube MP4, the second control signal terminal Inb is further connected to the gate terminal G of the first N-type power switch tube MN1 and the gate terminal G of the first P-type power switch tube MP1, the source terminal of the first P-type power switch tube MP1 is connected to the power supply voltage VDD, the gate terminal S of the first N-type power switch tube MN1 is grounded, the drain terminal D of the first N-type power switch tube MN1 is connected to the first P-type power switch tube MP 8945 to form a drain terminal MP1, the gate G of the first N-type power switch tube MN1 and the gate G of the first P-type power switch tube MP1 form the input end of the first inverter to receive the second control signal Inb, the drain D of the first N-type power switch tube MN1 and the drain D of the first P-type power switch tube MP1 form the output end of the first inverter to output the control signal Pull down, the output end of the first inverter is connected with the gate G of the fourth P-type power switch tube MP4 and the gate G of the third N-type power switch tube MN3, so that the fourth P-type power switch tube MP4 and the third N-type power switch tube MN3 receive the control signal Pull down, the drain D of the third N-type power switch tube MN3 is grounded, the drain D of the third N-type power switch tube MN3 is connected with the gate S of the fourth P-type power switch tube MP4, the gate G of the second capacitor MN2, the gate G of the first N-type power switch tube MP1 is connected with the gate G of the gate of the second N-type power switch tube MN2, a source terminal S of the second P-type power switch MP2 is connected to the second terminal of the second capacitor CAP2, a source terminal S of the second N-type power switch MN2 is grounded, a drain terminal D of the second N-type power switch MN2 is connected to the drain terminal D of the second P-type power switch MP2, such that the second N-type power switch MN2 and the second P-type power switch MP2 form a second inverter, a gate G of the second N-type power switch MN2 and a gate G of the second P-type power switch MP2 form an input terminal of the second inverter to receive the first control signal In, a drain terminal D of the second N-type power switch MN2 and the drain terminal D of the second P-type power switch MP2 form an output terminal of the second inverter to output the control signal Ctrl _ P, an output terminal of the second inverter is connected to a gate G of the fifth P-type power switch MP5, such that the fifth P-type power switch MP5 receives the control signal Ctrl _ P, and the source terminal S of the fifth P-type power switch MP5 is connected to the power supply voltage VDD, the drain terminal D of the fifth P-type power switch MP5 is connected to the second terminal of the second capacitor CAP2, and the second terminal of the second capacitor CAP2 constitutes the output terminal of the boost circuit applied to the flash memory.
In an embodiment of the invention, the second N-type power switch MN2, the second P-type power switch MP2, the fifth P-type power switch MP5 and the fourth P-type power switch MP4 are high voltage pass transistors. More specifically, in an embodiment of the present invention, the withstand voltage of the high voltage pass transistor is greater than the power supply voltage VDD. Furthermore, in an embodiment of the present invention, the withstand voltage of the high voltage pass transistor is less than 10V.
In an embodiment of the invention, the withstand voltage of the first N-type power switch MN1, the third N-type power switch MN3, the first P-type power switch MP1 and the third P-type power switch MP3 is between 0V and the power supply voltage VDD.
In an embodiment of the invention, the first P-type power switch MP1, the second P-type power switch MP2, the third P-type power switch MP3, the fourth P-type power switch MP4 and the fifth P-type power switch MP5 are PMOS transistors.
In an embodiment of the invention, the first N-type power switch MN1, the second N-type power switch MN2, and the third N-type power switch MN3 are NMOS.
In an embodiment of the invention, the boosting circuit applied to the flash memory is integrated in a semiconductor substrate. More specifically, in an embodiment of the present invention, the boost circuit applied to the flash memory is integrated in a semiconductor substrate by using a CMOS process.
Referring to fig. 3 again, fig. 3 is an internal schematic view of the logic control module shown in fig. 2, and as shown in fig. 3, the logic control module includes: a first not gate 111 and a second not gate 112, an input terminal of the first not gate 111 being an Enable signal terminal of the logic control module for receiving an Enable signal Enable, an output terminal of the first not gate 111 being connected to an input terminal of the second not gate 112, an output terminal of the second not gate 112 being connected to a first input terminal of the first nand gate 121, further comprising a first nor gate 130, a first input terminal of the first nor gate 130 receiving the second clock signal Clk2, a second input terminal of the first nor gate 130 receiving the system Reset signal Reset, further comprising a second nand gate 122 and a third nand gate 123, a first input terminal of the second nand gate 122 receiving the first clock signal Clk1, a first input terminal of the third nand gate 123 being connected to an output terminal of the first nor gate 130, a second input terminal of the third nand gate 123 being connected to an output terminal of the second nand gate 122, a second input terminal of the second nand gate 122 being connected to an output terminal of the third nand gate 123, and the output end of the second nand gate 122 is connected to the second input end of the first nand gate 121, the output end of the first nand gate 121 outputs the first control signal In, the output end of the first nand gate 121 is connected to the input end of the third not gate 113, the output end of the third not gate 113 is connected to the input end of the fourth not gate 114, the output end of the fourth not gate 114 is connected to the input end of the fifth not gate 115, and the output end of the fifth not gate 115 outputs the second control signal Inb.
In an embodiment of the present invention, Clk1, Clk2 and Reset signal form a Set-Reset flip-flop with active low, and the logic control module 100 controls the generation of the first control signal In and the second control signal Inb for the following boost circuit module 200. Specifically, referring to fig. 4, fig. 4 is a waveform diagram of the operation of the voltage boost circuit applied to the flash memory shown in fig. 2, wherein the Clk1, Clk2, Reset and Enable signals are all low-voltage logic signals (0)～VDD). As shown in fig. 4, where Vboost _ stage0 represents the potential of the first terminal of the first capacitor CAP1, Vboost _ stage1 represents the potential of the first terminal of the second capacitor CAP2, and Vboost represents the potential of the second terminal of the second capacitor CAP 2. First, since the third P-type power switch tube MP3 is diode-connected, the third P-type power switch tube MP3 is a normally-open tube, and Vboost _ stage0 is precharged to a potential of about VDD-VTH (where VTH is the threshold voltage of the third P-type power switch tube MP 3) via the normally-open third P-type power switch tube MP 3. At time t1, when the Enable signal Enable is changed to high level, the logic control module 100 starts to work; at time t2, logic control module 100 is connectedThe received first clock signal terminal Clk1 is converted from high level to low level, i.e. a pulse width signal is generated, at this time, the second clock signal terminal Clk2 is still at low level, the logic control module 100 obtains a first control signal In at low level and a second control signal Inb at high level, and obtains a control signal Ctrl _ P at high level and a control signal Pull _ down at low level after passing through the first inverter and the second reactor, the second control signal Inb at high level raises the second terminal of the first capacitor CAP1 to the potential of VDD, and simultaneously raises the potential of Vboost _ stage0 to the potential of 2VDD-VTH, and simultaneously the control signal Pull _ down at low level drives the fourth P-type power switch MP4 to be turned on, so that the potential of Vboost _ stage1 is equal to the potential of Vboost _ stage0 and is equal to the potential of 2-VTH, and at the previous time of t2, i.e. a previous clock time, i.e. a previous clock cycle 4, is as a previous time, the first clock signal terminal Clk1 is at high level, the second clock signal terminal Clk2 is at low level, the logic control module 100 obtains the first control signal In at high level and the second control signal Inb at low level, and the first inverter and the second reactor obtain the control signal Ctrl _ P at low level and the control signal Pull _ down at high level, the control signal Ctrl _ P at low level drives the fifth P-type power switch MP5 to turn on, the second terminal of the second capacitor CAP2 is raised to VDD, and is kept at the next clock cycle, therefore, at time t2, the first terminal of the second capacitor CAP2 is raised to 2VDD-VTH, the second terminal of the second capacitor CAP2, namely Vboost, is raised to 3VDD-VTH, the boost circuit applied to the flash memory outputs 3-VDD-VTH voltage, and the state is kept at time t3, before time t3, the first clock signal terminal Clk1 and the second clock signal terminal Clk2 are inverted, the first control signal In and the second control signal Inb are inverted at time t3, the control signal Pull _ down and the control signal Ctrl _ P are inverted, as shown before, In the operating state before time t4, the potential of Vboost is VDD, and Vboost _ stage1 is equal to Vboost _ stage0 and VDD-VTH, and the operating state is maintained until the next clock cycle, for example, time t4 comes. As shown in FIG. 4, t 2-t 4 are one clock cycle, which is sequentially the second and third … … clock cycles, and the operation process is not repeated as the first time cycleAnd will be described in detail.
That is, Vboost _ stage0 is precharged to a potential of about VDD-VTH via the diode-connected third P-type power switching tube MP 3. Then, the logic circuit control module generates a first control signal In and a second control signal Inb, which will raise the voltage level of Vboost _ stage0 to 2VDD-VTH via a first capacitor CAP 1. Meanwhile, the fourth P-type power switch MP4 is turned on by the Pull-down of the control signal Pull _ down, the potential of Vboost _ stage1 is also transferred and charged to 2VDD-VTH, and the potential of 2VDD-VTH is charged to the Vboost port via the second capacitor CAP2, so that the potential of the Vboost port is boosted and charged to the voltage of 3VDD-VTH at this time. More specifically, the first capacitor CAP1 is a MOS capacitor controlled by the second control signal Inb to complete the coupling and transmission of the high frequency signal, and the first capacitor CAP1 charges the potential of Vboost _ stage 0. The second capacitor CAP2 is a MOS capacitor controlled by the Vboost _ stage1 signal to generate a voltage boost function for the Vboost terminal. Under the condition that the Vboost port has no load, the booster circuit can be charged to the potential of about 3 multiplied by VDD-VTH, and can complete the functions of driving the load and the switch of the post-stage circuit.
Specifically, the prior art boost circuit shown in fig. 1 was simulated, and the boost circuit of the present invention shown in fig. 2 was simulated to verify that the power switches in the two circuit architectures were identically sized. The signal periods of the first clock signal Clk1 and the second clock signal Clk2 are 90ns, the duty ratio of the first clock signal Clk1 is 16.67%, and the duty ratio of the second clock signal Clk2 is 5.6%. The Vboost voltage of the boost circuit was measured, and the potential stability of the periodic boost was evaluated, to obtain the simulation results of the boost circuit of the prior art shown in table 1 and the simulation results of the boost circuit of the present invention shown in table 2. No.1/2/40/80 in the table represents the Vboost potential boosting condition in the 1 st clock cycle, 2 nd clock cycle, 40 th clock cycle, and 80 th clock cycle. From the simulation results, the boosting circuit of the invention can well complete the function of potential boosting, the voltage of Vboost reaches the voltage of about 3VDD-VTH under the condition of unloaded (no load), the boosting efficiency is 80.6 percent under the condition of the load of a later stage circuit, and the boosting function of the boosting circuit of the prior art can only reach 2 times of VDD (no load) at most. Fig. 5 is a schematic diagram of a load for simulation, and as shown in fig. 5, a post-stage circuit at the Vboost end is an RC load, and an equivalent load of the post-stage circuit at the Vboost end is: r300 Ω, C4 pF. The setup time (rise time) and fall time (fall time) of both circuits can be kept below 3 ns.
Table 1 shows simulation results of the boost circuit of the prior art
Table 2 shows simulation results of the boosting circuit of the present invention
From the simulation results, when the operating voltage requirement of the memory cell in the memory is greater than 2 times the VDD voltage, the boost circuit of the present invention can better solve the generation requirement of the voltage, so as to meet the operating requirement of the memory. The booster circuit of the present invention can be used for driving a logic decoder (blcok decoder) and an array driver (array driver) in a memory, and can also raise specification requirements for the read speed of the memory.
In summary, the logic control module in the boost circuit generates the first control signal and the second control signal, and the boost circuit module outputs the voltage of 3VDD-VTH under the control of the first control signal and the second control signal, so that the requirement of the memory on higher driving voltage is met, and the specification requirement on the reading speed of the memory can be improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A boost circuit for use in a flash memory, comprising:
a logic control module, including an Enable signal terminal, a first clock signal terminal, a second clock signal terminal and a system Reset signal terminal, respectively for receiving an Enable signal Enable, a first clock signal Clk1, a second clock signal Clk2 and a system Reset signal Reset, and including a first control signal terminal for outputting a first control signal In and a second control signal terminal for outputting a second control signal Inb; and
the booster circuit module comprises a third P-type power switch tube MP3, a source end S of the third P-type power switch tube MP3 is connected with a power supply voltage VDD, a drain end D of the third P-type power switch tube MP3 is connected with a first end of a first capacitor CAP1 and is connected with a gate electrode G of a third P-type power switch tube MP3, a second end of the first capacitor CAP1 is connected with a second control signal end Inb of the logic control module, a first end of the first capacitor CAP1 is also connected with a drain end D of a fourth P-type power switch tube MP4, the second control signal end Inb is also connected with a gate electrode G of a first N-type power switch tube MN1 and a gate electrode G of a first P-type power switch tube MP1, the source end S of the first P-type power switch tube MP1 is connected with the power supply voltage, the gate electrode S of the first N-type power switch tube MN1 is grounded, the drain end D of the first N-type power switch tube MN1 is connected with the first switch tube MP 8945 to form a drain end MP1 and a first N-type power switch tube, the gate G of the first N-type power switch tube MN1 and the gate G of the first P-type power switch tube MP1 form the input end of the first inverter to receive the second control signal Inb, the drain D of the first N-type power switch tube MN1 and the drain D of the first P-type power switch tube MP1 form the output end of the first inverter to output the control signal Pull down, the output end of the first inverter is connected with the gate G of the fourth P-type power switch tube MP4 and the gate G of the third N-type power switch tube MN3, so that the fourth P-type power switch tube MP4 and the third N-type power switch tube MN3 receive the control signal Pull down, the drain D of the third N-type power switch tube MN3 is grounded, the drain D of the third N-type power switch tube MN3 is connected with the gate S of the fourth P-type power switch tube MP4, the gate G of the second capacitor MN2, the gate G of the first N-type power switch tube MP1 is connected with the gate G of the gate of the second N-type power switch tube MN2, a source terminal S of the second P-type power switch MP2 is connected to the second terminal of the second capacitor CAP2, a source terminal S of the second N-type power switch MN2 is grounded, a drain terminal D of the second N-type power switch MN2 is connected to a drain terminal D of the second P-type power switch MP2, such that the second N-type power switch MN2 and the second P-type power switch MP2 constitute a second inverter, a gate G of the second N-type power switch MN2 and a gate G of the second P-type power switch MP2 constitute an input terminal of the second inverter to receive the first control signal In, a drain terminal D of the second N-type power switch MN2 and a drain terminal D of the second P-type power switch MP2 constitute an output terminal of the second inverter to output the control signal Ctrl _ P, an output terminal of the second inverter is connected to a gate G of the fifth P-type power switch MP5, such that the fifth P-type power switch MP5 receives the fifth P-type power switch voltage, the fifth P-type power switch MP 46 5 receives the fifth P power switch voltage, the drain terminal D of the fifth P-type power switch MP5 is connected to the second terminal of the second capacitor CAP2, and the second terminal of the second capacitor CAP2 constitutes the output terminal of the boost circuit applied to the flash memory.
2. The booster circuit as claimed in claim 1, wherein the second N-type power switch MN2, the second P-type power switch MP2, the fifth P-type power switch MP5 and the fourth P-type power switch MP4 are high voltage pass transistors.
3. The booster circuit applied to the flash memory according to claim 2, wherein the withstand voltage of the high voltage pass transistor is greater than the power supply voltage VDD.
4. The booster circuit applied to the flash memory according to claim 3, wherein the withstand voltage of the high voltage pass transistor is less than 10V.
5. The booster circuit of claim 1, wherein the withstand voltage of the first N-type power switch MN1, the third N-type power switch MN3, the first P-type power switch MP1 and the third P-type power switch MP3 is between 0V and a power supply voltage VDD.
6. The booster circuit as claimed in claim 1, wherein the first P-type power switch MP1, the second P-type power switch MP2, the third P-type power switch MP3, the fourth P-type power switch MP4 and the fifth P-type power switch MP5 are PMOS.
7. The booster circuit as claimed in claim 1, wherein the first N-type power switch MN1, the second N-type power switch MN2, and the third N-type power switch MN3 are NMOS.
8. The booster circuit applied to the flash memory according to claim 1, wherein the booster circuit applied to the flash memory is integrated in a semiconductor substrate.
9. The booster circuit applied to the flash memory according to claim 8, wherein the booster circuit applied to the flash memory is integrated in a semiconductor substrate using a CMOS process.
10. The booster circuit of claim 1, wherein the logic control module comprises: a first not gate and a second not gate, wherein the input end of the first not gate receives an Enable signal Enable, the output end of the first not gate is connected with the input end of the second not gate, the output end of the second not gate is connected with the first input end of the first NAND gate, the NAND gate further comprises a first NOR gate, the first input end of the first NOR gate receives a second clock signal Clk2, the second input end of the first NOR gate receives a system Reset signal Reset, the NAND gate further comprises a second NAND gate and a third NAND gate, the first input end of the second NAND gate receives a first clock signal Clk1, the first input end of the third NAND gate is connected with the output end of the first NOR gate, the second input end of the third NAND gate is connected with the output end of the second NAND gate, the output end of the second NAND gate is connected with the second input end of the first NAND gate, and the output end of the first NAND gate outputs a first control signal In, and the output end of the first NAND gate is connected with the input end of the third NOT gate, the output end of the third NOT gate is connected with the input end of the fourth NOT gate, the output end of the fourth NOT gate is connected with the input end of the fifth NOT gate, and the output end of the fifth NOT gate outputs a second control signal Inb.
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| CN201910311226.6A CN110189786B (en) | 2019-04-18 | 2019-04-18 | Booster circuit applied to flash memory |
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| CN201910311226.6A CN110189786B (en) | 2019-04-18 | 2019-04-18 | Booster circuit applied to flash memory |
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| CN110189786B true CN110189786B (en) | 2020-10-02 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6930536B2 (en) * | 2003-11-04 | 2005-08-16 | Micron Technology, Inc. | Voltage booster |
| CN101127479A (en) * | 2006-08-16 | 2008-02-20 | 天时电子股份有限公司 | Voltage increase circuit for elevated voltage charge |
| CN101286696A (en) * | 2007-02-07 | 2008-10-15 | 松下电器产业株式会社 | Booster circuit |
| CN102342006A (en) * | 2009-12-03 | 2012-02-01 | 松下电器产业株式会社 | Semiconductor integrated circuit and step-up circuit having same |
| CN102857098A (en) * | 2011-06-27 | 2013-01-02 | 华邦电子股份有限公司 | Boosting circuit |
| CN207475404U (en) * | 2017-11-16 | 2018-06-08 | 上扬无线射频科技扬州有限公司 | Charge pump compress cell circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5342324B2 (en) * | 2009-05-26 | 2013-11-13 | ルネサスエレクトロニクス株式会社 | Booster circuit |
-
2019
- 2019-04-18 CN CN201910311226.6A patent/CN110189786B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6930536B2 (en) * | 2003-11-04 | 2005-08-16 | Micron Technology, Inc. | Voltage booster |
| CN101127479A (en) * | 2006-08-16 | 2008-02-20 | 天时电子股份有限公司 | Voltage increase circuit for elevated voltage charge |
| CN101286696A (en) * | 2007-02-07 | 2008-10-15 | 松下电器产业株式会社 | Booster circuit |
| CN102342006A (en) * | 2009-12-03 | 2012-02-01 | 松下电器产业株式会社 | Semiconductor integrated circuit and step-up circuit having same |
| CN102857098A (en) * | 2011-06-27 | 2013-01-02 | 华邦电子股份有限公司 | Boosting circuit |
| CN207475404U (en) * | 2017-11-16 | 2018-06-08 | 上扬无线射频科技扬州有限公司 | Charge pump compress cell circuit |
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| CN110189786A (en) | 2019-08-30 |
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