CN101127479A - Voltage increase circuit for elevated voltage charge - Google Patents
Voltage increase circuit for elevated voltage charge Download PDFInfo
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- CN101127479A CN101127479A CNA2006101157778A CN200610115777A CN101127479A CN 101127479 A CN101127479 A CN 101127479A CN A2006101157778 A CNA2006101157778 A CN A2006101157778A CN 200610115777 A CN200610115777 A CN 200610115777A CN 101127479 A CN101127479 A CN 101127479A
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Abstract
The utility model relates to an electric charge boosting circuit, comprising a plurality of diode equivalent networks, at least a boosting capacitance network and at least one reverse current cut-off circuit; wherein the diode equivalent networks are electrically connected in series with each other; a node is arranged between every two diode equivalent networks and each node is responding to a boosting stage; the low-voltage side of the diode equivalent network with the lowest boosting stage is the input of the electric charge boosting circuit and the input receives an input voltage signal; one end of each boosting capacitance network is connected with a node and the other end of each boosting capacitance network is electrically connected with a clock signal; each reverse current cut-off circuit is electrically connected with the diode equivalent network; the reverse current cut-off circuit is provided with at least two break-over channels, which are alternately turned on according to the clock signal switch in each boosting stage.
Description
Technical field
The invention relates to a kind of electric charge boost pressure circuit, refer to a kind of especially by the electric charge boost pressure circuit of reverse current cut-off circuit with lifting circuit efficiency and reliability.
Background technology
Electric charge boost pressure circuit (Charge Pump) is a kind of by the circuit of charge accumulation effects on the electric capacity with the realization buck.Along with all kinds of portable memory and flash memory application and development, the situation that the required operating voltage of system is higher than power supply supply voltage is also general day by day, and wherein the power management issue of being derived can utilize booster type electric charge boost pressure circuit as solution.Booster type electric charge boost pressure circuit can be stablized the output that fall progressively voltage or generation are higher than supply voltage, ask for an interview Fig. 1, when being one existing pair to (dual phase) electric charge boost pressure circuit 100 schematic diagrames, electric charge boost pressure circuit 100 comprises one group of n-type metal oxide semiconductor transistor that is connected in series in the diode mode (diode-connected NMOS transistor) and a plurality of electric capacity, wherein the structure of n-type metal oxide semiconductor transistor has critical voltage Vt, and electric capacity is electrically connected on the node between two n-type metal oxide semiconductor transistor respectively.Its operation principle is to utilize a pair of inversion clock signal 1 and 2, electric capacity is replaced charging and reaches the purpose of supercharging, difference according to current path, its circuit working cycle (clock cycle) can be divided into setting cycle (setup period) and boost the cycle (pumpingperiod), when the stage of setting, clock signal 1 is low level (low), open one first charge path 110 to electric charge boost pressure circuit 100 when two, the magnitude of voltage of n-type metal oxide semiconductor transistor conducting on first charge path 110 on a first node 120 arrives Vin-Vt, and this moment, the voltage of one capacitor C 1 also charged to Vin-Vt.Then, when boost phase, clock signal 1 is high levle (high), in the present embodiment, the magnitude of voltage of clock signal arrives V in boost phase, will make capacitor C 1 voltage also therefore promote v , and make magnitude of voltage on the first node 120 arrive Vin+ (V -Vt), as the critical voltage value Vt of node 120 magnitudes of voltage, also open second charge path 140 this moment and make magnitude of voltage on the Section Point 130 arrive Vin+ (V -Vt)-Vt greater than n-type metal oxide semiconductor transistor.In like manner can get, when next setting cycle, the magnitude of voltage arrival Vin+2 on the Section Point 130 (V -Vt).
In summary, the output voltage values to the electric charge boost pressure circuit when comprising N node two can be expressed as:
Vout＝Vin+N*(V-Vt)-Vt........(1-1)。
By finding in the relation of 1-1 formula, be subject in the metal-oxide semiconductor transistor construction, the existence of critical voltage Vt (threshold voltage) effect, the supercharging efficient thereby the decline of electric charge boost pressure circuit 100, cause system effectiveness not high, especially under the low supply voltage situation, the influence that the critical voltage effect causes system effectiveness is with fairly obvious, make this electric charge boost pressure circuit 100 and be not suitable for low voltage operating, and not good the causing of the efficient of its supercharging must there be more power consumption to remedy its very big shortcoming especially on the general circuit application.
For this reason, many improvement to the electric charge boost pressure circuit are suggested in succession.Ask for an interview Fig. 2, be United States Patent (USP) card number: 6,670, a kind of Improvement type electric charge boost pressure circuit 200 that 884 B2 are disclosed, the structure and the electric charge boost pressure circuit 100 of this Improvement type electric charge boost pressure circuit 200 are roughly the same, are to implement with depletion most (Depletion-type MOS Transistor) except the diode in the Improvement type electric charge boost pressure circuit 200 connects metal oxide semiconductor transistor.Its advantage with depletion type N channel metal-oxide semiconductor transistor (Depletion-type N-channel MOS Transistor) for example, its critical voltage value is a negative value, its characteristic makes the transistorized channel of depletion type N channel metal-oxide semiconductor continue to keep conducting state, unless its grid voltage between source electrodes (Vgs) is applied in the magnitude of voltage of a subcritical voltage.Utilize the characteristic of above-mentioned depletion most, the influence that the system effectiveness that the critical voltage Vt effect of being avoided Improvement type electric charge boost pressure circuit 200 is caused descends makes electric charge boost pressure circuit 100 height of the output voltage of described Improvement type electric charge boost pressure circuit 200 than same order.But; in this simultaneously; the characteristic of above-mentioned depletion most also makes this Improvement type electric charge boost pressure circuit 200 when work time pulse switches; after the voltage of node A has been pressurized; depletion type N channel metal-oxide semiconductor transistor still can't end (turn off); thereby along a path 210 generations one reverse leakage current Iq; adopt the not good effect of the efficient of critical voltage supercharging that Vt causes of enhancement mode N channel transistor (Enhancement-typeN-channel Transistor) identical in reverse leakage current Iq and the electric charge boost pressure circuit 100; all will cause the low of system effectiveness; especially bad; reverse leakage current Iq overflow in Improvement type electric charge boost pressure circuit 200 more may make system's damage; reduce reliability; in order to prevent that reliability from descending; system often need increase protective circuit; such measure makes the cost of system rise again, more is unfavorable for the application and the sale of product.
In order to reduce reverse leakage current Iq, Improvement type electric charge boost pressure circuit 200 has disclosed and has utilized length-width ratio (W/L) parameter that changes described depletion most to reduce the method for reverse leakage current Iq, but such method only can reduce the generation that can't avoid reverse leakage current Iq fully, the transistor length-width ratio of excessive variation is except the difficulty that increases processing procedure, also may produce when design the electrical interference that can't discover, in a word, such practice at first can't be ended reverse reverse current fully, moreover the increase of processing procedure difficulty also may increase production cost, and secondly contingent electrical interference also makes the reliability of circuit descend.
For this reason, a kind of when ending reverse reverse current fully, the electric charge boost pressure circuit of all right holding circuit reliability is very to need.
Summary of the invention
One of purpose of the present invention is to provide a kind of voltage increase circuit for elevated voltage charge, this voltage increase circuit for elevated voltage charge utilizes depletion mode transistor (Depletion-type MOS Transistor) to form equivalence serial connection diode, makes voltage increase circuit for elevated voltage charge not have the critical voltage loss to increase boosting efficiency.
Another object of the present invention is to provide a kind of voltage increase circuit for elevated voltage charge, this voltage increase circuit for elevated voltage charge comprises at least one reverse current cut-off circuit, and the reverse current cut-off circuit ends reverse leakage current to increase boosting efficiency.
Another object of the present invention is to provide a kind of voltage increase circuit for elevated voltage charge, this voltage increase circuit for elevated voltage charge comprises at least one reverse current cut-off circuit, and voltage increase circuit for elevated voltage charge need not use particular process sequence, is saved cost.
Another object of the present invention is to provide a kind of voltage increase circuit for elevated voltage charge, this voltage increase circuit for elevated voltage charge comprises at least one reverse current cut-off circuit, and the reverse current cut-off circuit is by reverse leakage current, to reduce electrical interference and to increase system dependability.
Another object of the present invention is to provide a kind of voltage increase circuit for elevated voltage charge, this voltage increase circuit for elevated voltage charge comprises at least one voltage stabilizing circuit, and stable output voltage is provided.
For achieving the above object, the invention provides a kind of voltage increase circuit for elevated voltage charge, include:
A plurality of diode equivalent networks, wherein said diode equivalent network is to be electrically connected with series system, has a node between per two diode equivalent networks, each node correspondence one rank of boosting, the diode equivalent network low-pressure side on the wherein minimum rank of boosting is an input of voltage increase circuit for elevated voltage charge, and input receives an input voltage signal;
At least one boost capacitor network, one end points of each boost capacitor network is electrically connected with one of node such as grade respectively, another end points of each boost capacitor network is electrically connected with a clock signal respectively, wherein clock signal has accurate position of at least one high voltage and the accurate position of a low-voltage, alternate by the accurate position of clock signal makes input voltage signal in each rank boosted voltage reference position value that boosts; And
At least one reverse current cut-off circuit, each reverse current cut-off circuit is electrically connected with the diode equivalent network respectively, the diode equivalent network that the control of each reverse current cut-off circuit is corresponding enable (enable) and anergy (disable), wherein said reverse current cut-off circuit has at least two guiding paths.
Description of drawings
Phase when Fig. 1 is one existing pair (dual phase) electric charge boost pressure circuit 100 schematic diagrames.
Fig. 2 is a kind of Improvement type electric charge boost pressure circuit 200.
Fig. 3 is the schematic diagram of a kind of voltage increase circuit for elevated voltage charge 300 of being disclosed in one of embodiment of the invention.
Fig. 4 is the disclosed equivalent electric circuit 400 of quadravalence voltage increase circuit for elevated voltage charge 300 when one first input state.
Fig. 5 is the disclosed equivalent electric circuit 500 of voltage increase circuit for elevated voltage charge 300 when one second input state.
Equivalent circuit diagram when Fig. 6 returns back to first input state for clock signal.
Equivalent circuit diagram when Fig. 7 returns back to the 2nd input state for clock signal.
Drawing reference numeral:
During 2 couples of clock signal 1 clock signal to electric charge boost pressure circuit 100
Second charge path, 140 capacitor C, 1 Improvement type electric charge boost pressure circuit 200
Quadravalence voltage increase circuit for elevated voltage charge 300 first reverse current cut-off circuit 310a
The second reverse current cut-off circuit 310b the 3rd reverse current cut-off circuit 310c
The 4th reverse current cut-off circuit 310d first equivalent diode 320a
The second equivalent diode 320b C grade is imitated diode 320c
The fourth class is imitated the diode 320d first boost capacitor 330a
The second boost capacitor 330b the 3rd boost capacitor 330c
The 4th boost capacitor 330d input voltage signal Vin
First signal source of clock or a clock signal 1
A second clock signal source or a clock signal 2
Embodiment
The schematic diagram of a kind of quadravalence voltage increase circuit for elevated voltage charge (4-order Chareg-pump Circuit) 300 that Figure 3 shows that in one of embodiment of the invention to be disclosed, this quadravalence voltage increase circuit for elevated voltage charge 300 comprises one first reverse current cut-off circuit 310a, one second reverse current cut-off circuit 310b, one the 3rd reverse current cut-off circuit 310c, one the 4th reverse current cut-off circuit 310d, one first equivalent diode 320a, one second equivalent diode 320b, one C grade is imitated diode 320c, one fourth class is imitated diode 320d, one first boost capacitor 330a, one second boost capacitor 330b, one the 3rd boost capacitor 330c and one the 4th boost capacitor 330d, wherein to comprise a switch right for each reverse current cut-off circuit 310, in the present embodiment, reverse current cut-off circuit 310 is to be made up of an enhancement mode N channel MOS (metal-oxide-semiconductor) transistor (Enhancement-typeN-channel Transistor) and an enhancement mode P channel MOS (metal-oxide-semiconductor) transistor (Enhancement-type P-channel Transistor) respectively, but also not as limit.In fact, among the present invention, switch be to can being made up of the relative any switch of on state characteristic, except the electronic switch that semiconductor subassembly forms, such as electromagnetic switch etc., should be considered as disclosing in the present invention.
In the present embodiment, form between the enhancement mode N channel MOS (metal-oxide-semiconductor) transistor and enhancement mode P channel MOS (metal-oxide-semiconductor) transistor of each reverse current cut-off circuit, be to utilize transistor source electrode (source gate) separately and another transistorized source electrode, or drain electrode separately (drain gate) electrically connect with another transistor drain.In addition, form each transistorized grid of organizing reverse current cut-off circuit 310 and can be attached to a common node.In addition, in the present embodiment, each equivalent diode 320 is formed with a depletion type N channel MOS transistor (Depletion-type NMOS transistor) and the enhancement mode P channel MOS (metal-oxide-semiconductor) transistor of forming this cut-off circuit 310, the whether conducting of this enhancement mode of grid voltage may command P channel MOS (metal-oxide-semiconductor) transistor of this enhancement mode P channel MOS (metal-oxide-semiconductor) transistor, when the enhancement mode P channel MOS (metal-oxide-semiconductor) transistor conducting in the cut-off circuit 310 and the enhancement mode N channel MOS (metal-oxide-semiconductor) transistor in the cut-off circuit 310 by the time, can be considered between gate terminal of depletion type N channel transistor (gate terminal) and drain electrode end (drainterminal) and be connected to each other, the equivalence of depletion type N channel crystal tube side is a diode.In other words, present embodiment is right by the switch of forming the reverse current cut-off circuit, depletion type N channel transistor that control is corresponding and the formed equivalent diode of enhancement mode P channel MOS (metal-oxide-semiconductor) transistor in the reverse current cut-off circuit enable (enable) and anergy (disable).In fact, in the present embodiment, the gate terminal of described depletion mode transistor and the loop between drain electrode end only need equivalence can implement for the assembly of switch, and except that utilizing a P channel transistor, an enhancement mode N channel transistor also can realize aforementioned structure.
In addition, in the present embodiment, an end of reverse current cut-off circuit 310 is electrically connected with an earth terminal (GND), and the loop that each reverse current cut-off circuit and each equivalent diode circuit are formed can be according to the control conducting and the disconnection respectively of clock signal.It should be noted that earth terminal voltage of the present invention is adjusted to any suitable numerical value, does not exceed with no-voltage.
The annexation of quadravalence voltage increase circuit for elevated voltage charge 300 is described below:
The first equivalent diode 320a and the second equivalent diode 320b are be one another in series (connected inserial), its connection end point is a first node Node1, the second equivalent diode 320b and C grade are imitated diode 320c and are one another in series, its connection end point is a Section Point Node2, C grade imitates diode 320c and fourth class effect diode 320d is one another in series, its connection end point is one the 3rd node Node3, and the source electrode end points that the fourth class is imitated diode 320d is a voltage output node Vout of quadravalence.
In each reverse current cut-off circuit, the grid of forming the enhancement metal oxide-semiconductor transistor of switch correspondence is electrically connected to each other, and connection end point forms one the 4th node Node4, one the 5th node Node5, one the 6th node Node6 and one the 7th node Node7 respectively.
Two drain electrodes or two source electrodes between two enhancement metal oxide-semiconductor transistors of composition reverse current cut-off circuit 310 are electrically connected to each other, and connection end point forms one the 8th node Node8, one the 9th node Node9, one the 10th node Node10 and a Section 11 point Node11 respectively.
The first boost capacitor 330a is electrically connected with Node1, and the second boost capacitor 330b is electrically connected with Node2, and the 3rd boost capacitor 330c is electrically connected with Node3, and the 4th boost capacitor 330d is connected with quadravalence voltage output Vout point.In the present embodiment, boost capacitor 330 is that the depletion type N channel MOS (metal-oxide-semiconductor) transistor of utilizing source electrode and drain electrode to be electrically connected to each other realizes, but not as limit.In fact, anyly be enough to equivalence and one have the electronic building brick or the combination of circuits of suitable capacitance, the variation of all visual boost capacitor is for this reason implemented.Wherein be connected to one the 12nd node Node12 between the source electrode of the first boost capacitor 330a and drain electrode, in like manner analogize, tie point between the source electrode of the second boost capacitor 330b and drain electrode is one the 13rd node Node13, and tie point and Node12 between the source electrode of the 3rd boost capacitor 330c and drain electrode are same node.Tie point and Node13 between the source electrode of the 4th boost capacitor 330d and drain electrode are same node, and Node12 and Node13 are connected to one first a signal source of clock 1 and a second clock signal source 2 respectively, 1 and 2 are the inversion clock signal source, the high low level of signal source occurs alternately, in the present embodiment, the magnitude of voltage of expression low level is 0, and high levle is V , but also not as limit, its high low level changes can be needed to regulate according to system.The grid of boost capacitor is connected with first node Node1, Section Point Node2, the 3rd node Node3 and quadravalence voltage output node Vout respectively.
The operation principle of quadravalence voltage increase circuit for elevated voltage charge 300 is described below:
Ask for an interview shown in Figure 4ly, be the equivalent electric circuit 400 of disclosed quadravalence voltage increase circuit for elevated voltage charge 300 when one first input state.When first input state, one input voltage signal Vin imports voltage increase circuit for elevated voltage charge 300, this moment 1 be 0 (also can be accurate position of ground connection or the accurate position of Low) or the accurate position of low-voltage and 2 is V , then the reverse current cut-off circuit because of be subjected to its control respectively with the switch in the reverse current cut-off circuit to according to its on state characteristic, conducting (turn on) and disconnection (turn off) respectively, thereby form different guiding paths, make the loop conducting between depletion type N channel crystal tube grid and source electrode between this equivalent secondary body 320a and 320c be connected (Diode-connected) to form diode, depletion type N channel crystal tube grid between equivalence secondary body 320b and 320d and the loop between source electrode disconnect, so 320b is not that diode is connected with the depletion type N channel transistor of 320d at this moment, that is this equivalent diode is in disabled state when first input state.
At this moment, because the depletion type N channel transistor conducting among the 320a, so input Vin will produce a charging current I1 to electric capacity 330a charging, up to the voltage Vnode1=Vin of Node1.
Ask for an interview shown in Figure 5ly, be the equivalent electric circuit 500 of disclosed voltage increase circuit for elevated voltage charge 300 when one second input state.When second input state, one input voltage signal Vin imports voltage increase circuit for elevated voltage charge 300, this moment, 1 was 0 (the accurate position of ground connection or Low) for V 2, then the reverse current cut-off circuit makes switch in the reverse current cut-off circuit to according to its on state characteristic because of being subjected to its control, be switched on (turn on) respectively and disconnect (turn off), thereby form different guiding paths, depletion type N channel crystal tube grid between equivalence secondary body 320b and 320d is shaped as diode with the loop conducting between source electrode and is connected, depletion type N channel crystal tube grid between equivalence secondary body 320a and 320c and the loop between source electrode disconnect, so 320a is not that diode is connected with the depletion type N channel transistor of 320c at this moment, that is equivalent diode is in disabled state when first input state.With this, import the accurate position that the first signal source of clock , 1, the first boost capacitor 330a voltage is raised a V in the Node12 place, and the voltage Vnode1 of node1 also is promoted to Vin+V thereupon.Second equivalent diode 320b conducting because diode connects sees through 2 pairs of electric capacity 330b chargings of an electric current I that the loop produces, and Vnode2 also charges thereupon and is promoted to Vin+V .It should be noted that, in prior art, this moment because of Vode1 greater than Vin, to produce a reverse current Iq, and in voltage increase circuit for elevated voltage charge 300, owing to this moment the depletion type N channel transistor among the 320a grid because the switch of 310a is to being conducting to ground connection, and if the source electrode that has reverse current to produce the depletion type N channel transistor among the 320a this moment will be node Vin according to reverse current Iq direction, with this, this moment the depletion type N channel transistor among the 320a gate-source voltage Vgs1=-Vin, so it is also little compared to the critical voltage Vt of depletion type N channel transistor as if the gate-source voltage of working as depletion type N channel transistor this moment, that is to say Vgs1＜Vt, then will can not produce reverse current, voltage increase circuit for elevated voltage charge 300 is reached the purpose that increases supercharging efficient and reduce cost with this.
Ask for an interview shown in Figure 6ly, clock signal returns back to first input state subsequently, this moment second clock signal 2=V .With this, Node2 will be raised a V position as above-mentioned same principle, make Vnode2=Vin+2V .The depletion type N channel transistor that C grade is imitated among the diode network 320c also is switched on (turn on) respectively and disconnects (turn off) because of the switch of 310c, thereby form different guiding paths and form that diode connects and conducting, see through the loop and form a charging current I3 electric capacity 330c is charged to Vnode3=Vin+2V .In addition, the voltage of Vnode1 returns back to Vin, make Vgs2=-Vin, this moment, the gate-source voltage of depletion type N channel transistor was also little compared to the critical voltage Vt of depletion type N channel transistor, that is to say Vgs2＜Vt, then will can not produce reverse current, then the second equivalent diode 320b disconnects (turn off), and the voltage of Node2 and Node3 is maintained.
Ask for an interview shown in Figure 7ly, clock signal returns back to the 2nd input state subsequently, and is same as above, this moment the first clock signal 1=V .With this, the 3rd boost capacitor 330a voltage of importing the first clock signal 1 in the Node12 place is raised the accurate position of a V , and the voltage Vnode3 of node3 also is promoted to Vin+3V thereupon.The depletion type N channel transistor that the fourth class is imitated among the diode 320d also is actual diode connection conducting at this moment, and a charging current I4 who sees through loop formation is to electric capacity 330d charging, and Vout is also charged by electric current I 4 thereupon, up to being promoted to Vin+3V .
In like manner, when the clock signal was returned to the second clock signal once more, the magnitude of voltage that electric capacity 330d is raised a V again made Vout=Vin+4V and reaches the circuit function that supercharging is exported.
It should be noted that the reverse current cut-off circuit can utilize any its on state characteristic relative electronic building brick or combination of circuits to form, its role is to utilize the variation of input clock signal to change guiding path, to avoid the generation of aforesaid converse electrical leakage flow phenomenon.Therefore, the related personnel of this technology should understand, utilize an enhancement mode N channel MOS (metal-oxide-semiconductor) transistor and an enhancement mode N channel MOS (metal-oxide-semiconductor) transistor to realize the method for reverse current cut-off circuit in the present embodiment, for implementing one of method that the reverse current cut-off circuit exemplified, but not restriction of the present invention.
The present invention forms the reverse current cut-off circuit by electrically relative switch, and the reverse current that using prevents to boost is produced causes energy resource consumption and influences boosting efficiency, and increases the reliability of system.
In summary, an output voltage values that comprises the N rank voltage increase circuit for elevated voltage charge 300 on N rank (N-order) can be expressed as:
Vout＝Vin+N*V……..(3-1)
The serial connection progression of N rank voltage increase circuit for elevated voltage charge 300 can be adjusted according to need, up to electric charge supercharging gain (Pumping Voltage Gain) be tending towards saturated till.In other words, up to electric charge supercharging gain be tending towards saturated before, the progression of electric charge booster circuit can be adjusted according to need, 4 grades of booster circuits that voltage increase circuit for elevated voltage charge 300 discloses only are one of execution mode, can not be considered as restriction of the present invention.
The harmful effect that disclosed voltage increase circuit for elevated voltage charge can avoid critical voltage in the existing electric charge boost pressure circuit and converse electrical leakage stream that system effectiveness is produced when boosting, and need not carry out particular design on any processing procedure to size of components, utilize clock signal existing in the system can operate guiding path to avoid converse electrical leakage stream.With this, disclosed voltage increase circuit for elevated voltage charge not only has good boosting efficiency, have more the advantage of low production cost and high reliability, be more suitable for being applied to such as power supplys such as portable apparatus limited, voltage is lower and need in the better power management low-voltage system.
What deserves to be mentioned is, voltage increase circuit for elevated voltage charge 300 can see through input and be electrically connected with a voltage stabilizing circuit (Regulator), see through voltage stabilizing circuit one stable input voltage value is provided,, still can provide a stable output voltage with when the input power supply is decayed or changed.
Above embodiment only is used to implementation process of the present invention is described, is not to be used to limit protection scope of the present invention.
Claims (43)
1. a voltage increase circuit for elevated voltage charge is characterized in that, includes:
A plurality of diode equivalent networks, wherein this diode equivalent network is electrically connected with series system, has a node between per two diode equivalent networks, each node correspondence one rank of boosting, the low-pressure side of the diode equivalent network on the wherein minimum rank of boosting is an input of voltage increase circuit for elevated voltage charge, and input receives an input voltage signal;
At least one boost capacitor network, one end points of each boost capacitor network is electrically connected with one of node respectively, another end points of each boost capacitor network is electrically connected with a clock signal respectively, wherein clock signal has accurate position of at least one high voltage and the accurate position of a low-voltage, alternate by the accurate position of clock signal makes input voltage signal in each rank boosted voltage reference position value that boosts;
And, at least one reverse current cut-off circuit, each reverse current cut-off circuit is electrically connected with the diode equivalent network respectively, each reverse current cut-off circuit is controlled the enabling of a corresponding diode equivalent network (enable) and anergy (disable), and wherein the reverse current cut-off circuit has at least two guiding paths.
2. voltage increase circuit for elevated voltage charge as claimed in claim 1 is characterized in that, guiding path is alternately opened according to the switching of clock signal in each rank of boosting, and reverse reverse current occurs to avoid voltage increase circuit for elevated voltage charge.
3. voltage increase circuit for elevated voltage charge as claimed in claim 1 is characterized in that, the clock signal phase between per two adjacent nodes is opposite.
4. voltage increase circuit for elevated voltage charge as claimed in claim 1 is characterized in that the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
5. voltage increase circuit for elevated voltage charge as claimed in claim 1, it is characterized in that, each diode equivalent network is made up of one of two electronic switch networks in a depletion mode transistor and the reverse current cut-off circuit, when the electronic switch network conducting in the diode equivalent network, corresponding depletion mode transistor is that diode connects.
6. voltage increase circuit for elevated voltage charge as claimed in claim 2, it is characterized in that, each diode equivalent network is made up of one of two electronic switch networks in a depletion mode transistor and the reverse current cut-off circuit, when the electronic switch network conducting in the diode equivalent network, corresponding depletion mode transistor is that diode connects.
7. voltage increase circuit for elevated voltage charge as claimed in claim 1 is characterized in that the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
8. voltage increase circuit for elevated voltage charge as claimed in claim 2 is characterized in that the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
9. voltage increase circuit for elevated voltage charge as claimed in claim 4 is characterized in that the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
10. voltage increase circuit for elevated voltage charge as claimed in claim 1, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and this enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and this enhancement mode N channel metal-oxide semiconductor transistor turns.
11. voltage increase circuit for elevated voltage charge as claimed in claim 2, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and enhancement mode N channel metal-oxide semiconductor transistor turns.
12. voltage increase circuit for elevated voltage charge as claimed in claim 4, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and enhancement mode N channel metal-oxide semiconductor transistor turns.
13. voltage increase circuit for elevated voltage charge as claimed in claim 8, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
14. voltage increase circuit for elevated voltage charge as claimed in claim 9, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
15. voltage increase circuit for elevated voltage charge as claimed in claim 10, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
16. a voltage increase circuit for elevated voltage charge is characterized in that, includes:
A plurality of diode equivalent networks, wherein the diode equivalent network is to be electrically connected with series system, have a node between per two diode equivalent networks, each node correspondence one rank of boosting, the low-pressure side of the diode equivalent network on the wherein minimum rank of boosting is an input of voltage increase circuit for elevated voltage charge;
One voltage stabilizing circuit, comprise an input and an output, output is electrically connected with the input of voltage increase circuit for elevated voltage charge, input receives an input voltage signal, adjust the set voltage quasi position of input voltage signal to by voltage stabilizing circuit, and export the input of voltage increase circuit for elevated voltage charge by output to;
At least one boost capacitor network, one end points of each boost capacitor network is electrically connected with a node respectively, another end points of each boost capacitor network is electrically connected with a clock signal respectively, wherein clock signal has accurate position of at least one high voltage and the accurate position of a low-voltage, alternate by the accurate position of clock signal makes input voltage signal in each rank boosted voltage reference position value that boosts;
And, at least one reverse current cut-off circuit, each reverse current cut-off circuit is electrically connected with the diode equivalent network respectively, and each reverse current cut-off circuit is controlled enabling and anergy of a corresponding diode equivalent network, and wherein the reverse current cut-off circuit has at least two guiding paths.
17. voltage increase circuit for elevated voltage charge as claimed in claim 16 is characterized in that, guiding path is alternately opened according to the switching of clock signal in each rank of boosting, and reverse reverse current occurs to avoid voltage increase circuit for elevated voltage charge.
18. voltage increase circuit for elevated voltage charge as claimed in claim 1 is characterized in that, the clock signal phase between per two adjacent nodes is opposite.
19. voltage increase circuit for elevated voltage charge as claimed in claim 16 is characterized in that, the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
20. voltage increase circuit for elevated voltage charge as claimed in claim 16, it is characterized in that, each diode equivalent network is made up of one of two electronic switch networks in a depletion mode transistor and the reverse current cut-off circuit, when the electronic switch network conducting in the diode equivalent network, corresponding depletion mode transistor is formed diode with one of corresponding reverse current cut-off circuit and is connected.
21. voltage increase circuit for elevated voltage charge as claimed in claim 17, it is characterized in that, each diode equivalent network is made up of one of two electronic switch networks in a depletion mode transistor and the reverse current cut-off circuit, when the electronic switch network conducting in the diode equivalent network, corresponding depletion mode transistor is formed diode with one of corresponding reverse current cut-off circuit and is connected.
22. voltage increase circuit for elevated voltage charge as claimed in claim 16 is characterized in that, the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
23. voltage increase circuit for elevated voltage charge as claimed in claim 17 is characterized in that, the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
24. voltage increase circuit for elevated voltage charge as claimed in claim 19 is characterized in that, the reverse current cut-off circuit comprises two electronic switch networks, and the on state characteristic of electronic switch network is relative, with one of difference unlocking electronic switching network when clock signal is switched.
25. voltage increase circuit for elevated voltage charge as claimed in claim 16, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and enhancement mode N channel metal-oxide semiconductor transistor turns.
26. voltage increase circuit for elevated voltage charge as claimed in claim 17, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and enhancement mode N channel metal-oxide semiconductor transistor turns.
27. voltage increase circuit for elevated voltage charge as claimed in claim 19, it is characterized in that, the reverse current cut-off circuit comprises an enhancement mode N channel metal-oxide semiconductor transistor and an enhancement mode P channel metal-oxide semiconductor transistor, when the clock signal of importing when the rank of boosting of correspondence is low-voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor turns and enhancement mode N channel metal-oxide semiconductor transistor end, when the clock signal of importing when the rank of boosting of correspondence was high voltage standard position, enhancement mode P channel metal-oxide semiconductor transistor ended and enhancement mode N channel metal-oxide semiconductor transistor turns.
28. voltage increase circuit for elevated voltage charge as claimed in claim 23, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
29. voltage increase circuit for elevated voltage charge as claimed in claim 24, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
30. voltage increase circuit for elevated voltage charge as claimed in claim 25, it is characterized in that, the transistorized source terminal of enhancement mode P channel metal-oxide semiconductor receives input voltage signal, and enhancement mode P channel metal-oxide semiconductor transistor and the transistorized gate terminal of enhancement mode N channel metal-oxide semiconductor receive the clock signal that the corresponding rank of boosting are imported respectively.
31. voltage increase circuit for elevated voltage charge as claimed in claim 16 is characterized in that, each boost capacitor network is made of a depletion mode transistor, is electrically connected between the source electrode of depletion mode transistor and drain electrode.
32. voltage increase circuit for elevated voltage charge as claimed in claim 29 is characterized in that, each boost capacitor network is made of a depletion mode transistor, is electrically connected between the source electrode of depletion mode transistor and drain electrode.
33. voltage increase circuit for elevated voltage charge as claimed in claim 16 is characterized in that, each boost capacitor network is made of a junction field effect transistor (JFET), is electrically connected between the source electrode of junction field effect transistor and drain electrode.
34. voltage increase circuit for elevated voltage charge as claimed in claim 29 is characterized in that, each boost capacitor network is made of a junction field effect transistor (JFET), is electrically connected between the source electrode of junction field effect transistor and drain electrode.
35. voltage increase circuit for elevated voltage charge as claimed in claim 16, it is characterized in that, each diode equivalent network is made up of a junction field effect transistor (JFET), and each junction field effect transistor (JFET) is formed diode with one of corresponding reverse current cut-off circuit and connected.
36. voltage increase circuit for elevated voltage charge as claimed in claim 29, it is characterized in that, each diode equivalent network is made up of a junction field effect transistor (JFET), and each junction field effect transistor (JFET) is formed diode with one of corresponding reverse current cut-off circuit and connected.
37. one is used for the boosting unit of electric charge boost pressure circuit, it is characterized in that, includes:
One equivalent diode network receives an input voltage;
One capacitance network is electrically connected with the equivalent diode network, is higher than a voltage of input voltage by clock signal output;
And a switch is right, is electrically connected with the equivalent diode network, and whether control equivalent diode network forms that diode connects enables (enable) and anergy (disable).
38. boosting unit as claimed in claim 1 is characterized in that, switch is to the conduction by clock signal control input voltage, and switch is to having at least two guiding paths, and clock signal has at least two signal(l)ing conditions.
39. boosting unit as claimed in claim 2 is characterized in that, guiding path is alternately opened according to the variation of clock signal.
40. boosting unit as claimed in claim 3 is characterized in that, the generation of the alternate blocking-up reverse current of guiding path.
41. boosting unit as claimed in claim 1 is characterized in that, an end of switch correspondence is electrically connected with an earth terminal.
42. boosting unit as claimed in claim 4 is characterized in that, the magnitude of voltage of earth terminal is not limited to 0.
43. boosting unit as claimed in claim 2 is characterized in that, clock signal has a high-voltage state and a low-voltage state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101157778A CN101127479A (en) | 2006-08-16 | 2006-08-16 | Voltage increase circuit for elevated voltage charge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101157778A CN101127479A (en) | 2006-08-16 | 2006-08-16 | Voltage increase circuit for elevated voltage charge |
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| Publication Number | Publication Date |
|---|---|
| CN101127479A true CN101127479A (en) | 2008-02-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006101157778A Pending CN101127479A (en) | 2006-08-16 | 2006-08-16 | Voltage increase circuit for elevated voltage charge |
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| Country | Link |
|---|---|
| CN (1) | CN101127479A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107872151A (en) * | 2016-09-26 | 2018-04-03 | 上海和辉光电有限公司 | Charge pump unit, charge pump circuit and display device |
| CN110189786A (en) * | 2019-04-18 | 2019-08-30 | 上海华力集成电路制造有限公司 | Booster circuit applied to flash memories |
| CN111865075A (en) * | 2020-07-27 | 2020-10-30 | 合肥工业大学 | Boost conversion circuit suitable for light energy collection structure |
-
2006
- 2006-08-16 CN CNA2006101157778A patent/CN101127479A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107872151A (en) * | 2016-09-26 | 2018-04-03 | 上海和辉光电有限公司 | Charge pump unit, charge pump circuit and display device |
| CN110189786A (en) * | 2019-04-18 | 2019-08-30 | 上海华力集成电路制造有限公司 | Booster circuit applied to flash memories |
| CN110189786B (en) * | 2019-04-18 | 2020-10-02 | 上海华力集成电路制造有限公司 | Booster circuit applied to flash memory |
| CN111865075A (en) * | 2020-07-27 | 2020-10-30 | 合肥工业大学 | Boost conversion circuit suitable for light energy collection structure |
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