CN108718191B - Oscillator circuit - Google Patents

Oscillator circuit Download PDF

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Publication number
CN108718191B
CN108718191B CN201810921859.4A CN201810921859A CN108718191B CN 108718191 B CN108718191 B CN 108718191B CN 201810921859 A CN201810921859 A CN 201810921859A CN 108718191 B CN108718191 B CN 108718191B
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circuit
pmos
tube
self
pmos tube
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CN108718191A (en
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董渊
王云松
黄建刚
吴传奎
程剑涛
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Shanghai Awinic Technology Co Ltd
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Shanghai Awinic Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/014—Modifications of generator to ensure starting of oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Electronic Switches (AREA)

Abstract

The invention discloses an oscillator circuit, which comprises: the self-starting circuit, the self-adaptive current generating circuit, the capacitor charging and discharging circuit and the clock generating logic circuit. The oscillator circuit provided by the invention can be applied to work under ultra-low working voltage (< 2V), and keeps the specificity of high precision, namely the minimum working voltage is extremely low, and has good temperature and power supply fluctuation resistance, and can be widely applied to analog-to-digital converters, digital-to-analog converters, radio frequencies, sensors and power supply management chips.

Description

Oscillator circuit
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to an oscillator circuit.
Background
The oscillator circuit is widely used as an indispensable basic module in integrated circuits in analog-to-digital converters, digital-to-analog converters, interface circuits and power management chips. The oscillator circuit generally charges the capacitor by using a fixed bias current, generates a periodic sawtooth wave signal on the capacitor, and then generates the periodic square wave signal by comparing with a threshold voltage or a fixed reference level.
As shown in fig. 1, which is a typical ring oscillator circuit in the prior art, in the structure of fig. 1, a reference current generating module is used for generating a reference current and a resistor R0 and electricityThe current associated with resistance R1 can be obtained: i 0 ＝I 1 ＝V GSM1 And (R0-R1), the current charges and discharges the capacitor in the ring oscillator after being mirrored, wherein the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 can be replaced by MOS transistors as switching tubes. When the oscillator works, the first switch S1 and the second switch S2 are disconnected, the switch tube M11 charges the first capacitor C1, when the second switch S2 is charged to the conduction threshold value, the second switch S2 is conducted, the switch tube M7 discharges the second capacitor C2, the third switch S3 is discharged to be turned off, the switch tube M13 charges the third capacitor C3, when the fourth switch S4 is charged to the conduction threshold value, the fourth voltage V4 is turned from high level to low level, the oscillator is turned, the first switch S1 is turned on, the first voltage V1 is turned from high level to low level, and the next charge-discharge cycle is started, if the capacitance values of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are equal, the current values of the switch tube M11, the switch tube M12 and the switch tube M13 are I 0 The current value of the switching tube M6, the switching tube M7 and the switching tube M8 is 2I 0 The turn-on threshold of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 is V S The oscillation period is:from the above analysis, the oscillator circuit in fig. 1 has the following drawbacks: first, the oscillation period is related to the resistance R and the capacitance C, and also related to the conduction threshold V of the MOS tube S And V GSM1 In the related art, the precision of the three-stage ring oscillation circuit along with the process and temperature change is low, and the three-stage ring oscillation circuit needs to have good matching performance to ensure the accuracy of the period; second, in order to pass clamp V P ＝V N The reference current generation module uses an operational amplifier OP1, which makes the oscillator circuit difficult to apply under low voltage power (VDD < 2V), and further limits the minimum operating voltage by the use of stacked switching transistors in the ring oscillator section.
Disclosure of Invention
In view of the above, the present invention provides an oscillator circuit to solve the problems of the prior art that the frequency of the oscillator drifts greatly along with the process, the temperature and the power supply voltage, the precision is poor, and the oscillator circuit cannot be applied under low power supply voltage.
In order to achieve the above purpose, the present invention provides the following technical solutions:
an oscillator circuit comprising: the self-starting circuit, the self-adaptive current generation circuit, the capacitor charge-discharge circuit and the clock generation logic circuit, wherein:
the self-starting circuit includes: a first end, a second end, a third end, and a fourth end; the adaptive current generation circuit includes: a first end, a second end, a third end, a fourth end, and a fifth end; the capacitor charge-discharge circuit includes: a first end, a second end, a third end, a fourth end, a fifth end, a sixth end, a seventh end, and an eighth end; the clock generation logic circuit includes: a first end, a second end, a third end, a fourth end, and a fifth end;
the first end of the self-starting circuit, the first end of the self-adaptive current generating circuit and the first end of the capacitor charging and discharging circuit are connected with a power supply end (VDD); the second end of the self-starting circuit, the second end of the self-adaptive current generating circuit and the second end of the capacitor charging and discharging circuit are connected with a ground terminal (VSS);
the third end of the self-starting circuit is connected with the third end of the self-adaptive current generating circuit, and the fourth end of the self-starting circuit is respectively connected with the fourth end of the self-adaptive current generating circuit and the fourth end of the capacitor charging and discharging circuit;
the fifth end of the self-adaptive current generation circuit is connected with the third end of the capacitor charge-discharge circuit, the fifth end of the capacitor charge-discharge circuit is connected with the third end of the clock generation logic circuit, the sixth end of the capacitor charge-discharge circuit is connected with the fourth end of the clock generation logic circuit, the seventh end of the capacitor charge-discharge circuit is connected with the first end of the clock generation logic circuit, the eighth end of the capacitor charge-discharge circuit is connected with the second end of the clock generation logic circuit, and the fifth end of the clock generation logic circuit is used as the output end of the oscillator circuit to output a periodic signal with the duty ratio of 50%.
Further, the self-starting circuit includes: the first PMOS tube (MP 1), the sixth PMOS tube (MP 6) and the first resistor (R1), wherein:
the first end of the first PMOS tube (MP 1) and the first end of the sixth PMOS tube (MP 6) are used as the first ends of the self-starting circuit and are connected with the power supply end (VDD); the second end of the first PMOS tube (MP 1) is connected with the control end of the sixth PMOS tube (MP 6), the common end of the first PMOS tube is connected with the first end of the first resistor (R1), and the second end of the first resistor (R1) is used as the second end of the self-starting circuit to be connected with the grounding end (VSS);
the control end of the first PMOS tube (MP 1) is used as the third end of the self-starting circuit to be connected with the third end of the self-adaptive current generating circuit, and the second end of the sixth PMOS tube (MP 6) is used as the fourth end of the self-starting circuit to be respectively connected with the fourth end of the self-adaptive current generating circuit and the fourth end of the capacitor charging and discharging circuit.
Further, the first end of the first PMOS tube (MP 1) and the first end of the sixth PMOS tube (MP 6) are sources, the second end of the first PMOS tube is a drain, and the control end of the first PMOS tube is a grid.
Further, the adaptive current generation circuit includes: the second PMOS tube (MP 2), the third PMOS tube (MP 3), the first NMOS tube (MN 1), the second NMOS tube (MN 2) and the second resistor (R2), wherein:
the first end of the second PMOS tube (MP 2) and the first end of the third PMOS tube (MP 3) are used as the first ends of the self-adaptive current generation circuit and are connected with the power supply end (VDD); the control end of the second PMOS tube (MP 2) is connected with the control end of the third PMOS tube (MP 3), and the common end of the second PMOS tube is connected with the second end of the second PMOS tube (MP 2); the second end of the second PMOS tube (MP 2) is connected with the first end of the second NMOS tube (MN 2), the second end of the second NMOS tube (MN 2) is connected with the first end of the second resistor (R2), and the second end of the second resistor (R2) and the second end of the first NMOS tube (MN 1) are used as the second end of the adaptive current generation circuit and are connected with the ground end (VSS);
the first end of the first NMOS tube (MN 1) is connected with the control end of the first NMOS tube (MN 1), the control end of the first NMOS tube (MN 1) is connected with the control end of the second NMOS tube (MN 2), and the first end of the first NMOS tube (MN 1) is used as the third end of the adaptive current generation circuit and is connected with the third end of the self-starting circuit;
the control end of the third PMOS tube (MP 3) is used as the fifth end of the self-adaptive current generation circuit and is connected with the third end of the capacitor charge-discharge circuit.
Further, the first ends of the second PMOS tube (MP 2), the third PMOS tube (MP 3), the first NMOS tube (MN 1) and the second NMOS tube (MN 2) are sources, the second ends are drains, and the control ends are gates.
Further, the capacitor charging and discharging circuit includes: fourth PMOS pipe (MP 4), fifth PMOS pipe (MP 5), seventh PMOS pipe (MP 7), eighth PMOS pipe (MP 8), third NMOS pipe (MN 3), fourth NMOS pipe (MN 4) and fifth NMOS pipe (MN 5), wherein:
the first end of the fourth PMOS tube (MP 4), the first end of the fifth PMOS tube (MP 5) and the first end of the eighth PMOS tube (MP 8) are used as the first ends of the capacitor charge-discharge circuit and are connected with the power supply end (VDD); the control end of the fourth PMOS tube (MP 4) is used as the third end of the capacitor charge-discharge circuit to be connected with the fifth end of the self-adaptive current generation circuit, and the control end of the fourth PMOS tube (MP 4) is connected with the control end of the fifth PMOS tube (MP 5); the second end of the fourth PMOS tube (MP 4) is connected with the first end of the first capacitor (C1), the second end of the first capacitor (C1) is connected with the first end of the fifth NMOS tube (MN 5), and the first end of the fifth NMOS tube (MN 5) is connected with the control end of the fifth NMOS tube (MN 5);
the first end of the first capacitor (C1) is respectively connected with the first end of the third NMOS tube (MN 3), the first end of the seventh PMOS tube (MP 7) and the control end of the fourth NMOS tube (MN 4), the second end of the seventh PMOS tube (MP 7) is connected with the second end of the third NMOS tube (MN 3), and the common end of the seventh PMOS tube is connected with the first end of the fifth NMOS tube (MN 5); the control end of the seventh PMOS tube (MP 7) is used as the fifth end of the capacitor charge-discharge circuit to be connected with the third end of the clock generation logic circuit, and the control end of the third NMOS tube (MN 3) is used as the sixth end of the capacitor charge-discharge circuit to be connected with the fourth end of the clock generation logic circuit;
the first end of the fourth NMOS tube (MN 4) is respectively connected with the second end of the fifth PMOS tube (MP 5) and the second end of the eighth PMOS tube (MP 8), the control end of the eighth PMOS tube (MP 8) is used as the seventh end of the capacitor charging and discharging circuit to be connected with the first end of the clock generating logic circuit, and the second end of the eighth PMOS tube (MP 8) is used as the eighth end of the capacitor charging and discharging circuit to be connected with the second end of the clock generating logic circuit.
Further, the first ends of the fourth PMOS tube (MP 4), the fifth PMOS tube (MP 5), the seventh PMOS tube (MP 7), the eighth PMOS tube (MP 8), the third NMOS tube (MN 3), the fourth NMOS tube (MN 4) and the fifth NMOS tube (MN 5) are sources, the second end is a drain, and the control end is a gate.
Further, the clock generation logic circuit includes: a first inverter (INV 1), a second inverter (INV 2), a third inverter (INV 3), and a D flip-flop (QF 1), wherein:
an input end of the first inverter (INV 1) is used as a second end of the clock generation logic circuit to be connected with an eighth end of the capacitor charge-discharge circuit, and an output end of the first inverter (INV 1) is connected with an input end of the second inverter (INV 2);
the output end of the second inverter (INV 2) is connected with the input end of the third inverter (INV 3), and the common end of the second inverter is used as the third end of the clock generation logic circuit and is connected with the fifth end of the capacitor charge-discharge circuit;
an output end of the third inverter (INV 3) is used as a fourth end of the clock generation logic circuit to be connected with a sixth end of the capacitor charge-discharge circuit, and an output end of the third inverter (INV 3) is connected with a first end of the D trigger (QF 1); the second end of the D trigger (QF 1) is connected with the third end of the D trigger (QF 1), and the fourth end of the D trigger (QF 1) is used as the output end of the clock generation logic circuit to output a periodic signal with the duty ratio of 50%.
As can be seen from the above technical solution, compared with the prior art, the present invention discloses an oscillator circuit, which includes: the self-starting circuit, the self-adaptive current generating circuit, the capacitor charging and discharging circuit and the clock generating logic circuit. The oscillator circuit provided by the invention can be applied to work under ultra-low working voltage (< 2V), and keeps the specificity of high precision, namely the minimum working voltage is extremely low, and has good temperature and power supply fluctuation resistance, and can be widely applied to analog-to-digital converters, digital-to-analog converters, radio frequencies, sensors and power supply management chips.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a typical ring oscillator circuit of the prior art;
fig. 2 is a schematic diagram of an oscillator circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an oscillator circuit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 2, an embodiment of the present invention provides an oscillator circuit, which includes: an adaptive current generation circuit 21, an adaptive current generation circuit 22, a capacitor charge-discharge circuit 23, and a clock generation logic circuit 24, wherein:
the self-starting circuit 21 includes: a first end, a second end, a third end, and a fourth end; the adaptive current generation circuit 22 includes: a first end, a second end, a third end, a fourth end, and a fifth end; the capacitor charge/discharge circuit 23 includes: a first end, a second end, a third end, a fourth end, a fifth end, a sixth end, a seventh end, and an eighth end; the clock generation logic 24 includes: a first end, a second end, a third end, a fourth end, and a fifth end;
a first terminal of the self-starting circuit 21, a first terminal of the adaptive current generating circuit 22, and a first terminal of the capacitor charge/discharge circuit 23 are connected to a power supply terminal (VDD); a second terminal of the self-starting circuit 21, a second terminal of the adaptive current generating circuit 22, and a second terminal of the capacitor charge-discharge circuit 23 are connected to a ground terminal (VSS);
a third terminal of the self-starting circuit 21 is connected to a third terminal of the adaptive current generating circuit 22, and a fourth terminal of the self-starting circuit 21 is connected to a fourth terminal of the adaptive current generating circuit 22 and a fourth terminal of the capacitor charge/discharge circuit 23, respectively;
the fifth terminal of the adaptive current generating circuit 22 is connected to the third terminal of the capacitor charge/discharge circuit 23, the fifth terminal of the capacitor charge/discharge circuit 23 is connected to the third terminal of the clock generating logic circuit 24, the sixth terminal of the capacitor charge/discharge circuit 23 is connected to the fourth terminal of the clock generating logic circuit 24, the seventh terminal of the capacitor charge/discharge circuit 23 is connected to the first terminal of the clock generating logic circuit 24, the eighth terminal of the capacitor charge/discharge circuit 23 is connected to the second terminal of the clock generating logic circuit 24, and the fifth terminal of the clock generating logic circuit 24 outputs a periodic signal having a duty ratio of 50% as an output terminal of the oscillator circuit.
As shown in fig. 3, the self-starting circuit 21 includes: the first PMOS tube MP1, the sixth PMOS tube MP6 and the first resistor R1, wherein:
the first end of the first PMOS MP1 and the first end of the sixth PMOS MP6 are connected to the power supply (VDD) as the first ends of the self-starting circuit 21; a second end of the first PMOS MP1 is connected to the control end of the sixth PMOS MP6, a common end thereof is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the ground (VSS) as the second end of the self-starting circuit 21;
the control end of the first PMOS MP1 is connected to the third end of the adaptive current generating circuit 22 as the third end of the self-starting circuit 21, and the second end of the sixth PMOS MP6 is connected to the fourth end of the adaptive current generating circuit 22 and the fourth end of the capacitor charge-discharge circuit 23 as the fourth end of the self-starting circuit 21, respectively.
Specifically, the first end of the first PMOS transistor MP1 and the second end of the sixth PMOS transistor MP6 are sources, the second end is a drain, and the control end is a gate.
As shown in fig. 3, the adaptive current generating circuit 22 includes: the second PMOS tube MP2, the third PMOS tube MP3, the first NMOS tube MN1, the second NMOS tube MN2 and the second resistor R2, wherein:
the first end of the second PMOS MP2 and the first end of the third PMOS MP3 are connected to the power supply (VDD) as the first ends of the adaptive current generating circuit 22; the control end of the second PMOS tube MP2 is connected with the control end of the third PMOS tube MP3, and the common end of the second PMOS tube MP2 is connected with the second end of the second PMOS tube MP 2; the second end of the second PMOS MP2 is connected to the first end of the second NMOS MN2, the second end of the second NMOS MN2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 and the second end of the first NMOS MN1 are connected to the ground (VSS) as the second ends of the adaptive current generating circuit 22;
a first end of the first NMOS transistor MN1 is connected to a control end of the first NMOS transistor MN1, a control end of the first NMOS transistor MN1 is connected to a control end of the second NMOS transistor MN2, and the first end of the first NMOS transistor MN1 is connected to a third end of the self-starting circuit 21 as a third end of the adaptive current generating circuit 22;
the control end of the third PMOS MP3 is connected to the third end of the capacitor charge/discharge circuit 23 as the fifth end of the adaptive current generating circuit 22.
Specifically, the first ends of the second PMOS transistor MP2, the third PMOS transistor MP3, the first NMOS transistor MN1, and the second NMOS transistor MN2 are sources, the second ends are drains, and the control ends are gates.
As shown in fig. 3, the capacitor charge/discharge circuit 23 includes: fourth PMOS pipe MP4, fifth PMOS pipe MP5, seventh PMOS pipe MP7, eighth PMOS pipe MP8, third NMOS pipe MN3, fourth NMOS pipe MN4 and fifth NMOS pipe MN5, wherein:
the first end of the fourth PMOS MP4, the first end of the fifth PMOS MP5, and the first end of the eighth PMOS MP8 are connected to the power supply terminal (VDD) as the first ends of the capacitor charge-discharge circuit 23; the control end of the fourth PMOS MP4 is connected to the fifth end of the adaptive current generating circuit 22 as the third end of the capacitor charge-discharge circuit 23, and the control end of the fourth PMOS MP4 is connected to the control end of the fifth PMOS MP 5; the second end of the fourth PMOS MP4 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the fifth NMOS MN5, and the first end of the fifth NMOS MN5 is connected to the control end of the fifth NMOS MN 5;
the first end of the first capacitor C1 is connected to the first end of the third NMOS transistor MN3, the first end of the seventh PMOS transistor MP7, and the control end of the fourth NMOS transistor MN4, respectively, the second end of the seventh PMOS transistor MP7 is connected to the second end of the third NMOS transistor MN3, and the common end thereof is connected to the first end of the fifth NMOS transistor MN 5; the control end of the seventh PMOS MP7 is connected to the third end of the clock generation logic circuit 24 as the fifth end of the capacitor charge-discharge circuit 23, and the control end of the third NMOS MN3 is connected to the fourth end of the clock generation logic circuit 24 as the sixth end of the capacitor charge-discharge circuit 23;
the first end of the fourth NMOS transistor MN4 is connected to the second end of the fifth PMOS transistor MP5 and the second end of the eighth PMOS transistor MP8, respectively, the control end of the eighth PMOS transistor MP8 is connected to the first end of the clock generation logic circuit 24 as the seventh end of the capacitor charge/discharge circuit 23, and the second end of the eighth PMOS transistor MP8 is connected to the second end of the clock generation logic circuit 24 as the eighth end of the capacitor charge/discharge circuit 23.
Specifically, the first ends of the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are sources, the second ends are drains, and the control ends are gates.
As shown in fig. 3, the clock generation logic 24 includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, and a D flip-flop QF1, wherein:
an input terminal of the first inverter INV1 is connected to an eighth terminal of the capacitor charge/discharge circuit 23 as a second terminal of the clock generation logic circuit 24, and an output terminal of the first inverter INV1 is connected to an input terminal of the second inverter INV 2;
an output terminal of the second inverter INV2 is connected to an input terminal of the third inverter INV3, and a common terminal thereof is connected to a fifth terminal of the capacitor charge/discharge circuit 23 as a third terminal of the clock generation logic circuit 24;
an output terminal of the third inverter INV3 is connected to a sixth terminal of the capacitor charge/discharge circuit 23 as a fourth terminal of the clock generation logic circuit 24, and an output terminal of the third inverter INV3 is connected to a first terminal of the D flip-flop QF 1; the second terminal of the D flip-flop QF1 is connected to the third terminal of the D flip-flop QF1, and the fourth terminal of the D flip-flop QF1 outputs a periodic signal having a duty ratio of 50% as the output terminal of the clock generation logic circuit 24.
Referring to fig. 3, the principle of the oscillator circuit provided by the embodiment of the invention is as follows: when the power supply is powered on, the self-adaptive current generating circuit 22 starts to be not established, the MP2 and the MP3 are turned off, when the power supply voltage rises to a certain value, the MP6 is turned on, the gate end of the MN2 is pulled up, the MN2 and the MN1 are turned on, and the starting circuit is turned off. The circuit breaks away from the zero degeneracy point, generating a charging current:
I BP2 ＝I BP3 ＝I BP4 ＝I BP5 ＝(V GSN1 -V GSN2 )/R2
wherein I is BP2 、I BP3 、I BP4 And I BP5 The current flows through the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4 and the fifth PMOS tube MP5 respectively. After the charge-discharge circuit starts to work, FB1 is low level, FB1B is high level, the third NMOS tube MN3 and the seventh NMOS tube MP7 are cut off, the current of the fourth NMOS tube MP4 charges the first capacitor C1, and when the current is charged to V GSN4 So that V is N4 When the high level is turned to the low level, the third NMOS tube MN3 and the seventh PMOS tube MP7 are conducted, V C1 The node is pulled to V N5 Node, i.e. V at this time C1 ＝V N5 ，V N4 The third NMOS transistor MN3 and the seventh PMOS transistor MP7 are turned off, and the fourth PMOS transistor MP4 resumes charging the first capacitor C1, thus reciprocating, generating a periodic narrow pulse signal, which is divided by the D flip-flop QF1, generating a periodic signal with a duty ratio of 50%. The period of the signal is:
dT OSC ＝R2*dC1+C1*dR2
if V GSN4 -V GSN5 ＝V GSN1 -V GSN2 T is then OSC ＝2R2*C1
From the above, if the MOS parameters are designed such that V GNS4 -V GSN5 ＝V GSN1 -V GSN2 The oscillator period of the embodiment of the invention is only related to the first capacitor C1 and the first resistor R2, so that the bias derivative of the above formula can be obtained, and the oscillator period of the embodiment of the invention is only related to the value of RC, and is only related to the change of RC under different temperatures and processes.
The circuit is available from the working principle, and the lowest working voltage of the circuit is as follows:
VDD MIN ＝V GSN1 +V DSP3 ＜2V
wherein V is GSN1 Is the gate-source voltage (about 0.7V-0.9V) of the first NMOS transistor MN1 during normal operation DSP3 The drain-source voltage (about 0.2V) is used when the third PMOS tube MP3 works, thus the oscillator of the invention can be obtained under the ultra-low working voltage<2V) and maintains the characteristic of high precision.
The oscillator circuit provided by the embodiment of the invention has extremely low minimum working voltage requirement and good temperature and power supply fluctuation resistance, and can be widely applied to an analog-to-digital converter, a digital-to-analog converter, a radio frequency, a sensor and a power supply management chip.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The circuit according to the present invention has been described above by way of example with reference to the accompanying drawings, and the description of the above embodiments is only for aiding in the understanding of the core idea of the present invention. Variations in the detailed description and the application scope will occur to those skilled in the art upon consideration of the teachings of the present invention. In view of the foregoing, the present disclosure should not be construed as limiting the invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. An oscillator circuit, comprising: the self-starting circuit, the self-adaptive current generation circuit, the capacitor charge-discharge circuit and the clock generation logic circuit, wherein:
the self-starting circuit includes: a first end, a second end, a third end, and a fourth end; the adaptive current generation circuit includes: a first end, a second end, a third end, a fourth end, and a fifth end; the capacitor charge-discharge circuit includes: a first end, a second end, a third end, a fourth end, a fifth end, a sixth end, a seventh end, and an eighth end; the clock generation logic circuit includes: a first end, a second end, a third end, a fourth end, and a fifth end;
the first end of the self-starting circuit, the first end of the self-adaptive current generating circuit and the first end of the capacitor charging and discharging circuit are connected with a power supply end (VDD); the second end of the self-starting circuit, the second end of the self-adaptive current generating circuit and the second end of the capacitor charging and discharging circuit are connected with a ground terminal (VSS);
the third end of the self-starting circuit is connected with the third end of the self-adaptive current generating circuit, and the fourth end of the self-starting circuit is respectively connected with the fourth end of the self-adaptive current generating circuit and the fourth end of the capacitor charging and discharging circuit;
the fifth end of the self-adaptive current generation circuit is connected with the third end of the capacitor charge-discharge circuit, the fifth end of the capacitor charge-discharge circuit is connected with the third end of the clock generation logic circuit, the sixth end of the capacitor charge-discharge circuit is connected with the fourth end of the clock generation logic circuit, the seventh end of the capacitor charge-discharge circuit is connected with the first end of the clock generation logic circuit, the eighth end of the capacitor charge-discharge circuit is connected with the second end of the clock generation logic circuit, and the fifth end of the clock generation logic circuit is used as the output end of the oscillator circuit to output a periodic signal with the duty ratio of 50%;
the adaptive current generation circuit includes: the second PMOS tube (MP 2), the third PMOS tube (MP 3), the first NMOS tube (MN 1), the second NMOS tube (MN 2) and the second resistor (R2), wherein:
the first end of the second PMOS tube (MP 2) and the first end of the third PMOS tube (MP 3) are used as the first ends of the self-adaptive current generation circuit and are connected with the power supply end (VDD); the control end of the second PMOS tube (MP 2) is connected with the control end of the third PMOS tube (MP 3), and the common end of the second PMOS tube is connected with the second end of the second PMOS tube (MP 2); the second end of the second PMOS tube (MP 2) is connected with the first end of the second NMOS tube (MN 2), the second end of the second NMOS tube (MN 2) is connected with the first end of the second resistor (R2), and the second end of the second resistor (R2) and the second end of the first NMOS tube (MN 1) are used as the second end of the adaptive current generation circuit and are connected with the ground end (VSS);
the first end of the first NMOS tube (MN 1) is connected with the control end of the first NMOS tube (MN 1), the control end of the first NMOS tube (MN 1) is connected with the control end of the second NMOS tube (MN 2), and the first end of the first NMOS tube (MN 1) is used as the third end of the adaptive current generation circuit and is connected with the third end of the self-starting circuit;
the control end of the third PMOS tube (MP 3) is used as the fifth end of the self-adaptive current generation circuit and is connected with the third end of the capacitor charge-discharge circuit;
the capacitor charge-discharge circuit includes: fourth PMOS pipe (MP 4), fifth PMOS pipe (MP 5), seventh PMOS pipe (MP 7), eighth PMOS pipe (MP 8), third NMOS pipe (MN 3), fourth NMOS pipe (MN 4) and fifth NMOS pipe (MN 5), wherein:
the first end of the fourth PMOS tube (MP 4), the first end of the fifth PMOS tube (MP 5) and the first end of the eighth PMOS tube (MP 8) are used as the first ends of the capacitor charge-discharge circuit and are connected with the power supply end (VDD); the control end of the fourth PMOS tube (MP 4) is used as the third end of the capacitor charge-discharge circuit to be connected with the fifth end of the self-adaptive current generation circuit, and the control end of the fourth PMOS tube (MP 4) is connected with the control end of the fifth PMOS tube (MP 5); the second end of the fourth PMOS tube (MP 4) is connected with the first end of the first capacitor (C1), the second end of the first capacitor (C1) is connected with the first end of the fifth NMOS tube (MN 5), and the first end of the fifth NMOS tube (MN 5) is connected with the control end of the fifth NMOS tube (MN 5);
the first end of the first capacitor (C1) is respectively connected with the first end of the third NMOS tube (MN 3), the first end of the seventh PMOS tube (MP 7) and the control end of the fourth NMOS tube (MN 4), the second end of the seventh PMOS tube (MP 7) is connected with the second end of the third NMOS tube (MN 3), and the common end of the seventh PMOS tube is connected with the first end of the fifth NMOS tube (MN 5); the control end of the seventh PMOS tube (MP 7) is used as the fifth end of the capacitor charge-discharge circuit to be connected with the third end of the clock generation logic circuit, and the control end of the third NMOS tube (MN 3) is used as the sixth end of the capacitor charge-discharge circuit to be connected with the fourth end of the clock generation logic circuit;
the first end of the fourth NMOS tube (MN 4) is respectively connected with the second end of the fifth PMOS tube (MP 5) and the second end of the eighth PMOS tube (MP 8), the control end of the eighth PMOS tube (MP 8) is used as the seventh end of the capacitor charging and discharging circuit to be connected with the first end of the clock generating logic circuit, and the second end of the eighth PMOS tube (MP 8) is used as the eighth end of the capacitor charging and discharging circuit to be connected with the second end of the clock generating logic circuit.
2. The oscillator circuit of claim 1, wherein the self-starting circuit comprises: the first PMOS tube (MP 1), the sixth PMOS tube (MP 6) and the first resistor (R1), wherein:
the first end of the first PMOS tube (MP 1) and the first end of the sixth PMOS tube (MP 6) are used as the first ends of the self-starting circuit and are connected with the power supply end (VDD); the second end of the first PMOS tube (MP 1) is connected with the control end of the sixth PMOS tube (MP 6), the common end of the first PMOS tube is connected with the first end of the first resistor (R1), and the second end of the first resistor (R1) is used as the second end of the self-starting circuit to be connected with the grounding end (VSS);
the control end of the first PMOS tube (MP 1) is used as the third end of the self-starting circuit to be connected with the third end of the self-adaptive current generating circuit, and the second end of the sixth PMOS tube (MP 6) is used as the fourth end of the self-starting circuit to be respectively connected with the fourth end of the self-adaptive current generating circuit and the fourth end of the capacitor charging and discharging circuit.
3. The oscillator circuit according to claim 2, wherein the first PMOS transistor (MP 1) and the sixth PMOS transistor (MP 6) have a first terminal being a source, a second terminal being a drain, and a control terminal being a gate.
4. The oscillator circuit of claim 1, wherein the second PMOS transistor (MP 2), the third PMOS transistor (MP 3), the first NMOS transistor (MN 1) and the second NMOS transistor (MN 2) have a first end being a source, a second end being a drain, and a control end being a gate.
5. The oscillator circuit according to claim 1, wherein the first ends of the fourth PMOS transistor (MP 4), the fifth PMOS transistor (MP 5), the seventh PMOS transistor (MP 7), the eighth PMOS transistor (MP 8), the third NMOS transistor (MN 3), the fourth NMOS transistor (MN 4), and the fifth NMOS transistor (MN 5) are sources, the second ends are drains, and the control ends are gates.
6. The oscillator circuit of claim 1, wherein the clock generation logic circuit comprises: a first inverter (INV 1), a second inverter (INV 2), a third inverter (INV 3), and a D flip-flop (QF 1), wherein:
an input end of the first inverter (INV 1) is used as a second end of the clock generation logic circuit to be connected with an eighth end of the capacitor charge-discharge circuit, and an output end of the first inverter (INV 1) is connected with an input end of the second inverter (INV 2);
the output end of the second inverter (INV 2) is connected with the input end of the third inverter (INV 3), and the common end of the second inverter is used as the third end of the clock generation logic circuit and is connected with the fifth end of the capacitor charge-discharge circuit;
an output end of the third inverter (INV 3) is used as a fourth end of the clock generation logic circuit to be connected with a sixth end of the capacitor charge-discharge circuit, and an output end of the third inverter (INV 3) is connected with a first end of the D trigger (QF 1); the second end of the D trigger (QF 1) is connected with the third end of the D trigger (QF 1), and the fourth end of the D trigger (QF 1) is used as the output end of the clock generation logic circuit to output a periodic signal with the duty ratio of 50%.
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