CN100561864C - Self-starting current biasing circuit - Google Patents
Self-starting current biasing circuit Download PDFInfo
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- CN100561864C CN100561864C CNB2007101781770A CN200710178177A CN100561864C CN 100561864 C CN100561864 C CN 100561864C CN B2007101781770 A CNB2007101781770 A CN B2007101781770A CN 200710178177 A CN200710178177 A CN 200710178177A CN 100561864 C CN100561864 C CN 100561864C
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- 238000005516 engineering process Methods 0.000 description 6
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- 238000000034 method Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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- PICXIOQBANWBIZ-UHFFFAOYSA-N zinc;1-oxidopyridine-2-thione Chemical class [Zn+2].[O-]N1C=CC=CC1=S.[O-]N1C=CC=CC1=S PICXIOQBANWBIZ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a kind of self-starting current biasing circuit, comprising: enabling signal generator and biasing circuit, wherein, described enabling signal generator comprises: transistor, a PMOS pipe, resistance, electric capacity; Described transistor receives the external pulse signal, and with the grid of this pulse signal conducting to a described PMOS pipe, the duty ratio of described pulse signal is lower than preset first threshold value; One of described resistance is connected to the end that described transistor receives described pulse signal, the other end ground connection of this resistance; One of described electric capacity is connected to the grid of a PMOS pipe, the other end ground connection of this electric capacity; The source electrode of a described PMOS pipe is connected to power supply, and drain electrode is connected to the enabling signal input of described biasing circuit; The bias current output of described biasing circuit is connected to the generation source of described external pulse signal.This circuit can reduce current loss, the saving circuit area of start-up circuit and not be subjected to the influence of power supply electrifying speed.
Description
Technical field
The present invention relates to current biasing circuit, particularly relate to a kind of self-starting current biasing circuit at the low current loss oscillator.
Background technology
At present, general current biasing circuit is relatively independent module in the entire chip system, and this Module Design needs it enabling the normal startup in back to reach the constant bias current (biascurrent) of output.For different startup environment and current loss requirement, self-starting current biasing circuit design difficulty difference is very big.
Fig. 1 is the electrical block diagram of existing current biasing circuit.As shown in Figure 1, this circuit mainly is made up of two P channel MOS tubes of M1, M2 (PMOS pipe) and two N-channel MOS pipes of M3, M4 (NMOS pipe) and resistance R 6, and VCC is a supply voltage, the VSS earthed voltage.This circuit needs extraneous enabling signal input, enabling signal input input that enabling signal and bias current indicate from figure respectively and the output of bias current output, a logic skip signal after enabling signal herein refers to power on, for example: can trigger the logical pulse of an about 200ns of width with this logical signal, be used for temporarily drawing high the grid of M4 among Fig. 1 to force the equilibrium state of entire circuit disengaging zero current.
But above-mentioned current biasing circuit needs extraneous enabling signal input, can't realize self-starting.
For making the existing biasing circuit can self-starting, on existing biasing circuit basis, 3 kinds of improved self-starting current biasing circuits be arranged at present.
Fig. 2 is the electrical block diagram of existing self-starting current biasing circuit 1.As shown in Figure 2, this circuit is to have increased the start-up circuit part of being made up of PMOS pipe M0, resistance R 2 and capacitor C 0 on existing biasing circuit basis.Though this circuit does not need extraneous input enabling signal, but, for guaranteeing the operate as normal of start-up circuit part, require the power supply electrifying time to be far smaller than the time constant of resistance R 2 and capacitor C 0, thereby make the self-starting of current biasing circuit be subjected to the restriction of power supply electrifying time.
Fig. 3 is the electrical block diagram of existing self-starting current biasing circuit 2.As shown in Figure 3, this circuit is to have increased the start-up circuit part of being made up of two PMOS pipe M5, M6 and resistance R 3 on existing biasing circuit basis.This circuit does not need extraneous enabling signal input, and is applicable to supply voltage the VCC unknown or very slow environment of speed that powers on of speed that powers on.Do not start operate as normal afterwards because the starting current of this circuit is not participated in biasing circuit directly, therefore the bias current that is produced is not subjected to the influence of start-up circuit.But the current drain that above-mentioned start-up circuit partly produces is bigger, thereby then needs resistance R 3 to have bigger resistance increase circuit area if reduce current drain.
Average current consumption that need to suppose current biasing circuit and start-up circuit is up to 5V less than the average current of 200nA, start-up circuit less than 30nA and supply voltage VCC, then the resistance of resistance R 3 needs megaohms up to a hundred among Fig. 3, and this is unacceptable for little packaged chip.
Fig. 4 is the electrical block diagram of existing self-starting current biasing circuit 3.M1 replaces with resistance R 5 with the pipe of the PMOS in the current biasing circuit as shown in Figure 1, can obtain self-starting current biasing circuit 3 as shown in Figure 4.This circuit does not need extraneous enabling signal input, and is applicable to supply voltage the VCC unknown or very slow environment of speed that powers on of speed that powers on.Compare with existing self-starting current biasing circuit 2, influence and current drain that the bias current that this circuit produced will be subjected to starting current are also bigger.With Fig. 3 in like manner, thereby if reduce current drain and then need resistance R 3 to have bigger resistance to increase circuit area.If the long channel PMOS pipe of 5 usefulness of the resistance R among Fig. 4 is replaced, consider supply voltage VCC excursion (1.5V～5V), it is still bigger that required metal-oxide-semiconductor accounts for silicon area, for example: for 1.2um technology, the PMOS pipe of channel width W/ channel length L=1800/2, the about 6300um of its shared circuit area
2, and the channel length of this PMOS pipe device model (foundry model) that provides of the technology scope that can guarantee head and shoulders above, thereby be difficult to realize.
As seen, the existing biasing circuit of realizing self-starting perhaps is subjected to the influence of power supply electrifying speed or has bigger current loss or need take bigger circuit area.
Summary of the invention
Problem at existing self-starting biasing circuit exists the present invention proposes a kind of self-starting current biasing circuit, and this circuit can reduce current loss, the saving circuit area of start-up circuit and not be subjected to the influence of power supply electrifying speed.
For solving the problems of the technologies described above, the technical scheme that the present invention proposes is:
A kind of self-starting current biasing circuit comprises: enabling signal generator, biasing circuit and the 2nd PMOS pipe, wherein,
Described enabling signal generator comprises: transistor, a PMOS pipe, resistance, electric capacity;
Described transistor receives the external pulse signal, and with the grid of this pulse signal conducting to a described PMOS pipe, the duty ratio of described pulse signal is lower than preset first threshold value;
One of described resistance is connected to the end that described transistor receives described pulse signal, the other end ground connection of this resistance;
One of described electric capacity is connected to the grid of a PMOS pipe, the other end ground connection of this electric capacity;
The source electrode of a described PMOS pipe is connected to power supply, and drain electrode is connected to the enabling signal input of described biasing circuit;
The bias current output of described biasing circuit is connected to the grid of the 2nd PMOS pipe, and another PMOS tube source grade is connected to power supply, leaks the generation source that level is connected to described external pulse signal.
Described transistor is the NPN triode,
The base stage of described NPN triode receives the external pulse signal, and source electrode, the emitter that collector electrode is connected to a described PMOS pipe is connected to the grid of a described PMOS pipe.
Described transistor is a diode,
The anode of described diode receives the external pulse signal, and negative electrode is connected to the grid of a described PMOS pipe.
The generation source of described external pulse signal can be oscillator, and the bias current input of this oscillator links to each other with the leakage level of described the 2nd PMOS pipe.
Described self-starting current biasing circuit may further include: described the 2nd PMOS pipe is between the bias current input of the bias current output of described biasing circuit and described oscillator.
The current loss of this oscillator can be received peace less than 500.
The speed of powering on of described power supply can be less than default second threshold value.
The resistance of the resistance of described enabling signal generator can be less than 1 megaohm.
The present invention also provides a kind of enabling signal generator, comprising: transistor, a PMOS pipe, resistance, electric capacity;
Described transistor receives the external pulse signal, and with the grid of this pulse signal conducting to a described PMOS pipe, wherein, the duty ratio of described pulse signal is lower than preset first threshold value;
One of described resistance is connected to the other end ground connection that described transistor receives an end of described pulse signal, described resistance;
One of described electric capacity is connected to the other end ground connection of the grid of a PMOS pipe, described electric capacity;
The source electrode of described PMOS pipe is connected to power supply, draining is connected to the enabling signal input of external bias circuit, and grid, the source class that the bias current output of described external bias circuit is connected to the 2nd PMOS pipe is connected to power supply, leaks the generation source that level is connected to described external pulse signal.
As seen from the above technical solution, a kind of self-starting current biasing circuit that the present invention proposes, after bias current produces, external oscillator promptly can be to the pulse signal of enabling signal generator input low duty ratio, when the logic of input when being high, the NPN transistor base that this signal can drive the enabling signal generator makes the NPN triode to the electric capacity iunjected charge, because the end leakage current over the ground that electric capacity links to each other with the NPN transistor emitter is far smaller than the injection current from the NPN transistor emitter, therefore, through several charge cycles, link to each other with the NPN transistor emitter voltage of an end of electric capacity can rise to supply voltage and deducts the base stage of NPN triode and the voltage between the emitter, again since this moment source electrode to the voltage between the grid of a PMOS pipe equal the base stage of NPN triode and the voltage between the emitter, and because therefore the base stage of technology NPN triode and the voltage between the emitter, can determine that this moment, the one PMOS pipe no longer injected starting current to biasing circuit less than the threshold voltage of a PMOS pipe.
This shows, because pulse signal has than low duty ratio, thereby can reduce the current loss of start-up circuit, and also not need big resistance resistance, thereby save circuit area.And this circuit also is not subjected to the influence of power supply electrifying speed.
Description of drawings
Fig. 1 is the electrical block diagram of existing current biasing circuit;
Fig. 2 is the electrical block diagram of existing self-starting current biasing circuit 1;
Fig. 3 is the electrical block diagram of existing self-starting current biasing circuit 2;
Fig. 4 is the electrical block diagram of existing self-starting current biasing circuit 3;
Fig. 5 is the block diagram that is connected of self-starting current biasing circuit of the present invention and external oscillator;
Fig. 6 is the electrical block diagram of the self-starting current biasing circuit in the embodiment of the invention one;
Fig. 7 is the electrical block diagram of the self-starting current biasing circuit in the embodiment of the invention two.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
The present invention is a kind of self-starting current biasing circuit at the low current loss oscillator, this circuit provides bias current for the oscillator in the same chip, for example, current loss is lower than the low current loss oscillator of 500nA, and the output of the bias current of this circuit promptly is the enabling signal of oscillator.
Fig. 5 is the block diagram that is connected of self-starting current biasing circuit of the present invention and external oscillator.As shown in Figure 5, self-starting current biasing circuit of the present invention comprises enabling signal generator and biasing circuit two parts, wherein the enabling signal generator sends enabling signal to biasing circuit, biasing circuit output offset electric current is to outside oscillator, and oscillator sends the low-duty-cycle pulses signal to the enabling signal generator.Before the bias current of self-starting current biasing circuit produced, the oscillator pulses output signal was a logic low, after bias current produces, and oscillator starting oscillation, and output logic clock signal.
Embodiment one
Fig. 6 is the electrical block diagram of the self-starting current biasing circuit in the embodiment of the invention one.As shown in Figure 6, this circuit comprises: enabling signal generator, biasing circuit and a PMOS pipe M9.Wherein, the enabling signal generator comprises: PMOS manages M8, NPN triode Q0, resistance R and capacitor C 2.
The base stage of Q0 receives the low-duty-cycle pulses signal of external oscillator, the source electrode that collector electrode is connected to M8, the grid that emitter is connected to M8; One of resistance R is connected to base stage, the other end ground connection of Q0; One of capacitor C 2 is connected to emitter, the other end ground connection of Q0; The source electrode of M8 is connected to power supply, draining is connected to the enabling signal input of described biasing circuit.
Biasing circuit in the self-starting current biasing circuit in the present embodiment is identical with the biasing circuit of prior art, and the bias current output of biasing circuit is connected to the grid of PMOS pipe M9; The source electrode of M9 is connected to power supply, drain electrode is connected to the bias current input of external oscillator, it is pointed out that M9 is mainly used in the oscillator that activates the outside after receiving bias current, both oscillator can be positioned at, also biasing circuit one side can be positioned at as shown in Figure 6.That is to say that if comprised PMOS pipe M9 in the external oscillator, the self-starting current biasing circuit in the present embodiment then can not comprise this PMOS pipe M9; Otherwise in order to activate outside oscillator, the self-starting current biasing circuit in the present embodiment need be managed M9 by PMOS and be linked to each other with external oscillator.
When oscillator does not start and no-output, be that pulse signal that oscillator exports the enabling signal generator to is can see logic low as the time, the capacitor C 2 of enabling signal generator is to M8 electric leakage of the grid path is arranged between the power supply, parasitic oppositely PN junction and C2 Leaked Current of Line to Ground path among the Q0 are arranged over the ground, regulate M8 and Q0, the ratio of C2 is to guarantee that C2 goes up electric charge and can be discharged into ground by electric leakage.
VCC powers on when power supply, no matter its speed that powers on is still slow soon, as long as supply voltage is enough high, M8 just can be to the grid iunjected charge of M4, thereby produce enabling signal and export the enabling signal input that starts biasing circuit to, and then current biasing circuit produces bias current.
After oscillator receives the bias current of M9 drain electrode output of biasing circuit, promptly can start and output pulse signal, when the pulse signal of output is logic high, this signal can drive the Q0 base stage makes Q0 to the C2 iunjected charge, because the end leakage current over the ground that C2 links to each other with the Q0 emitter is far smaller than the injection current from Q0, therefore, through several charge cycles, the voltage of C2 can rise to VCC-Vbe, and wherein, Vbe is the base stage of Q0 and the voltage between the emitter.Because the source electrode of M8 is to the voltage V between the grid this moment
SGTherefore=Vbe and already known processes Vbe can determine that less than the threshold voltage of PMOS pipe this moment, M8 no longer injected starting current to biasing circuit.So far, the current biasing circuit self-starting finishes.
Because the duty ratio of the logic clock signal that oscillator produced is very little usually, therefore, no matter the time length of start-up course and do not need very big resistance R, can guarantee can be less by the current loss that resistance R produced in this self-starting current biasing circuit.
For example, the speed that powers on of supposing power supply VCC is less than the second default threshold value, for example be 1V/S, resistance R is less than 1 megaohm, and the duty ratio of the pulse signal of oscillator output is less, the average current loss that then can guarantee start-up circuit is less than 10nA, and because resistance R does not need very greatly, therefore also can not take bigger circuit area.
Embodiment two
Than embodiment one, present embodiment replaces the NPN triode Q0 among Fig. 6 for diode D0.
Fig. 7 is the electrical block diagram of the self-starting current biasing circuit in the embodiment of the invention two.As shown in Figure 7, this circuit comprises: enabling signal generator, biasing circuit and a PMOS pipe M9.Wherein, the enabling signal generator comprises: PMOS manages M8, diode D0, resistance R and capacitor C 2.
Low-duty-cycle pulses signal, negative electrode that the anode of diode D0 receives external oscillator are connected to the grid that PMOS manages M8; One of resistance R is connected to anode, the other end ground connection of D0; One of capacitor C 2 is connected to negative electrode, the other end ground connection of D0; The source electrode of M8 is connected to power supply, draining is connected to the enabling signal input of described biasing circuit.
Biasing circuit in the self-starting current biasing circuit in the present embodiment is identical with the biasing circuit of prior art, and the bias current output of biasing circuit is connected to the grid of PMOS pipe M9; The source electrode of M9 is connected to power supply, and drain electrode is connected to the bias current input of external oscillator, it is pointed out that the oscillator that M9 is mainly used in to the outside provides bias current, both can be positioned at oscillator, also can be positioned at biasing circuit one side as shown in Figure 7.That is to say that if comprised PMOS pipe M9 in the external oscillator, the self-starting current biasing circuit in the present embodiment then can not comprise this PMOS pipe M9; Otherwise in order to activate outside oscillator, the self-starting current biasing circuit in the present embodiment need be managed M9 by PMOS and be linked to each other with external oscillator.
When oscillator does not start and no-output, be that pulse signal that oscillator exports the enabling signal generator to is can see logic low as the time, the capacitor C 2 of enabling signal generator is to M8 electric leakage of the grid path is arranged between the power supply, parasitic oppositely PN junction and C2 Leaked Current of Line to Ground path among the D0 are arranged over the ground, regulate M8 and D0, the ratio of C2 is to guarantee that C2 goes up electric charge and can be discharged into ground by electric leakage.
VCC powers on when power supply, no matter its speed that powers on is still slow soon, as long as supply voltage is enough high, M8 just can be to the grid iunjected charge of M4, thereby produce enabling signal and export the enabling signal input that starts biasing circuit to, and then current biasing circuit produces bias current.
After oscillator receives the bias current of M9 drain electrode output of biasing circuit, promptly can start and output pulse signal, when the pulse signal of output is logic high, this signal can drive the D0 anode makes D0 to the C2 iunjected charge, because the end leakage current over the ground that C2 upward links to each other with the D0 negative electrode is far smaller than the injection current from D0, therefore, through several charge cycles, the voltage of C2 can rise to VCC-Vpn, and wherein, Vpn is the positively biased on state threshold voltage of diode D0.Because the source electrode of M8 is to the voltage V between the grid this moment
SGTherefore=Vpn and already known processes Vpn can determine that less than the threshold voltage of PMOS pipe this moment, M8 no longer injected starting current to biasing circuit.So far, the current biasing circuit self-starting finishes.
Because the duty ratio of the logic clock signal that oscillator produced is very little usually, therefore, no matter the time length of start-up course and do not need very big resistance R, can guarantee can be less by the current loss that resistance R produced in this self-starting current biasing circuit.
By above-mentioned two embodiment as seen, self-starting current biasing circuit provided by the present invention not only can be realized the self-starting of current biasing circuit, can also reduce start-up circuit current loss, save circuit area and be not subjected to the influence of power supply electrifying speed.
By contrast, adopted NPN triode Q0 among the embodiment one, its driving force is better than the diode D0 among the embodiment two, thereby start-up course is faster; But the diode D0 among the embodiment two is lower to the requirement of processing technology, thereby cost is lower.In the practical application, can select to plant arbitrarily embodiment as required.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of self-starting current biasing circuit is characterized in that, this circuit comprises: enabling signal generator, biasing circuit and the 2nd PMOS pipe, wherein,
Described enabling signal generator comprises: transistor, a PMOS pipe, resistance, electric capacity;
Described transistor receives the external pulse signal, and with the grid of this pulse signal conducting to a described PMOS pipe, the duty ratio of described pulse signal is lower than preset first threshold value;
One of described resistance is connected to the end that described transistor receives described pulse signal, the other end ground connection of this resistance;
One of described electric capacity is connected to the grid of a PMOS pipe, the other end ground connection of this electric capacity;
The source electrode of a described PMOS pipe is connected to power supply, and drain electrode is connected to the enabling signal input of described biasing circuit;
Grid, the source class that the bias current output of described biasing circuit is connected to the 2nd PMOS pipe is connected to power supply, leaks the generation source that level is connected to described external pulse signal.
2, self-starting current biasing circuit according to claim 1 is characterized in that, described transistor is the NPN triode,
The base stage of described NPN triode receives the external pulse signal, and source electrode, the emitter that collector electrode is connected to a described PMOS pipe is connected to the grid of a described PMOS pipe.
3, self-starting current biasing circuit according to claim 1 is characterized in that, described transistor is a diode,
The anode of described diode receives the external pulse signal, and negative electrode is connected to the grid of a described PMOS pipe.
According to each described self-starting current biasing circuit of claim 1 to 3, it is characterized in that 4, the generation source of described external pulse signal is an oscillator, the bias current input of this oscillator links to each other with the leakage level of described the 2nd PMOS pipe.
5, self-starting current biasing circuit according to claim 4 is characterized in that, described the 2nd PMOS pipe is between the bias current input of the bias current output of described biasing circuit and described oscillator.
6, self-starting current biasing circuit according to claim 4 is characterized in that, the current loss of this oscillator is received peace less than 500.
According to each described self-starting current biasing circuit of claim 1 to 3, it is characterized in that 7, the speed that powers on of described power supply is less than default second threshold value.
8, according to each described self-starting current biasing circuit of claim 1 to 3, it is characterized in that the resistance of the resistance of described enabling signal generator is less than 1 megaohm.
9, a kind of enabling signal generator is characterized in that, comprising: transistor, a PMOS pipe, resistance, electric capacity;
Described transistor receives the external pulse signal, and with the grid of this pulse signal conducting to a described PMOS pipe, wherein, the duty ratio of described pulse signal is lower than preset first threshold value;
One of described resistance is connected to the other end ground connection that described transistor receives an end of described pulse signal, described resistance;
One of described electric capacity is connected to the other end ground connection of the grid of a PMOS pipe, described electric capacity;
The source electrode of described PMOS pipe is connected to power supply, draining is connected to the enabling signal input of external bias circuit, and grid, the source class that the bias current output of described external bias circuit is connected to the 2nd PMOS pipe is connected to power supply, leaks the generation source that level is connected to described external pulse signal.
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| CNB2007101781770A CN100561864C (en) | 2007-11-27 | 2007-11-27 | Self-starting current biasing circuit |
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| CNB2007101781770A CN100561864C (en) | 2007-11-27 | 2007-11-27 | Self-starting current biasing circuit |
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| CN102098027B (en) * | 2009-12-15 | 2015-05-06 | 北京中星微电子有限公司 | Clock signal generating circuit |
| CN107071401B (en) * | 2017-02-17 | 2019-02-15 | 中国电子科技集团公司第二十四研究所 | Detection Log Video Amplifier self-checking circuit |
| CN108718191B (en) * | 2018-08-14 | 2023-09-19 | 上海艾为电子技术股份有限公司 | Oscillator circuit |
| CN110336558B (en) * | 2019-07-10 | 2024-02-13 | 深圳市锐能微科技有限公司 | Oscillator circuit and integrated circuit |
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