TWI387871B - Adaptive power control apparatus with delay estimation scheme - Google Patents

Description

Adaptive power control device with circuit delay evaluation mechanism

The present invention relates to a circuit delay evaluation and adaptive power control apparatus, and more particularly to an apparatus for environmentally adaptive dynamic power control.

In recent years, due to the rapid advancement of semiconductor process technology, the density of transistors and the complexity of the system have grown rapidly, and the design of controlling and reducing power consumption has become a subject that cannot be ignored. At present, there are some designs that reduce power consumption, as illustrated below:

U.S. Patent No. 7,276,932 discloses an architecture utilizing a virtual power gating cell (VPC), wherein the virtual power gating cell is controlled by a control circuit for buffering control signals and includes two or more NFETs. It is composed of a power gating block (PGB) of PFETs. However, the power gate cell is only used as a simple switch, that is, it can be turned on and off (connected or disconnected) only between the mounted circuit and the power source, except that it can be turned off. In addition to saving static power, there is no dynamic power control capability.

Also for example, M. Nakai (M. Nakai, S. Akui, K, Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, Dynamic Voltage And Frequency Management for a Low-Power Embedded Microprocessor, IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005) et al. The technology of frequency adjustment is used as a method to effectively reduce power consumption. This technique utilizes a delay synthesizer that combines gate delay, resistor-capacitor interconnect delay, and rise/fall delay to achieve a better critical path emulation. However, this conventional technique also uses a delay matching circuit in principle, and thus has the aforementioned drawbacks. In addition, M. Nakai needs a worst case critical path delay matching circuit when implementing adaptive or dynamic voltage modulation. However, the worst case actually occurs rarely, so it is large. To underestimate the possibility of reducing power, it is not suitable for today's high-speed circuits.

The power brakes and other settings of the prior art can only be used as switches, and can really save power in only a few states, resulting in failure to effectively reduce power consumption and achieve adaptive power control requirements. The present invention proposes a new The mechanism for judging the operation state of the circuit, by monitoring the voltage of the virtual voltage source (virtual-VDD, VDDV) of the power gate to determine the end timing of the circuit operation, and obtaining the delay information of the circuit, and operating through the proposed circuit The judgment method of the end timing is applied to the power control, so that the combined circuit has the power control with active and environmental variation adaptability, and solves the technical problem of the prior art.

In conjunction with the foregoing technical problems, the present invention provides an adaptive power control apparatus having a circuit delay evaluation mechanism, including: a multi-mode power gate network, a voltage sensor, a variable threshold comparator, and a redundancy interval. a detection circuit and a bidirectional displacement register, the multimode power gate network comprising a plurality of parallel transistors, when the multimode power gate network is connected between a power supply and a circuit module, each transistor a P-type transistor and the connection node of the multi-mode power gate network and the circuit module is regarded as a virtual voltage source. When the multi-mode power gate network is connected between a grounding point and the circuit module, Each transistor is an N-type transistor and the node between the multi-mode power gate network and the circuit module is regarded as a virtual ground point, wherein:

The input end of the voltage sensor is connected to the virtual voltage source or the virtual ground point, and it searches for a lowest voltage (VL) of the virtual voltage source or finds a highest voltage (VH) of the virtual ground point;

The variable threshold comparator is electrically connected to the output end of the voltage sensor, and compares whether the instantaneous voltage (VV) of the virtual voltage source and the minimum voltage (VL) satisfy a first specific relationship and outputs a first Comparing the result state, or the variable threshold comparator comparing the instantaneous voltage (VG) of the virtual ground point with the highest voltage (VH) to satisfy a second specific relationship and outputting a second comparison result state;

An input end of the redundant interval detecting circuit is connected to the variable threshold comparator, and according to the first or second comparison result state of the variable threshold comparator and a clock edge to detect whether a clock period exists Redundant interval

The input end of the bidirectional displacement register is electrically connected to the redundant interval detecting circuit, and the displacement is generated according to whether the redundant interval exists, so that the output states of the plurality of control signals of the bidirectional displacement register are changed. ;as well as

The multi-mode power gate network is connected to each control signal of the bidirectional displacement register, and each transistor is turned on or off by the state of each control control signal of the bidirectional displacement register, so that the multi-mode power gate network The power output to the circuit module is changed according to the existence of the redundant interval.

Wherein the first specific relationship satisfies the following formula:

Wherein VDD is the voltage supplied by the power source; Vth is a threshold voltage of the multi-mode power gate network and the P-type transistor in the circuit module; VD0 is a P-type transistor when VGS=VDD One of the drain saturation voltages; α is a velocity saturation index; λ is a P-type transistor channel length modulation parameter; and VDS0 is a predetermined threshold voltage value.

Wherein, the variable threshold comparator is a modified Schmitt trigger circuit.

Wherein, the voltage sensor comprises a sensing circuit of two transistors connected in series by a diode connection.

Wherein, when the VDS0 is 100 mV, the first specific relationship satisfies one of the following two formulas: VV 0.5685+0.4568. VL ; or VV 0.0902+1.7137. VL -0.8109. VL ² .

Wherein the second specific relationship satisfies the following formula: Wherein, VDD is the voltage supplied by the power source; Vth is a threshold voltage of the multi-mode power gate network and the N-type transistor in the circuit module; and VD0 is an N-type transistor when VGS=VDD One of the drain saturation voltages; α is a velocity saturation index; λ is an N-type transistor channel length modulation parameter; and VDS0 is a predetermined threshold voltage value.

Wherein, when the VDS0 is 100 mV, the second specific relationship satisfies one of the following two formulas: VG -0.01729+0.4424. VH ; or VG 0.0045+0.1810. VH +0.5810. VH ² , the voltage unit is volts (V).

Thereby, the present invention has the following advantages:

1. Dynamically monitoring the virtual voltage source to determine the delay of the circuit module and the existence of the redundancy interval, and thereby controlling the power output to the circuit module to achieve the technical effect of reducing power consumption.

2. The method of the present invention has low correlation with environmental parameters and, therefore, has high environmental adaptability.

3. The present invention allows the circuit module to use all available clock lengths as much as possible by judging the redundancy condition. Therefore, when the present invention is applied to various circuit modules, it has the lowest at various operating frequencies. Power consumption for optimal energy efficiency.

First, in order to explain one of the circuit delay evaluation schemes of the adaptive power control device with the circuit delay evaluation mechanism proposed by the present invention, please refer to the first figure, which shows that a 16-bit multiplier is in operation. One of the power terminals draws a drained current. The state of the multiplier can be divided into a stable state and a switching state. In the steady state, the current draw contains only a small amount of leakage current, but in the switching state, the multiplier draws a large amount of the current drawn from the power supply terminal to perform the multiplication operation. It can be seen from the above that by determining the change in the magnitude of the current drawn, the working state of the multiplier can be determined, and when the working state of the multiplier is distinguished, a delay time evaluation of the multiplier during operation can be obtained ( Delay estimation).

In order to further apply the foregoing examples to other circuits and to facilitate the explanation that the aforementioned delay time evaluation method is actually applied to other circuit modules, please refer to the second and third figures, with one of the simplest CMOS inverters. As an illustrative example:

As shown in the second figure, the inverter is connected to an ideal power supply (VDD). When one of the inverters (input node, IN) is switched from the high level to the low level, the reverse The P-type MOS transistor (PMOS, P1) is turned on and the current (VDD) draws current to charge one of the inverters (output node, OUT), and the output is switched to the high-precision Bit, however, the decision to use whether to complete the switch between the high and low levels of the output is usually based on a static Criterion determination, that is, the voltage at the output must be set to the power level (ie, The voltage level provided by the power supply VDD) or a fixed power supply level such as 90% of the power supply level.

The so-called "delay time" is defined as the time from the start of the switching of the input terminal to the completion of the switching of the output terminal in the circuit module or the digital circuit. Therefore, in the inverter of the previous example, the delay time is from the start of the switching of the input terminal to the time when the output reaches 90% VDD. According to this definition, this delay time is affected by the criterion of the aforementioned handover.

And if a power gating device (PG) is connected in series between the inverter and the power source (VDD), as a switching switch between the subsequent circuit component and the power source, the power gate component is a circuit module The same components used in P-type transistors. The power gate element (PG) can adopt an N-type or P-type transistor according to design requirements. If an N-type transistor is used as the power gate element (PG), the power gate element of the N-type transistor (PG) ) is connected between the circuit module (this is an inverter) and a ground point (GND).

As shown in the third figure, it is assumed that the power gate element (PG) and the P-type MOS transistor (P1) of the inverter are connected to each other as a virtual voltage source (Virtual-VDD, VDDV). The voltage source (VDDV) exhibits a fall-then-rise trend during the switching between the high and low levels of the inverter, so that the power supplied by the power gate element (PG) to the inverter is also The change is that the drained current is relatively small in the presence of the power gate element (PG) than the inverter directly connected to the ideal power source, mainly because of the power gate element (PG). ) increased impedance caused by. Therefore, the switching slope of the output (OUT) is relatively slower than the inverter directly connected to the ideal power supply. In other words, the voltage at the output (OUT) is increased to 90% of the ideal power supply (VDD). The delay time required to become a high level, the worst may be more than twice the connection of the power gate component (PG), so simply determine whether the output (OUT) voltage reaches a certain level ( For example, up to 90% VDD) is no longer suitable for the current high-speed switching requirements, because the state of the inverter has already been switched, the excess delay time is only wasted on the voltage level of the output (OUT) and The voltage of the virtual voltage source (VDDV) is boosted to the voltage level provided by the power supply (VDD). Therefore, in order to avoid the problem of the aforementioned fixed type judgment criterion, the present invention proposes a delay time evaluation mechanism in the operation of the circuit. Taking the foregoing third figure as an example, if it is assumed that the inverter completes the state switching, it is determined as a point B, wherein the point B is selected by the drain source voltage drop of the P-type MOS transistor (P1) ( VDS) is equal to a preset threshold voltage (VDS0). The preset threshold voltage can be selected by a rule of thumb to a relatively small value, such as 100 mV. The drain source voltage drop is used by the P-type MOS transistor (P1) to continue the output terminal after the switching is completed ( The voltage level of OUT) is raised to the voltage level provided by the power supply (VDD). At point B, the drain current of the power gate element (PG) is equal to the drain current of the P-type MOS transistor (P1).

However, as described above, after the inverter voltage level exceeds point B, the current is continuously drawn to bring the voltage of the virtual voltage source (VDDV) to the highest voltage level (VDD). As the voltage of the virtual voltage source (VDDV) rises, the drain-source voltage drop (VDS) of the power gate element (PG) decreases as the voltage of the virtual voltage source (VDDV) rises, making it smaller. Current is passed through the power gate element (PG). In other words, because the power of the power gate element (PG) at point B is equal to the current of the P-type MOS transistor (P1), after passing through point B, the power gate element flows through ( The current of PG) continues to decrease. Therefore, when it is observed that the current of the P-type MOS transistor (P1) of the inverter at point B is greater than (or equal to) the drain current of the power gate element (PG) after passing point B, It can be said that the inverter has completed state switching operation (wherein the P-type MOS transistor (P1), the power gate element (PG) operates in a linear region). Accordingly, when the alpha power model of the past literature is used to describe the voltage and current behavior of the transistor, the aforementioned inequality relationship can be described by the following formula (1):

among them:

ID0C is the current of the above-mentioned inverter circuit (specifically, its P-type gold-oxygen semiconductor (P1)) under the condition of VGS=VDS=VDD, which is related to the size parameter of the transistor (for example: electricity) The width and length of the channel of the crystal);

ID0PG is the current of the aforementioned power gate element (PG) under the condition of VGS=VDS=VDD;

Vth is the threshold voltage of the transistor;

VV is the transient value of the virtual voltage source (VDDV) as a function of time;

VDS0 is the aforementioned preset threshold voltage value.

The correlation of the aforementioned parameters related to the transistor size can be obtained from point A in the third figure. The point A, which corresponds to the lowest voltage point (VL) of the virtual voltage source (VDDV), represents the time at which the current through the power gate element (PG) is maximum, and is also the time at which the inverter is switched; wherein the voltage The lowest point (VL) is not constant, with the transistor size parameter of the power gate element (PG), the circuit module of the power gate element (PG) connected in series (for example, the inverter of this example), and the circuit Operating conditions: etc. vary. At point A, the power gate element (PG) is the same as the drain current of the P-type MOS transistor (P1), and the P-type MOS transistor (P1), the power gate The elements (PG) operate in a saturation region and a linear region, respectively. Therefore, the current equal to point A can be expressed as equation (2):

among them:

When VD0 is VGS=VDD, the drain saturation voltage of the P-type transistor used in this embodiment;

α is a velocity saturation index;

λ is a channel length modulation parameter;

Further, the ID0C of the formula (1) is replaced by the formula (2), and the formula (1) can be rewritten as the following formula (3):

...(3)

It can be seen from the above formula (3) that parameters such as ID0C and ID0PG which are dependent on (related to) the size parameter of the transistor are eliminated under the aforementioned simplified basis, and represent the aforementioned delay time evaluation mechanism and the power gate element (PG). Regardless of the size parameter of the circuit component, the aforementioned delay time evaluation mechanism is only related to VV, VL, that is, related to the dynamic response behavior of the virtual voltage source (VDDV), and therefore, the judgment mechanism referred to in the present invention is tolerable. The effectiveness of environmental variability.

If the power gate element (PG) is an N-type transistor, the node between the N-type transistor and the ground point (GND) is called a virtual ground point (Virtual GND, VGND), and the aforementioned dummy voltage. The difference between the point (VDDV) is that the virtual ground point (VGND) has a tendency to rise first and then fall during the high-level level switching of the inverter, that is, the voltage at the virtual ground point has the highest voltage. Point (VH); and the above formula derived from the P-type transistor, after replacing the N-type/P-type characteristic formula and the N-type/P-type characteristic parameters of the adopted process, the concept mentioned in the foregoing can be directly used; For example, with respect to the above formula (3), if the power gate element (PG) is an N-type transistor, the equation (3) can be changed to the following equation (3.1):

among them:

VDD is the voltage supplied by the power supply;

VG is the transient value of the virtual ground point (VGND) as a function of time;

Vth is a threshold voltage of the multi-mode power gate network and the N-type transistor in the circuit module;

VD0 is one of the drain saturation voltage of the N-type transistor when VGS=VDD;

α is a velocity saturation index;

λ is an N-type transistor channel length modulation parameter; and

VDS0 is a preset threshold voltage value.

Please refer to the fourth figure, which is a graphical solution drawn by the parameters VL and VV in the third figure. The two sides of the equation (3) are respectively two independent polynomials, and VL and VV are variables of two polynomials respectively. The left and right half of the formula (3) can be respectively drawn into the circular line of the fourth figure ( , f(VL)) and rectangular label lines ( , f(VV)), wherein the VDS0 of the formula (3) is set to 100 mV here. By using the parameter VL as the self-variable, the minimum value of the parameter VV can be obtained in the fourth figure under the condition that the formula (3) is satisfied, and the value of the VL is repeatedly changed to obtain a relatively complete relationship between the parameter VL and the VV. By using the linear value of the VL, VV relationship value group, the following inequality (4) is obtained:

VV 0.5685+0.4568‧ VL ...(4)

Alternatively, the quadratic equation can be used to obtain the following inequality (5):

VV 0.0902+1.7137‧ VL -0.8109‧ VL ² ...(5)

The units of the above formulas (4) and (5) are volts, and the unequal relationships between the description parameters, VL, and VV are respectively depicted in the fifth figure.

Following the similar derivation process of equations (4) and (5) above, when the power gate element (PG) is an N-type transistor, the inequalities for the N-type transistor relative to (4) and (5) are as follows. The following formula:

VG -0.01729+0.4424‧ VH ...(4.1)

VG 0.0045+0.1810‧ VH +0.5810‧ VH ² ...(4.2)

Wherein, the voltage units of the formulas (4.1) and (4.2) are volts (V).

The steps of the foregoing and the delay time evaluation mechanism disclosed in the formula (3) may include:

(i) start/reset;

(ii) drawing the lowest voltage VL of the virtual voltage source (VDDV);

(iii) monitoring the virtual voltage source (VDDV) and the voltage minimum point VL to satisfy the value of equation (4) or (5);

(iv) Completion of the delay time assessment.

In summary, the voltage lowest point VL of the virtual voltage source (VDDV) can be found in the state switching process of the circuit (here, the inverter), and the voltage of the virtual voltage source (VDDV) passes through the lowest voltage point. It must be continuously raised to satisfy the above equation (4) or (5) to determine that the switching state of the circuit has been completed.

Referring to the sixth figure, when the power supply is connected to a 16-bit multiplier (PG), the delay of the multiplier (11) can also be obtained according to the foregoing judgment mechanism. Time evaluation, however, after the research test results show that the delay evaluation mechanism proposed by the present invention is about 10% different from the delay of the actual circuit, therefore, it is necessary to add a margin of about 10% to 15% to the final delay. evaluation result.

Using the foregoing delay evaluation mechanism, a circuit block diagram of an adaptive power control (APC) device of the present invention can be as shown in the seventh figure, and the adaptive power control device includes a multi-mode power gate network. Multi-mode power gating network (21), a voltage sensor (23), a variable threshold comparator (24), and a redundant interval detection circuit (Slack Detection, 25) And a bidirectional displacement register (27), wherein the adaptive power control device of the embodiment can be applied to various circuit modules, such as the aforementioned multipliers, inverters, and the like. The logic circuit, the adaptive power control device of the embodiment is connected to a complementary CMOS circuit (30).

The output and input ends of the multi-mode power gate network (21) are electrically connected to the circuit module (30) and the bidirectional displacement register (27), and the voltage sensor (23) is connected to the multi-mode The power gate network (21) and the circuit module (30) are connected to one of the virtual voltage sources (VDDV), and the output of the voltage sensor (23) is connected to the variable threshold comparator (24), and the The variable threshold comparator (24), the redundant interval detector (25), the bidirectional displacement sensor (27), and the multi-mode power gate network (21) are serially connected in sequence.

Referring to FIG. 8 , the multi-mode power gate network (21) of the embodiment includes a plurality of P-type gold oxides connected in parallel and serially connected between the ideal power source (VDD) and the circuit module (30). A semi-transistor (PMOS) in which the gate of each P-type MOS transistor is connected to a control signal (Ctrl4~0) stored by the bidirectional displacement sensor (27). According to the foregoing description, the addition of the power gate element (PG) causes a voltage drop of the virtual voltage source of the connected circuit module, and therefore, the smaller the size parameter of the added power gate element (PG), The greater the voltage drop condition, such a voltage drop condition can be considered as the supply noise input to the circuit module. When the voltage drops, the delay in the circuit module is reflected. Therefore, the multi-mode power gate network (21) can selectively turn on the multi-mode power gate network by selectively driving the control signal (Ctrl4~0). The P-type metal oxide semi-transistor (PMOS) of the circuit (21) further affects or controls the delay of the circuit module.

Further, each power gate element (PG) of the multi-mode power gate network (21) may have different channel size parameters, and the power source is output to the circuit module through the multi-mode power gate network (21). The power can be generated by switching various power gate elements (PG) to produce a variety of different combinations.

Referring to the ninth figure, the voltage sensor (23) of the embodiment comprises two transistors (MP1, MP2) connected in a diode-connected manner, wherein the circuit module works. During the switching process, one of the VL nodes connected to the transistor (MP2) can obtain the lowest voltage of the virtual voltage source (VDDV).

Referring to the tenth figure, the variable threshold comparator (24) of the embodiment is a modified Schmitt Trigger, and the Schmitt trigger circuit is pre-charged by a pulsed clock. (precharged). The variable threshold comparator (24) is connected to the VL node of the transistor (MP2) of the voltage sensor (23), and a variable threshold is controlled by the VL node (for reverse control, such as i_VL in the tenth figure). Therefore, the variable threshold comparator (24) can judge whether the instantaneous voltage (VV) of the virtual voltage source (VDDV) in the equation (4) or the equation (5) is saturated or not. In other words, the variable threshold comparator (24) compares the VL node of the voltage sensor (23) (such as i_VL in the tenth figure) and the instantaneous voltage of the virtual voltage source (VV in the tenth figure) Whether the formula (4) or (5) is satisfied. When the output of the variable threshold comparator (24) is switched to the low level to form an assertion of the comparator and output, it indicates that the circuit module has completed the switching operation. When the transistor used in the power gate network (21) is N-type, the circuit of the voltage sensor (23) and the variable threshold comparator (24) needs to be modified, and can be changed to Detecting the voltage variation characteristic of the virtual ground point (VGND); for example, the voltage sensor (23) must be modified to be connected to the virtual ground point (VGND), and the internal circuit must be modified to sense the The voltage at the virtual ground point (VGND) changes.

The redundant interval detecting circuit (25) determines whether there is a redundant interval in the clock cycle by comparing the comparison result state of the variable threshold comparator (24) with a clock edge of a circuit operation ( Unused slack). The redundant interval refers to the time margin added in the clock cycle to prevent the delay time from increasing due to the change of the working environment, or the remaining clock due to the shortening of the operation time due to different circuit input data. length.

Referring to FIG. 11, the multi-mode power gate network (21) is connected to a plurality of control signals (Ctrl4~0) of the bidirectional displacement register (27), wherein when too many redundant intervals are found, The state "1" of the bidirectional displacement register (27) is shifted to the right to turn off the power gate of the multimode power gate network (21) (ie, P-type metal oxide semiconductor (PMOS)); When there is not enough redundant interval (when the timing margin is less than the timing margin required by the circuit module), the state of the two-way shift register (27) is shifted to the left to open more of the multi-mode. Power gate of the power gate network (21). The bidirectional displacement register (27) may be provided with a control signal such as reset, a hold, a power gating state, etc., respectively, as the bidirectional displacement The bits in the register (27) are reset to zero (turning on all power gates), maintaining the state of each bit in the two-way shift register (27), and turning off all power gates.

Generally, in the current technology, the speed specification of the circuit module during operation usually needs to consider the worst case of the process, voltage, temperature (Process, Voltage, Temperature, PVT) changes and must be in the clock specification. A lot of margins are added to ensure that the delay time of the circuit operation is not greater than the clock specification due to the change of the working environment, and the other circuits are prevented from causing chain errors and affecting the final operation result. However, during the use of the circuit module, the aforementioned worst case occurs rarely, so that a large amount of power input to the circuit module is wasted on the margins. The foregoing adaptive power control method and apparatus can determine whether the circuit module (30) exhausts all clock margins.

In addition, in some large-scale circuit modules, the delay time of non-critical paths also has a clock margin relative to the clock specification, so the same concept (determining whether the circuit has a redundant interval) may also Used in a non-critical path in a circuit module.

In addition, the adaptive power control method and apparatus of the present embodiment have characteristics that can tolerate various variations, because variations in temperature of all process voltages are reflected in the delay time of the circuit, and this embodiment can be used in the operation of the circuit module. Obtaining the delay condition of the circuit and actively using the margin in the circuit to achieve the technical effect of saving power.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally varied and modified. All should be included in the scope of the patent application of the present invention.

(twenty one). . . Multimode power gate network

(twenty three). . . Voltage sensor

(twenty four). . . Variable threshold comparator

(25). . . Redundant interval detection circuit

(27). . . Two-way displacement register

(30). . . Circuit module

The first figure is a schematic diagram of the current consumption performance of a multiplier.

The second figure is a schematic diagram of the state of the input and output voltages of an inverter switching.

The third figure is a schematic diagram of the input and output voltage states of a power gate and inverter circuit.

The fourth figure is a graphical solution diagram of a delay time evaluation mechanism with a virtual voltage source as the monitoring object.

The fifth graph is a schematic diagram of the straight/curve seeking results of a delay time evaluation mechanism.

The sixth figure is a circuit diagram of a multiplier containing a power gate.

The seventh figure is a block diagram of an adaptive power control device circuit.

The eighth figure is a circuit diagram of a multi-mode power gate network.

The ninth figure is a circuit diagram of a voltage sensor.

The tenth figure is a schematic diagram of a variable threshold comparator.

The eleventh figure is a schematic diagram of a bidirectional displacement register.

(twenty one). . . Multimode power gate network

(twenty three). . . Voltage sensor

(twenty four). . . Variable threshold comparator

(25). . . Redundant interval detection circuit

(27). . . Two-way displacement register

(30). . . Circuit module

Claims (7)

An adaptive power control device with a circuit delay evaluation mechanism includes: a multi-mode power gate network, a voltage sensor, a variable threshold comparator, a redundant interval detection circuit, and a bidirectional displacement temporary storage The multi-mode power gate network includes a plurality of parallel transistors. When the multi-mode power gate network is connected between a power source and a circuit module, each transistor is a P-type transistor and the multi-mode The connection node of the power gate network and the circuit module is regarded as a virtual voltage source; when the multi-mode power gate network is connected between a grounding point and the circuit module, each transistor is an N-type transistor and The node between the multi-mode power gate network and the circuit module is regarded as a virtual ground point, wherein: the input end of the voltage sensor is connected to the virtual voltage source or the virtual ground point, and the voltage sensor During the operation of the circuit module, repeatedly searching for a minimum voltage (VL) of the virtual voltage source or finding a highest voltage (VH) of the virtual ground point; the variable threshold comparator and the voltage sensor The output is electrically connected, Comparing whether a transient voltage (VV) of the virtual voltage source and the minimum voltage (VL) satisfy a first specific relationship and outputting a first comparison result state, or the variable threshold comparator compares the instantaneous voltage of the virtual ground point (VG) outputting a second comparison result state according to whether the highest voltage (VH) satisfies a second specific relationship; an input end of the redundant interval detecting circuit is connected to the variable threshold comparator, according to the variable threshold The first or second comparison result state of the comparator and a clock edge to detect whether there is a redundant interval in a clock cycle; the input end of the bidirectional displacement register and the redundant interval detecting circuit a sexual connection, which is displaced according to whether the redundant interval exists, so that an output state of the plurality of control signals of the bidirectional displacement register is changed; and each of the multi-mode power gate network and the bidirectional displacement register Controlling signal connection, each transistor being turned on or off by the state of each control control signal of the bidirectional displacement register, so that the multi-mode power gate network changes the power output to the circuit mode according to the existence condition of the redundant interval Group power. An adaptive power control device with a circuit delay evaluation mechanism as described in claim 1, wherein the first specific relationship satisfies the following formula: Wherein VDD is the voltage supplied by the power source; Vth is a threshold voltage of the multi-mode power gate network and the P-type transistor in the circuit module; VD0 is a P-type transistor when VGS=VDD One of the drain saturation voltages; α is a velocity saturation index; λ is a P-type transistor channel length modulation parameter; and VDS0 is a predetermined threshold voltage value. An adaptive power control device with a circuit delay evaluation mechanism as described in claim 1, wherein the second specific relationship satisfies the following formula: Wherein, VDD is the voltage supplied by the power source; Vth is a threshold voltage of the multi-mode power gate network and the N-type transistor in the circuit module; and VD0 is an N-type transistor when VGS=VDD One of the drain saturation voltages; α is a velocity saturation index; λ is an N-type transistor channel length modulation parameter; and VDS0 is a predetermined threshold voltage value. An adaptive power control device having a circuit delay evaluation mechanism as described in claim 1 or 2 or 3, wherein the variable threshold comparator is a modified Schmitt trigger circuit. An adaptive power control device having a circuit delay evaluation mechanism according to claim 1 or 2 or 3, wherein the voltage sensor comprises a sensing circuit of two transistors connected in series by a diode connection. For an adaptive power control device with a circuit delay evaluation mechanism according to claim 2, when the VDS0 is 100 mV, the first specific relationship satisfies one of the following two formulas: VV 0.5685+0.4568. VL ; or VV 0.0902+1.7137. VL -0.8109. VL ² , the voltage unit is volts (V). An adaptive power control device with a circuit delay evaluation mechanism according to claim 3, wherein the second specific relationship satisfies one of the following two formulas when the VDS0 is 100 mV: VG -0.01729+0.4424. VH ; or VG 0.0045+0.1810. VH +0.5810. VH ² , the voltage unit is volts (V).