TW201035738A - Adaptive power control apparatus with delay estimation scheme - Google Patents

Abstract

An adaptive power control apparatus with delay estimation scheme comprises a multi-mode power gating network, a voltage sensor, a variable threshold comparator, a slack detection and a Bi-directional shift register. The multi-mode power gating network is serial connected between a voltage source and a circuit module to form a virtual VDD with the multi-mode power gating network therebetween. The multi-mode power gating network comprises multiple transistors that are selectively turned on to adjust the power into the circuit module, where the transistors are controlled by Bi-directional shift register to be turned on and off according to a detecting result of the slack detection.

Description

201035738 VI. Description of the Invention: [Technical Field] The present invention relates to a circuit delay evaluation and adaptive power control device, and more particularly to a device for environmentally adaptive dynamic power (4): [Prior Art] In recent years, The rapid advancement of semiconductor process technology, the rapid growth of transistor density and system complexity, and the design of control and reduction of power consumption have become a topic that cannot be ignored. At present, there are some designs for reducing power consumption, which are exemplified as follows: U.S. Patent No. 7,276,932 discloses a virtual power gating ce (VPC) architecture in which the virtual power gate cell system It consists of a control circuit for buffering the control signal and a power gate block (PGB, p〇we "gating block" containing two or more NFETs and PFETs. However, the power gate cell is only used as a simple The switch, that is, only between the circuit and the power supply that is carried on and off (connected or disconnected), which can save static power in the closed state, and has no dynamic power control. For example, M. Nakai (M. Nakai, S. Akui > K > Seno, Τ· Meguro, Τ· Seki, T. Kondo, A· Hashiguchi, H. Kawahara, K. Kumano, and M Shimura * Dynamic

Voltage and Frequency Management for a Low-Power Embedded Microprocessor, IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 28-35, Jan. 2005) et al. ) Technology with frequency adjustment 201035738, as a method to effectively reduce power consumption. This technique utilizes a delay synthesizer that combines gate delay, t-resistance interconnect delay, and rise/down & delay to achieve a better critical path simulation (ni u丨a t i ο η). However, this prior art technique also employs a delay matching circuit in principle, thus also having the aforementioned drawbacks. In addition, 'M·Nakai needs a worst case critical path delay matching circuit when implementing adaptive or dynamic voltage modulation (wo "st case c"mca| path de|ay matching circujt), then n, take the situation In fact, it rarely occurs, so the underestimation of power reduction is greatly underestimated, so it is not suitable for today's high-speed circuits. [Disclosed] The power brakes and other settings of the prior art can only be used as switches. 'There can be real savings in only a few states (4), resulting in a failure to effectively reduce power consumption and achieve adaptive power control requirements. A new mechanism for judging the operational state of the circuit, #by monitoring the power of the 〇® source (10)tual_VDD, VDDV) The voltage is used to determine the timing of the circuit operation, and the delay of the circuit can be obtained. The method of judging the timing of the end of the operation through the proposed circuit is applied to the power control, and the circuit of the user is active and has environmental variation adaptability. The power control solves the technical problems of the prior art. In conjunction with the aforementioned technology, the stomach is provided by the present invention. Adaptive power control device, i. ', 匕έ. A multi-mode power 閙: circuit, - voltage sensing ϋ, a variable threshold comparator, a redundant measuring circuit and a bidirectional displacement register, ' ° θ ' > such as ° 夕 换 换 换 换 换 换 换 换 换 换 换 换 换 换 换 换 换 换 换 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交 交Each transistor of the 't ^ ^ ^ is a p-type transistor and the connection node of the multi-mode n network and the circuit module is regarded as a - virtual voltage source ': the multi-mode power closed network is connected to a ground point And the circuit module::: each transistor is an N-type transistor and the multi-mode power gate network and the node between the "group" are seen as a virtual ground point, wherein: the secret I "^ sense The input end is connected to the virtual voltage source or the virtual Ο 八 to find 4 virtual voltage sources - the lowest (four) (VL) or find the highest voltage (VH) of the double pseudo grounding point; And the output end of the voltage sensor is electrically connected to the second: whether the instantaneous voltage (vv) and the minimum voltage (VL) of the virtual voltage source are full a first-to-relationship outputting a first comparison result state 2, the variable threshold comparator comparing the instantaneous voltage of the virtual ground point (:) (four) the highest voltage (10)) satisfies the second specific relationship and outputs a second comparison result State; * 6 hai interval interval pre-measure circuit $ #人办山, 击μ crying circuit input knowledge is connected to the variable threshold comparison: according to the variable threshold comparator of the first or second comparison result state The edge of the clock is speculative - whether there is a redundant interval in the clock cycle; the #λ Α山&# input bat and the redundant interval detection circuit of the bidirectional displacement register: 妾, according to the redundancy Whether the interval exists and the displacement is generated, so that the output state of the plurality of control signals of the shift register to the shift register is changed; and the number is connected: ==:?Γ The control signal of the two-way shift register is two::= The :::::W system changes the power output to the circuit module. Wherein, the first specific lanthanum satisfies the following formula: 201035738 f VDD - F/;7 γ VDD-VL , vl-m ) ~\Tm7 -VDD-Vth + -VL {VDD - VV) --?->

• VDD - Vth + -VV

VDO

VDD — Vlh —— VDQ

VDSO m~2VDS〇 where VDD is the voltage supplied by the power supply;

Vth is the threshold voltage of the multi-mode power gate network and the p-type transistor in the circuit module; VD0 is one of the gate-saturation voltage of the P-type transistor when VGS=VD[) Saturation voltage); <2 is a speed saturation parameter (ve|0Cjty saturation index); λ is a p-type transistor channel modulation parameter (channe丨丨ength modulation parameter); and VDS0 is a preset threshold voltage value. Wherein, the variable threshold comparator is a modified Schmitt trigger circuit, wherein the delta voltage sensor comprises a sensing circuit of a diode connected in series by a diode connection. Where 'VDS0 is 100mV, the first specific relationship satisfies one of the following two formulas: FF >0.5685+ 0.4568-PX ; ^ heart 0.0902 +1.7137 · KZ - 〇.81〇n where 'the second specific The relationship satisfies the following formula:

(VDD-Vth) a VH VDD~Vth--VH --— 2 VG{vDD~Vth~~VG , l ? \ VDL) — V Η — Vi hJ 1 + A{VDD - VH) ( i λ VD〇 \ VDD-Vlh--VD0 \ 2 J ----, -/ ( , \ VDSQ VDD-VG-Vth-^VDSQ L 2 J where 201035738 VDD is the voltage supplied by the power supply;

Vth is a threshold voltage of the multi-mode power gate network and the n-type transistor in the circuit module; VD0 is a drain saturation voltage of the N-type transistor at VGS=VDD (drain saturation voltage) ο: is a speed saturation parameter (Ve|0Cjty saturatjori jnc|ex); into the N-type electric day a body channel length modulation parameter (channe丨丨ep) gth modulation parameter);

V D S 0 is a predetermined threshold voltage value. Where 'VDS0 4 100mV, the second specific relationship satisfies one of the following two formulas: KG<-0.01729 +0.4424 ·Κ// ; ^ (10)045 + 0•(8)0._Caf 2, the unit is volt (7) . Therefore, the present invention has the following advantages: 1. Dynamically monitoring the virtual voltage source 'by determining the delay of the circuit module" and the existence of the redundancy interval, and thereby controlling the output to the circuit module to reduce the power rate The technical effect of power consumption. 2 · The a ^ and the ancient ^ 10,000 method proposed by the present invention have low correlation with the 锿楗 parameter, and therefore, the environmental adaptability of the 彳艮咼 彳艮咼. 3 · The present invention can determine that y μ &, q can reduce the length of all available clocks, so that the circuit module can use the same circuit module as much as possible, so that the present invention can be applied to various types without optimal consumption. Energy efficiency. Knife shoulder 8 201035738 [Embodiment] First, a delay estimation scheme for an adaptive power control device with a circuit delay evaluation mechanism proposed by the present invention is referred to the first figure, Shows a 16-bit multiplication Is that draws current (dra丨ned current) from the power supply at work. The state of the multiplier can be divided into a steady state (stab|e) and a switching state. In the steady state, the current draw contains only a small amount of leakage current, but in the switching state, the multiplier draws a large amount of current drawn from the power supply terminal to perform multiplication. It can be seen from the above that by determining the change in the magnitude of the current drawn, the working state of the multiplier can be determined, and when the working state of the multiplier is distinguished, a delay time evaluation of the multiplier during operation can be obtained ( Delay estimati〇n). In order to further apply the foregoing examples to other circuits and to facilitate the explanation that the aforementioned delay time evaluation method is actually applied to other circuit modules, please refer to the second and third figures, with one of the simplest CM〇s inverters ( Inverter) as an example:

Cl, as shown in the second figure, the inverter is connected to an ideal power supply (vdd). When one of the inverters (input node, 丨N) is switched from the high level to the low level, The P-type MOS transistor (PM〇s, ρι) of the inverter is turned on, and the current is drawn by the power source (VDD) to charge one output terminal (〇UT) of the inverter, so that The output is switched to a high level. However, the judgment of whether to switch between the high and low levels of the round-trip end is usually adopted by a fixed-type criterion (static criteri〇n determinati〇n), that is, setting the The voltage at the output must reach the power level (that is, the voltage level provided by the power supply vdd) or a fixed power supply level such as 9〇% of the power supply level. The so-called "delay time" is fixed. For the circuit module or the digital circuit, the switch from the input end starts to the time when the switch to the + 士山丄 is finished. because

In the inverter of the previous example, the delay time A bites between the start of the input switching and the time when the output reaches 90% VDD. According to this definition, this delay time is affected by the above criteria for switching. And if the inverter is connected to the power supply (VDD) by a power gate component

(power gating device, PG) for helmet a P A

M is used as a switch between the circuit components of the after-performance circuit and the power source. The power gate element is the same component as the 电-type transistor used in the circuit module. The power idle component (PG) can be selected according to the design requirements of the N-type or P-type electro-crystal Μ 'If the N-type transistor is used as the power core WPCBm ' _ 电 $ the transistor of the power gate element (PG) is connected to § The circuit module (this is the inverter) and a ground point (G nd ). As shown in the third figure, 'assuming that the power gate element (PG) and the P-type MOS transistor (P1) of the inverter are connected to a virtual voltage source (Vir__ VDD' VDDV) 'the virtual voltage The source (VDDV) exhibits a tendency to drop first and then rise (fa丨丨_then_“ise) during the switching of the high and low levels of the inverter, so that the power request element (PG) is supplied to the inverter. The current also changes, that is, and the drained current is relatively small in the presence of the power gate element (PG) than the inverter is directly connected to the ideal power source, mainly because The power gate element (PG) increases the impedance. Therefore, the switching slope of the output (OUT) is relatively slower than the reverse benefit of directly connecting to the ideal power supply. In other words, the output (〇UT) The voltage is increased to 90% of the ideal power supply (VDD) to become the high-latency delay time, and the worst would be when the power gate element (pG) is not connected.] 0 201035738 Specific two:: Therefore, Simply judge whether the output (ουτ) voltage reaches 22ΓΓΓ90%) In the current high-speed switching demand, the excess certificate, the network * π is the same as it has already been switched over, and the I war time is only wasted in the # ψ M m II τ, and the virtual power source ( Vdd^m) The electrical waste level, (DDV) voltage is raised to the voltage level indicated by the power supply (VDD). Therefore, ΑA a as provided by the present invention proposes a Thunder The question is , Ο The delay time evaluation mechanism in the circuit work. The first picture of the former L is taken as an example, if

The judgment of the door state is a B', and the choice of the B point is by the 剂p agent λ* generation, "r 糟 由 ° ° P P P P P P P P P P P P P P The extreme voltage drop (VDs) is equal to the threshold voltage (VDS0) of the pre-existing <p pre-existing threshold. This pre-sighing threshold voltage can be a rule of thumb, a relatively small value of the j-domain, such as 100mV, this drain-source voltage drop It is used by the p-type full, jade oxygen + electric Japanese body (ρυ is used to continuously input the voltage of the output terminal (〇UT) after the switching is completed.

Electric & dry position soared to the power supply (VD: for the electric charge level. At point B, the power gate element (four)) current (d_CU_t), etc. ... type gold oxide semi-transistor " _ current) 〇 However, as described above, after the inverter's electric dust level exceeds B, the current is continuously drawn to bring the voltage of the virtual voltage source (VDDv) to the highest voltage level (VDD). As the voltage of the virtual voltage source (vddv) rises, the drain-source voltage drop (VDs) of the inter-power element (PG) decreases as the voltage of the virtual voltage source (VDDV) rises, . Drop, so that a smaller current passes through the inter-power component (PG)° in other words, because the current of the power-off element (PG) at point B is equal to the current of the p-type MOS transistor (drain current) ) 'With the point B, * 'a# , + ,. After that, the current flowing through the power gate element (pG) continues to decrease. Therefore, 'when the inverter is observed, p-type MOS half-powered 201035738 crystal (P1) current at point B is greater than (or equal to) the current (drain cu_t) of the power-off element (pG) after passing point B (drain cu_t) At this time, it can be said that the reverse piano has completed the state switching operation (where the p-type MOS transistor (p", the power-on element (PG) operates in the linear region (10) reg|_〇n). When the aipha p〇Wer _de| of the past literature is used to describe the voltage and current behavior of the transistor, the aforementioned unequal relationship can be described by the following formula (1): (1) 丨D0C is the aforementioned inverter circuit ( Specifically refers to the current (drain current) of its p-type MOS transistor (P1) under the condition of VGS = VDS = VDD, which is related to the size parameter of the transistor (for example, the width and length of the channel of the transistor) );

ID0PG is the current (d r a i n c u ιτ 6 π t) of the aforementioned power gate element (pG) under the condition of vgs = VDS = VDD;

Vth疋% b body voltage of the day body (thresh〇|d v〇itage); VV is the transient voltage of the virtual voltage source (vddv) as a function of time; and VDS0 is the aforementioned preset threshold voltage value. The correlation of the aforementioned parameters relating to the size of the transistor can be obtained from point A in the third figure. The point a of the voltage point (VL) corresponding to the virtual voltage source (VDDV) represents the time at which the current through the power gate element (pG) is switched to the maximum of 201035738 ... 5 hp reverser; wherein the voltage is the lowest Point) the non-invariant constant value of the transistor, the number of the crystals of the power gate element (pG), the circuit module of the power gate element (PG) connected in series (for example, the inverter of this example), circuit operation Conditions, etc. vary. At point A, the power gate element (PG) is passed through the p-type MOS transistor (the current of ρυ (drain (10) is the same as the 'e' and the 金-type MOS transistor (ρι), the power gate The component (PG) operates in the saturation region (saturatj〇n regj〇n) and the linear region. Therefore, the current equal to point A can be expressed as 〇(2):

f ID0C V VL-Vth, VDD-Vth,

(1 + XVL) = 1D0PG

VDD-VL FDO VDD-Vth~~VD〇I VDD-Vth-VL u -(2) where: When VDO is VGS = VDD, the drain saturation voltage of the P-type transistor used in this embodiment (drain saturation voltage) Ο α is the velocity saturation index; λ is the channel length modulation parameter; further, the 丨DOC of equation (1) is replaced by the formula (2), ) can be rewritten as the following formula (3):

-VDD-Vth + -VL (F£>£) - VV){-VDD - Vth + \VV o 9 . ? 2 ( i 1 — f 1 ) VDO l 2 J VDSO VV - Vih --VS 0 l 2 J

^VDD-VthX VDD-VL 1 + IVL 13 .. (3) 201035738 It can be seen from the above formula (3) that parameters such as 丨D0C and 丨D0PG depend on the size parameter of the transistor (in the above). Simplified on the basis of elimination, representing the aforementioned delay time evaluation mechanism and the inter-power component (pG) or circuit

Regardless of the size parameters of several pieces, the aforementioned delay time evaluation mechanism is only related to W and VL, that is, related to the dynamic response behavior of the virtual voltage source (VDDV), and thus the judgment mechanism referred to in the present invention has tolerable environmental variation. Performance. If the power component (PG) is an N-type transistor, the node between the N-type transistor and the ground (GND) is called a virtual ground point (V_al GND 'VGND)' and the aforementioned dummy voltage. The difference between the points (vddv) is that the virtual ground point (VGND) is first rising and then falling during the high-level level switching of the inverter (four) 'that is, in the virtual ground 〇: the highest voltage point (10) The above-mentioned formula derived from the p-type transistor can be directly used in the front row after replacing the characteristic of the N-type/p-type and the Ν-type/Ρ-type parameter of the adopted process. The concept; for example, compared to the above formula (3)', if the power gating element, the formula (3) can be changed to the following formula (3.1): ) is a Ν-type transistor, VDD-Vth ~ VDD-VH-Vth )

VH 1 + _ one) VDD~V, h~\vD〇\ VDS〇 VG VDD-Vth-[VG S 2 , f 1 , VDD - VG-m - ivDSQ V 2

J 14 201035738 where: VDD is the voltage supplied by the power supply; VG is the transient value of the virtual ground point (VGND) as a function of time;

Vth is the ε product threshold voltage of the multi-mode power gate network and the n-type electric solar field in the circuit module; VD0 is one of the N-type transistors when vgS=VDD (drain saturation voltage);

« is a speed saturation parameter (vei〇cjty saturation index); is also a N-type electric day channel length modulation parameter (channe丨丨ength modulation parameter); and VDS0 is a preset threshold voltage value. The month of the reference is shown in the fourth figure, which is the two sides of the graph solution (3) drawn by the parameters VL and VV in the third figure, respectively, as two independent polynomials, and vl and W are variables of two polynomials respectively. The left and right half of the equation (7) can be respectively formed into the circular label lines (〇_, f(VL)) and the rectangular label lines (f(VV)) of the fourth graph, where the VDs of the equation (3)设定This is set to 1〇〇mV. By using the parameter ^ as the self-variable, the minimum value of the parameter w can be taken from the fourth picture under the condition that the formula (3) is satisfied, and the value of VL is repeatedly changed to obtain a relatively complete parameter VL |

For the relational value group of VV, the relational value group of vl and VV can be expressed by the linear law (10). The equation is not equal (4): the lower is ^2 0.5685 +0.4568. (4) Alternatively, it can be used twice. The square fitted) obtains the following inequality (5): The curve of the rule of law (quadratic 15 201035738 ^>〇.〇9〇2 + 1.7137-FL-0.8109·^2 (5) Description (4) The unit of (5) is volt, and the unequal relationship between the description parameters and w is respectively depicted in the fifth figure. Following the similar derivation process of equations (4) and (5) above, when the power gate element ( PG) is an N-type transistor, and the inequality for the n-type transistor with respect to (4) and (5) is as follows: ^<-0.01729 + 0.4424· W ... (4.1) Ο Ο VG < 0.0045 + 0.1810-F// + 0.5810-F//2 (4 2) wherein the voltage units of the equations (4.1) and (4.2) are volts (v). The disclosed delay time evaluation mechanism may include: (i) start/reset; (Π) draw the virtual voltage source (VDDV) voltage lowest point vl. monitor the virtual voltage source (qing v) and the voltage lowest point ν (4) or (5) the value; and (iv) the completion Delay time evaluation. In summary, the voltage minimum point of the virtual voltage source (VDDV) can be found in the state switching process of the circuit (here, the inverter), and the voltage of the virtual voltage source (VDDV) passes. After the lowest voltage, it must continue to rise and meet the above formula (4) or (5) to determine the lightning. j疋.g also the switching state of the road has been completed: the green reference to the sixth figure 'when in the ideal power supply and _ heart Yuan multiplier (10) "When the Chuanxi PI is connected to a power component (pG), it can also be based on

The judgment mechanism described above obtains the delay time evaluation of the multiplication test M Zhu Xizhai (11), and after the research test results show that the delay of the delay evaluation machine 16 201035738 and the actual circuit are extracted by the invention Approximately #10% difference, therefore, it is necessary to add about 10% to 15% margin (margjn) in the final delay evaluation results. Using the foregoing delay evaluation mechanism, a circuit block diagram of an adaptive power control (APC) device of the present invention can be as shown in FIG. 7, the adaptive power control device includes a multi-mode power gate network. Multi-mode power gating netwo "k, 21", a voltage sensor (23), a variable threshold comparator (va "丨a - thresho丨d comparator, 24", a redundant interval Debt measurement circuit::;Detectlon, 25) and a bidirectional displacement register (B|__directi〇na|讣(1) Register 27), wherein the adaptive power control device of the present embodiment can be applied to various circuit modes. For example, the adaptive power control device of the present embodiment is connected to a complementary MOS circuit (CMOS circuit, 30 丨. The multi-mode power gate is connected to various logic circuits such as the multiplier and the inverter described above. The output and input ends of the network (21) are electrically connected to the circuit module (3〇) and the bidirectional displacement register (27), and the voltage sensor ^ (23) is connected to the multi-mode power gate network. Road (21) and the circuit module (3 〇) connecting one of the virtual voltage sources (VDDV), the output of the voltage sensor (23) is connected to the variable threshold comparator (24), and the variable threshold comparator (24), the redundant interval The detector (25), the bidirectional displacement sensor (27), and the multi-mode power gate network (21) are serially connected in series. Referring to the eighth figure, the multi-mode power gate network of the embodiment (21) comprising a plurality of P-type MOS transistors (PM〇s) connected in parallel with each other and connected in series between the ideal power supply (VDD) and the circuit module (3〇), wherein each p-type gold oxide The gate of the semi-transistor (PM〇S) is connected to the control signal (Ctrl4~0) stored by the bidirectional displacement sensor (27). According to the above description, it is known that 'join 17 201035738 between the force rate and the S piece (PG) The virtual voltage source of the four connected circuit modules generates a case where the % is depressed by 4, and therefore, the smaller the size/number of the added power gate elements (ρ〇), the larger the voltage drop is. The voltage drop can be regarded as the power noise (511 叩丨乂 丨%) input to the circuit module. The delay in the circuit module is reflected. Therefore, the multi-mode power closed network (21) can turn on the multi-mode power gate network (21) by selectively driving the control signal (Ctrl4~0). Type MOS semi-transistor (PMOS), step-in-effect or delay of the control circuit module. Further, each power gate element (PG) of the multi-mode power sluice network (21) may have different channel size parameters The power of the power supply to the f-channel module (10) through the multi-mode inter-power network (21) can be varied by switching the power gate elements (PG). Please refer to the ninth figure. The voltage sensor (23) of the embodiment includes two transistors (Μρι, MP2) connected in a diode-connected manner (wherein 'in the circuit The VL node connected to the transistor (MP2) during the working switching of the module can obtain the lowest voltage of the virtual voltage source (vddv). Please refer to the tenth figure, the variable gate root comparator of the embodiment (2 is a variant of the Schmitt trigger circuit (modified Schmiu Trjgg called the Schmidt trigger circuit by a clock pulse (pu|sed c丨〇ck) precharged. The variable threshold comparator (24) is connected to the VL node of the transistor (MP2) of the voltage sensor (23), which is a variable gate; (thresho丨d) Controlled by the VL node (for reverse control, such as 丨'-VL in the tenth figure). Therefore, the variable threshold comparator (24) can determine the instant of the virtual voltage source (VDDV) in the equation or the equation Voltage (VV) saturation 盥 "} /, ύ. 易言18 201035738, the variable threshold comparator (24) compares the vl node of the voltage sensor (23) (such as i_VL in the tenth figure) and Whether the instantaneous voltage of the virtual voltage source (W in the tenth figure) satisfies the formula (4) or (5), and when the output end of the variable gate pinch comparator (24) is switched to the low level, a Comparing the result state (assert丨·〇η 〇f the comparator) and outputting, it means that the circuit module has completed the switching work. When the power gate network 21) When the transistor used is N-type, the circuit of the voltage sensor (23) and the variable threshold comparator (24) needs to be adaptively modified, and the virtual ground point can be detected instead ( VGND) voltage variation characteristics; for example, the voltage sensor (23) must be modified to be connected to the virtual ground point (VGND), and the internal circuit must be modified to sense the virtual ground point (VG ND) The redundant interval detecting circuit (25) compares the comparison result state of the variable threshold comparator (24) with the clock edge of a circuit operation to determine whether there is a redundant interval in the clock period. (unused s|ack). This = residual interval refers to the time margin added in the clock cycle to prevent the circuit from being added due to the increase of the delay time due to the working ring, or because of the "input data" The length of the clock that is caused by the shortening of the calculation time. The eleventh figure of the monthly wheat test, the multi-mode power gate network (2彳) and the plurality of control signals of the two-way=private register (27) (Ctrl4~0) connection, where Tianfa sees too much When the remainder interval exists, the state of the bidirectional displacement register (27) is shifted to the right to turn off the power of the multimode power gate network (2彳) (ie, p-type MOS transistor (PM〇s) )); conversely, when there is not enough redundant interval temple (less than the time margin (1) (7) 丨叩 ma "g jn) required by the circuit module), the state of the bidirectional displacement register (27), '〇, toward Move left and turn on more of the power of the 19 201035738 mode power on the network (21). The bidirectional displacement register (27) may be provided with a reset signal, a sustain _d), a power off state (Ρ_“_ng state), etc., which are respectively used as the bidirectional The bits in the shift register (27) are reset to zero (open all power closures only to hold the state of each element inside the bidirectional displacement register (27), and to turn off all power gates. ο In the existing technology, the speed specification of the circuit module during operation (4)...specmcation usually needs to consider the process, voltage and degree (Process. Voltage, Temperature PVT)t, b^t, f, and must be in the clock. Many specifications are added to the specifications (bribe g (4) to ensure that the delay time of the circuit operation is not greater than the clock specification due to the change of the working environment, avoiding the chain error of other circuits and affecting the final operation result. However, the circuit mode During the use of the group, the aforementioned worst situation rarely occurs, so that a large amount of power input into the circuit module is spent on the margins. The aforementioned adaptive power control method and the skirt 2 can be judged. The circuit 槿 group gate η彳b especially time " 0, 疋 whether to exhaust all clock margins 〇 another 'in some large circuit modules, the non-critical path (non_ cmicai paths) delay time relative to There is also a clock margin in the clock specification. 'The same concept (determining whether there is a redundant interval in the circuit) can also be used in a non-critical path in the private branch group. In addition, this embodiment The adaptive power control method and device have a variety of changes, and the changes in the temperature of all process voltages are reflected in the delay of the circuit, π, and the implementation. For example, in the operation of the circuit module, the delay condition of the circuit can be taken, and at the same time, the remaining 20 201035738 margin in the circuit can be used to achieve the technical effect of saving power. The above is only the invention - preferably The scope of the present invention is not limited to the shapes, structures, features, and essences of the invention. The scope of the invention should be included in the scope of the patent application of the present invention. Schematic DESCRIPTION The first picture shows a picture shows a third picture shows the two brother a * intentions.

The current meter of the multiplier; see the schematic. Schematic diagram of the input and output voltage state of the inverter switching. The output voltage state of the Μ Μ Μ circuit is shown in the figure. The fourth figure is a graphical solution of the delay time evaluation mechanism with the virtual voltage 湄Α m .. ΑΛ ι泉 as the test object. Figure 5 is a schematic diagram showing the results of the straight/curve law of a delay time evaluation mechanism.

The sixth picture is a circuit diagram of the multiplier containing the power gate. The seventh figure is a block diagram of an adaptive power control device circuit. = Figure 8 is a circuit diagram of a multi-mode power gate network. The ninth figure is a circuit diagram of a voltage sensor. The tenth figure is a schematic diagram of a variable threshold comparator. The tenth-figure is a schematic diagram of a bidirectional displacement register. [Main component symbol description] (21) Multi-mode power gate network 21 201035738 (23) Voltage sensor (24) Variable threshold comparator (25) Redundant interval detection circuit (27) Bidirectional displacement register ( 30) Circuit module

Claims (1)

201035738 VII. Patent application scope: The second == adaptive power control device of the evaluation mechanism, 栌 relatively crying], the same way, the voltage sensor, a variable door, the seasonal state, the redundant interval Detective j π cough more than ten said Xuan, circuit and a two-way displacement temporary crying, mouth Hai Xisong power idle network contains "storage mouth, ^ nB two sub-connected crystals, apricots The power gate network is connected to - Tian 5 Xuan ^ 杈 々, and - circuit 槿 4 Ο The body is a P-type transistor and the multi-mode text ...,, '% between, each of the electro-glyph nodes is regarded as - virtual purchase, the connection of the Guangluo group - the grounding point and the gate of the circuit molded power The inter-network is connected to the multi-mode power gate network 盥兮φ 勹N i electric day and body and the grounding point, wherein: jπ is the point that a virtual ground power is connected to the virtual voltage source or The virtual product is grounded f: looking for: the virtual voltage source of the sea - the lowest voltage (VL) or looking for one of the virtual ground points (VH); the: the gate comparator and the output of the voltage sensor Electrically connecting the transient voltage (vv) of one of the ΔH virtual voltage sources to the minimum voltage () 满足 whether the first-specific relationship is satisfied and outputting the “first comparison result state” or the variable threshold comparator comparing the virtual The instantaneous voltage (VG) of the grounding point and the highest voltage (VH) satisfy a second specific relationship and output a second comparison result state; 4 the input of the interval detection circuit is connected to the variable threshold comparator, According to the first or second comparison of the variable gate comparator The state and the edge of the clock are detected - whether there is a redundant interval in the clock cycle; the input end of the bidirectional displacement register is electrically connected with the redundant interval detecting circuit, and the basis is Whether the interval exists or not, the displacement of the 23 201035738 bidirectional displacement register is changed in the turn-off state of the ^^ t system, and the multi-turn power gate network and the number connection are connected, and the transistors are respectively temporarily stored. The status of each control signal of the device is turned on or off: each of the "empty system ^ , U | makes the ^ Xi pull power gate network change according to the existence of the redundant S. 2. If the application The adaptive power control device with the circuit delay evaluation system described in the first part of the patent scope, and the formula of the age system··〃,宁六海弟—the specific relationship satisfies the following calendar: ten z (VDD~ Vv{l_-m+W VD〇\, VDD-Vth~~VD〇VL-Vth) l+AVL 7~~ --r->--_V2 2 , VDSO where VV — Vth—2V_ VDD is the power supply The voltage supplied; Vih is the multi-mode power gate network and one of the p-type transistors in the circuit module Voltage (threshold voltage); VD0 is a P-type transistor at vgs=VDD saturation voltage; one of the non-polar saturation electric α is a speed saturation parameter (ve|0Cjty ίΓ1(:^χ丨; into the p-type transistor channel length adjustment) The variable parameter (channe丨丨ength modulation parameter); and VDS0 is a predetermined threshold voltage value. 3. The adaptive power control device with a circuit delay evaluation mechanism according to claim 1, wherein the second The specific relationship satisfies the following formula: 24 201035738 VDD-Vih VDD-VH-Vih VH VDD-Vth-^VH VG 1 + k{VDD ~ VH) VDO VDD-Vth ——VDO VDSO VDD~Vt} tyG 2 Γ , VDD — VG-Vth 2 VDSQ 2 y where VDD is the voltage supplied by the power supply; Vth is the threshold voltage of the multimode power gate network and the N-type transistor in the circuit module (thresh0ld v〇|tage); VDO For the N-type transistor at VGS=VDD, the drain saturation voltage is used; α is a velocity saturation parameter (ve|0Cyty saturation index); λ is the N-type transistor channel length modulation parameter (channe)丨丨ength modulation parameter); and VDS0 is a preset Boundary voltage value 4. An adaptive power control device with a circuit delay as described in claim 1 or 2 or 3. The variable threshold comparator is a modified Schmitt trigger circuit. 5. An adaptive power control device with a circuit delay § evaluation mechanism as described in claim 1 or 2 or 3 'The voltage sensor comprises a diode connected in series by a diode connection 6. The adaptive power control device with the circuit delay evaluation mechanism described in claim 2, when the X/DS0 is 1 〇〇mV, the first specific relationship satisfies the following two formulas. One: )^> 0.5685 +0.4568.KL; and KKk〇.〇9〇2 + l.7137.FL-0.81〇9.Ki:2, the voltage unit is volt (V). 7 _ The adaptive power control device of the circuit delay evaluation machine 25 201035738, as described in claim 3, wherein the second specific relationship satisfies one of the following two formulas when the VDS0 is 10OmV: FGS-0.01729 +0.4424. K// ; and KGS0.0045 + 0.1810.K// + 0.5810.K//2, the voltage unit is volt (V). Eight, schema: (such as the next page) 26