CN104124951A - Circuit for driving high-side transistor - Google Patents
Circuit for driving high-side transistor Download PDFInfo
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- CN104124951A CN104124951A CN201410176171.XA CN201410176171A CN104124951A CN 104124951 A CN104124951 A CN 104124951A CN 201410176171 A CN201410176171 A CN 201410176171A CN 104124951 A CN104124951 A CN 104124951A
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Abstract
The embodiment of the invention provides a circuit for driving a transistor which includes a drive circuit, a first voltage boost circuit and a second voltage boost circuit. The drive circuit has a first specific node, a second specific node, and a third specific node coupled to a control node of the transistor. The drive circuit is arranged for coupling the first specific node to the third specific node according to at least a voltage of the first specific node and a voltage of the second specific node in order to charge the control node. The first voltage boost circuit is coupled between the first specific node and a connection node of the transistor, and is arranged for boosting the voltage of the first specific node. The second voltage boost circuit is coupled between the first specific node and the second specific node, and is arranged for boosting the voltage of the second specific node.
Description
Technical field
The present invention relates in general to a kind of drive circuit, relates in particular to the drive circuit that can produce over the stabilized driving voltage of supply power voltage.
Background technology
Two nodes of n channel metal-oxide-semiconductor field effect transistor switch (NMOSFET switch or nmos switch) (for example, source electrode and drain electrode) between there is relatively little voltage drop (voltage drop), in order to transmit large electric current between two nodes of n channel metal-oxide-semiconductor field effect transistor switch, charge pump (charge pump) technology can be used for improving the grid voltage of nmos switch, thereby reduces its conducting resistance (turn-on resistance).
In charge pumping technique, according to the alternating phase of clock signal, electric charge is poured into the grid of nmos switch.Rely on to prevent that electric charge from flowing to the diode of contrary direction or the equipment of similar diode (MOSFET being for example connected with diode, diode-connected MOSFET), can stored charge and in grid stored charge, thus raising grid voltage.Yet the use of diode is accompanied by the shortcoming of diode drop, diode drop can reduce the maximum voltage that the grid of nmos switch can be thus lifted to.This voltage drop is generally at supply power voltage that on 5V or lower sheet, to implement in (on-chip implement) be very important.
Bootstrap capacitor (bootstrap capacitor) technology can be more suitable for implementing on sheet.Bootstrap capacitor is used for improving the grid voltage of nmos switch.Because the electric charge on bootstrap capacitor is along with the time leaks, grid voltage may be reduced to the point that nmos switch turn-offs (turn off).So, be necessary to set up the new drive circuit that can produce high and stable driving voltage.
Summary of the invention
According to exemplary embodiment of the present invention, provide a kind of drive circuit that can produce over the stabilized driving voltage of supply power voltage, to address the above problem.
According to one embodiment of present invention, disclose a kind of exemplary circuit for driving transistors.This exemplary circuit comprises drive circuit, the first booster circuit and the second booster circuit.Described drive circuit has the first specific node, the second specific node and the 3rd specific node, wherein, described the 3rd specific node and transistorized control node couple, described drive circuit is at least according to the voltage of the voltage of the first specific node and the second specific node, described the first specific node is couple to described the 3rd specific node, to transistorized control node charging.The first booster circuit is coupled between the first specific node and transistorized connected node, and for promoting the voltage of the first specific node.Described the second booster circuit is coupled between described the first specific node and described the second specific node, and for promoting the voltage of the second specific node.
The circuit for driving transistors that the application proposes charges to transistorized control node by the first specific node is couple to the 3rd specific node, to high driving voltage is provided.
Accompanying drawing explanation
Fig. 1 is the block diagram of the exemplary circuit for driving transistors that exemplifies according to the invention process;
Fig. 2 illustrates for driving the schematic diagram of a kind of implementation of transistorized circuit illustrated in fig. 1;
Fig. 3 illustrates for the control signal of the running of circuit shown in control chart 2 and the sequential chart of enable signal;
Fig. 4 is illustrated in very first time point illustrated in fig. 3, the schematic diagram of circuit running illustrated in fig. 2;
Fig. 5 is illustrated in the second time point illustrated in fig. 3, the schematic diagram of circuit running illustrated in fig. 2;
Fig. 6 is illustrated in the 3rd time point illustrated in fig. 3, the schematic diagram of circuit running illustrated in fig. 2;
Fig. 7 is illustrated in the 4th time point illustrated in fig. 3, the schematic diagram of circuit running illustrated in fig. 2;
Fig. 8 illustrates for driving the schematic diagram of the another kind of implementation of transistorized circuit illustrated in fig. 1;
Fig. 9 illustrates for the control signal of the running of circuit shown in control chart 8 and the sequential chart of enable signal;
Figure 10 is according to the block diagram of the exemplary circuit for driving transistors shown in another embodiment of the present invention.
Embodiment
In the middle of specification and appending claims, used some vocabulary to censure specific assembly.Those skilled in the art should understand, and same assembly may be called with different nouns by manufacturer.This specification and appending claims are not used as distinguishing the mode of assembly with the difference of title, but the difference in function is used as the criterion of distinguishing with assembly.In the whole text, in the middle of specification and appending claims, be to be an open term mentioned " comprising ", therefore should be construed to " comprise but be not limited to ".In addition, " coupling " word comprises directly any and is indirectly electrically connected means at this.Therefore, if describe a first device in literary composition, be coupled to one second device, represent that this first device can directly be electrically connected in this second device, or be indirectly electrically connected to this second device through other devices or connection means.
In order large drive current to be provided and to reduce power loss to switching device (such as high-end NMOS), electric charge shared ideas and a plurality of booster circuit (such as, boostrap circuit) be used to by actuating switch device one predetermined time interval, to switching device, provide stable driving voltage (such as surpassing the voltage of supply power voltage).
Please refer to Fig. 1, Fig. 1 is the block diagram of the exemplary circuit for driving transistors that exemplifies according to the invention process.In this embodiment, to can be, but not limited to be nmos switch to transistor MN1.Transistor MN1 can comprise control node NC
n1and a plurality of connected node NA
n1and NB
n1.According to controlling node NC
n1on voltage VC, transistor MN1 is switched on (turn on) or turn-offs (turn off), and (is connected node NA according to input voltage
n1voltage VI), at connected node NB
n1produce output voltage (that is, voltage VO).As shown in Figure 1, the circuit 100 for driving transistors MN1 can comprise drive circuit 110, the first booster circuit 120, the second booster circuits 130 and switching device SW.Drive circuit 110 can have the first specific node N1, the second specific node N2 and the 3rd specific node N3, wherein, the control node NC of the 3rd specific node N3 and this transistor MN1
n1couple.The first booster circuit 120 is coupled in the connected node NA of the first specific node N1 and transistor MN1
n1between, and the second booster circuit 130 is coupled between the first specific node N1 and the second specific node N2.Switching device SW is optionally coupled between the 3rd specific node N3 and reference voltage VR.
In this embodiment, according to the on off state of switching device SW, whether circuit 100 can determine driving transistors MN1.By this embodiment but be not limited to this embodiment, reference voltage VR can be low-voltage (such as ground voltage).When switching device, SW is switched on, and the 3rd specific node N3 can be coupled to reference voltage VR, and controls node NC
n1and connected node NB
n1between voltage difference can be less than predetermined value.Transistor MN1 is turned off (turn off) accordingly.In other words, circuit 100 does not have driving transistors MN1.When switching device, SW is turned off, and according to the voltage V2 of the voltage V1 of the first specific node N1 and the second specific node N2, drive circuit 110 can be couple to the 3rd specific node N3 by the first specific node N1, makes the control node NC to transistor MN1
n1charging (improving voltage VC).In other words, circuit 100 is by driving transistors MN1, and wherein, the first booster circuit 120 and the second booster circuit 130 can be for adjustment/booster tension V1 and voltage V2 respectively.
For example, when voltage V1 is greater than voltage V2, drive circuit 110 is exercisable is couple to the 3rd specific node N3 by the first specific node N1.In one embodiment, when the first specific node N1 is coupled to the 3rd specific node N3, voltage V1 can be greater than reference voltage (for example supply power voltage), and voltage V2 is not more than reference voltage.So, between the first specific node N1 and the second specific node N2, there is large voltage difference, so allow drive circuit 110 to improve fast and effectively, control node NC
n1voltage VC, to surpass reference voltage.When voltage V1 is not more than voltage V2, drive circuit 110 is not couple to the first specific node N1 the 3rd specific node N3 and (that is, is stored in and controls node NC
n1on electric charge will can not flow to the first specific node N1 by drive circuit 110).In one embodiment, when the first specific node N1 is not couple to the 3rd specific node N3, voltage V2 is greater than reference voltage (for example supply power voltage).So, guaranteed that voltage V2 is greater than voltage V1, to avoid being stored in control node NC
n1electric charge from the 3rd specific node N3, flow to the first specific node N1 (that is, voltage VC is held stable).
In order conveniently to understand the present invention, provide illustrative embodiments below, for further describing the proposed circuit for driving transistors.Need to be appreciated that, it is feasible using other circuit execution modes of the structure shown in Fig. 1.Please refer to Fig. 2, Fig. 2 illustrates for driving the execution mode of the circuit 100 of Fig. 1 transistor MN1.As shown in Figure 2, circuit 200 can comprise the switching device SW shown in Fig. 1, drive circuit 210, the first booster circuit 220, the second booster circuits 230 and control circuits 240.Drive circuit 110, the first booster circuits 120 shown in Fig. 1 and the second booster circuit 130 can be implemented by drive circuit 210, the first booster circuits 220 and the second booster circuit 230 respectively.
Control circuit 240 and switching device SW, drive circuit 210, the first booster circuits 220 and the second booster circuit 230 couple, and the operation that carrys out control circuit 200 for generation of control signal SC and enable signal SEN.In this embodiment, when being turned off according to enable signal SEN switching device SW, circuit 200 can be according to control signal SC driving transistors MN1; When being switched on (turn on) according to enable signal SEN switching device SW, the 3rd specific node N3 can be coupled to reference voltage (for example, ground voltage VSS), and circuit 200 stops driving transistors MN1 accordingly.
Drive circuit 210 can comprise a plurality of transistor switch MP1 and MP2.Transistor switch MP1 can have the control node NC coupling with the second specific node N2
p1, connected node NA
p1and the connected node NB coupling with the first specific node N1
p1.Transistor switch MP2 can have the node of control NC
p2, with the control node NC of transistor MN1
n1the connected node NA coupling
p2, and with the connected node NA of transistor switch MP1
p1the connected node NB coupling
p2.According to enable signal SEN, the control node NC of transistor switch MP2
p2be coupled to connected node NA
n1voltage VI or reference voltage (for example, supply power voltage VDD).
The first booster circuit 220 can comprise capacitor C1, and wherein, control circuit 240 can control capacitor C1 be coupled in the connected node NA of the first specific node N1 and transistor MN1
n1between, or be coupled between reference voltage (being supply power voltage VDD) and another reference voltage (being ground voltage VSS) by the first specific node N1.
The second booster circuit 230 can comprise inverter I1, transistor switch MN2 and capacitor C2.Inverter I1 can have input node NP and output node NQ, and wherein inverter I1 is from input node NP reception control signal SC.Transistor switch MN2 can have the node of control NC
n2, connected node NA
n2and connected node NB
n2, wherein, control node NC
n2be coupled to the first specific node N1, and connected node NA
n2be coupled to the second specific node N2.Control circuit 240 can control connection node NB
n2be coupled to voltage VI or reference voltage (being supply power voltage VDD).For example, control circuit 240 can carry out control connection node NB with control signal SC
n2be coupled to voltage VI or supply power voltage VDD.One end of capacitor C2 is coupled to the second specific node N2, and the other end of capacitor C2 is coupled to output node NQ.
In practice, the first booster circuit 220 may further include a plurality of switching device S1-S3, and the second booster circuit 230 may further include a plurality of switching device S4 and S5, and drive circuit 210 may further include a plurality of switching device S6 and S7.When control is suitable, switching device S1-S7 can be used to realize transistor driver circuit, and this transistor driver circuit can produce high and stable driving voltage.Please refer to Fig. 3 and Fig. 4.Fig. 3 is for the control signal SC of control chart 2 circuit 200 runnings and the sequential chart of enable signal SEN, and Fig. 4 is illustrated in very first time point illustrated in fig. 3 T1 place, the schematic diagram of circuit 200 runnings shown in Fig. 2.At very first time point T1, enable signal SEN is in the first level L1 (such as high level), and switching device SW is turned off (turn off) (opening open).So circuit 200 can be according to control signal SC driving transistors MN1.When enable signal SEN is in the first level LI, switching device S7 is turned off (turn off) and switching device S6 is switched on (turn on) (closing (close)), allows to control node NC
p2be coupled to voltage VI.In addition,, when control signal SC for example, in second electrical level L2 (low level), according to control signal SC, switching device S1 and S4 are turned off, and according to control signal SC switching device S2, S3 and S5 are switched on.So the two ends of capacitor C1 are coupled to respectively supply power voltage VDD and ground voltage VSS (two ends that are capacitor C1 can be charged to respectively supply power voltage VDD and ground voltage VSS), and control node NC
n2and connected node NB
n2can be coupled to and control voltage VDD.The second specific node N2 (is the connected node NA of transistor switch MN2
n2) can be charged to approximately " supply power voltage VDD deducts the threshold voltage vt h of transistor switch MP1 " (being VDD-Vth).Inverter I1 can be output node NQ output voltage (approximating greatly supply power voltage VDD).In other words, the voltage drop at the two ends by capacitor C2 can approximate greatly threshold voltage vt h.
Please refer to Fig. 3 and Fig. 5, Fig. 5 is illustrated in the second time point T2 illustrated in fig. 3, the schematic diagram of circuit 200 runnings illustrated in fig. 2.At the second time point T2, control signal SC is in the first level L1, wherein, according to control signal SC, switching device S1 and S4 can be switched on (turn on), and according to control signal SC, switching device S2, S3 and S5 can be turned off (turn off).So the voltage of the first specific node N1 can be raised, and the second specific node N2 can be coupled to voltage VI by transistor switch MN2, and wherein, capacitor C1 can be used as the bootstrap capacitor in boostrap circuit.Capacitor C1 can with the control node NC of transistor MN1
n1share electric charge.After one or several clock cycle of control signal SC, control node NC
n1voltage VC can be thus lifted to that approximately " supply power voltage VDD adds connected node NA
n1voltage VI " (that is, VDD+VI).
After voltage VC is enhanced, is stored in and controls node NC
n1electric charge can leak by transistor switch MP2.Please refer to Fig. 3 and Fig. 6.It is upper that Fig. 6 is illustrated in the 3rd time point T3 shown in Fig. 3, the schematic diagram of circuit 200 runnings shown in Fig. 2.In the 3rd time T 3, the signal level of control signal SC is switched to second electrical level L2.The first specific node N1 is coupled to supply power voltage VDD by switching device S3 again, and connected node NB
n2again by switching device S5, be coupled to supply power voltage VDD.The voltage of the second specific node N2 can be enhanced (for example,, to VDD+VI).In other words, capacitor C2 can be counted as the bootstrap capacitor in boostrap circuit.As connected node NB
p1voltage be less than and control node NC
p1voltage and control node NC
n1voltage, transistor switch MP1 is not switched on (turn on) and large capacity source parasitic diode (bulk-source parasitic diode) (not shown in Figure 6) is reverse biased, guaranteed minimum/do not have electric charge to pass through transistor switch MP1 and/or transistor switch MP2 leaks.So transistor MN1 can rest on conducting state one predetermined time interval.
Please refer to Fig. 3 and Fig. 7.Fig. 7 is illustrated in the 4th time point T4 shown in Fig. 3, the schematic diagram of circuit 200 runnings illustrated in fig. 2.At the 4th time point T4, enable signal SEN is in second electrical level L2.So switching device SW and S7 are switched on (turn on), and switching device S6 is turned off (turn off).Control node NC as transistor switch MP2
p2by switching device S7, be coupled to supply power voltage VDD, not conducting of transistor switch MP2 (the first specific node N1 is not coupled to the 3rd specific node N3).In addition the control node NC of transistor MN1,
n1by switching device SW, be coupled to ground voltage VSS.Briefly, at the 4th time point T4 from the first specific node N1 (or supply power voltage VDD) to controlling node NC
n1there is no guiding path.
Although it should be noted that the booster circuit 120/130 in Fig. 1 can for example,, by boostrap circuit (, the booster circuit 220/230 shown in Fig. 2) realization, be also feasible with the booster circuit 120/130 that the circuit of other types is realized in Fig. 1.In one embodiment, the first booster circuit 220 that the first booster circuit 120 shown in Fig. 1 can go out is as shown in Figure 2 realized, and the second booster circuit 130 shown in Fig. 1 can for example, be realized by booster circuit rather than boostrap circuit (, the second booster circuit 230 illustrated in fig. 2).In another embodiment, the second booster circuit 130 shown in Fig. 1 can be realized by the second booster circuit 230 shown in Fig. 2, and the first booster circuit 120 shown in Fig. 1 can be realized by booster circuit rather than boostrap circuit (such as, the first booster circuit 220 shown in Fig. 2).In addition, the transistor being driven by circuit 100 (or the circuit 200 shown in Fig. 2) shown in Fig. 1 is not limited to nmos switch.Further, signal level illustrated in fig. 3 is only exemplary object.For example, the high level of control signal SC is different from the high level of enable signal SEN, and/or the low level of control signal SC is different from the low level of enable signal SEN.
According to non-superposing control signal switching device S1-S5, can operate, to improve performance and/or reliability.Please refer to Fig. 8, Fig. 8 is for driving the schematic diagram of another implementation of the circuit 100 of the transistor MN1 shown in Fig. 1.As shown in Figure 8, circuit 800 can comprise switching device SW illustrated in fig. 1, drive circuit 210, the first booster circuit 820, the second booster circuits 830 and the control circuits 840 shown in Fig. 2.The structure of circuit 800 is the structures based on circuit 200 illustrated in fig. 2, and wherein, Main Differences is that control circuit 840 can produce a plurality of control signal SC
1and SC
2.Each of the first booster circuit 820 and the second booster circuit 830 is according to the control signal SC producing
1and SC
2running.
Incorporated by reference to Fig. 8, come with reference to figure 9.Fig. 9 is the control signal SC for the running of circuit 800 shown in control chart 8
1and SC
2and the sequential chart of enable signal SEN.As shown in Figure 9, control signal SC
1and SC
2nonoverlapping.About the first booster circuit 820, as control signal SC
1at a particular level (such as high level), the connected node NB of transistor switch MN2
n2be coupled to the connected node NA of transistor MN1
n1voltage VI.In addition, as control signal SC
2in this particular level, the connected node NB of transistor switch MN2
n2be coupled to the first reference voltage (that is, supply power voltage VDD).In other words, switching device S4 controlled signal SC
1control, and switching device S5 controlled signal SC
2control.About the first booster circuit 820, as control signal SC
1for example, in particular level (high level), capacitor C1 is coupled in the connected node NA of the first specific node N1 and transistor MN1
n1between.Herein, as control signal SC
2for example, in particular level (high level), (one end of capacitor C1 is coupled to the first reference voltage by the first specific node N1, supply power voltage VDD), and the other end of capacitor C1 is coupled to second reference voltage different from the first reference voltage (that is, ground voltage VSS).In other words, switching device S1 controlled signal SC
1control, and switching device S2 and S3 controlled signal SC
2control.Those skilled in the art, after reading the paragraph that is assigned to Fig. 1 to Fig. 7, should easily understand the running (it operates according to sequential chart illustrated in fig. 9) of the circuit 800 shown in Fig. 8, and omissions of detail is described for simplicity herein.
Please refer again to Fig. 1 and Fig. 2.Based on above description, according to the voltage of the first specific node N1, the on off state of the voltage of the second specific node N2 and switching device SW (or enable signal SEN), drive circuit 110/210 can be couple to the 3rd specific node N3 by the first specific node N1.When switching device, SW is turned off, and the driving mechanism proposing can be realized by drive circuit 110, the first booster circuits 120 and the second booster circuit 130.So when proposed driving mechanism operates, switching device SW is optional.Please refer to Figure 10, Figure 10 is according to the block diagram of the exemplary circuit for driving transistors shown in another embodiment of the present invention.The structure of this circuit 1000 is the structures based on circuit 100 illustrated in fig. 1, and wherein Main Differences is that circuit 1000 does not comprise switching device SW illustrated in fig. 1.After reading the paragraph that is assigned to Fig. 1-Fig. 9, even if it should be appreciated by those skilled in the art that switching device SW is omitted, according to voltage V1 and V2, drive circuit 110 still can be couple to the 3rd specific node N3 by the first specific node N1.So circuit 1000 can be to controlling node NC
n1charging, to provide high and stable driving voltage for transistor MN1.For simplicity, the no longer description of duplication similarity herein.
The circuit for driving transistors that the application proposes can provide high driving voltage, to reduce described transistorized conducting resistance.This transistor can be in conducting state in predetermined time interval.In addition,, by using electric charge to share (charge-sharing) mechanism, the circuit for driving transistors that the application proposes can provide the driving voltage with slight ripple.
Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claims.
Claims (20)
1. for a circuit for driving transistors, it is characterized in that, comprising:
Drive circuit, there is the first specific node, the second specific node and the 3rd specific node, wherein, described the 3rd specific node and described transistorized control node couple, described drive circuit, at least according to the voltage of the voltage of described the first specific node and described the second specific node, is couple to described the 3rd specific node by described the first specific node, to described transistorized control node charging;
The first booster circuit, is coupled between described the first specific node and described transistorized connected node, and described the first booster circuit is for promoting the voltage of described the first specific node;
The second booster circuit, is coupled between described the first specific node and described the second specific node, and described the second booster circuit is for promoting the voltage of described the second specific node.
2. the circuit for driving transistors according to claim 1, is characterized in that, in described the first booster circuit and described the second booster circuit, at least one is boostrap circuit.
3. the circuit for driving transistors according to claim 1, is characterized in that, when the voltage of described the first specific node is greater than the voltage of described the second specific node, described drive circuit is couple to described the 3rd specific node by described the first specific node.
4. the circuit for driving transistors according to claim 3, it is characterized in that, when described the first specific node is coupled to described the 3rd specific node, the voltage of described the first specific node is greater than reference voltage, and the voltage of described the second specific node is not more than described reference voltage.
5. the circuit for driving transistors according to claim 1, it is characterized in that, when the voltage of described the first specific node is not more than the voltage of described the second specific node, described drive circuit is not couple to described the 3rd specific node by described the first specific node.
6. the circuit for driving transistors according to claim 5, is characterized in that, when described the first specific node does not couple with described the 3rd specific node, the voltage of described the second specific node is greater than reference voltage.
7. according to the circuit for driving transistors described in claim 4 or 6, it is characterized in that, described reference voltage is supply power voltage.
8. the circuit for driving transistors according to claim 1, is characterized in that, described the second booster circuit comprises:
Inverter, has input node and output node, and wherein, described inverter receives the first control signal from described the first input node;
Transistor switch, has control node, the first connected node and the second connected node, and wherein, the control node of described transistor switch and described the first specific node couple, and the first connected node of described transistor switch and described the second specific node couple; And
The second capacitor, one end of wherein said the second capacitor and described the second specific node couple, and the other end of described the second capacitor and described output node couple; And described circuit for driving transistors further comprises:
Control circuit, couple with described the second booster circuit, described control circuit is for generation of described the first control signal, and described the second connected node of controlling described transistor switch is coupled to voltage or first reference voltage of described transistorized connected node.
9. the circuit for driving transistors according to claim 8, it is characterized in that, when described the first control signal is in the first level, the second connected node of described transistor switch is coupled to the voltage of described transistorized connected node, and when described control signal is in the second electrical level different from described the first level, the second connected node of described transistor switch is coupled to described the first reference voltage.
10. according to the circuit for driving transistors described in claim 1,8 or 9, it is characterized in that, described the first booster circuit comprises the first capacitor; When described the first control signal is in the first level, described the first capacitor is coupled between described the first specific node and described transistorized connected node; And when described the first control signal is in second electrical level, one end of described the first capacitor is coupled to described the first reference voltage by described the first specific node, and the other end of described the first capacitor is coupled to second reference voltage different from described the first reference voltage.
11. circuit for driving transistors according to claim 8, is characterized in that, described control circuit further produces the second control signal, and described the second control signal and described the first control signal right and wrong are overlapping; And when described the first control signal is in particular level, the second connected node of described transistor switch is coupled to the voltage of described transistorized connected node, and when described the second control signal is in described particular level, the second connected node of described transistor switch is coupled to described the first reference voltage.
12. circuit for driving transistors according to claim 11, is characterized in that, described the first booster circuit comprises the first capacitor; When described the first control signal is in described particular level, described the first capacitor is coupled between described the first specific node and described transistorized connected node; And when described the second control signal is in described particular level, one end of described the first capacitor is coupled to described the first reference voltage by described the first specific node; And the other end of described the first capacitor is coupled to second reference voltage different from described the first reference voltage.
13. circuit for driving transistors according to claim 8, is characterized in that, described the first reference voltage is supply power voltage.
14. circuit for driving transistors according to claim 1, is characterized in that, described the first booster circuit comprises capacitor, and described circuit further comprises:
Control circuit, couple with described the first booster circuit, described control circuit is used for controlling described capacitor and is coupled between described the first specific node and described transistorized connected node or is coupled between the first reference voltage and the second reference voltage, and described the second reference voltage is different from described the first reference voltage.
15. circuit for driving transistors according to claim 14, is characterized in that, described control further produces the first control signal; When described the first control signal is in the first level, described capacitor is coupled between described the first specific node and described transistorized connected node; And when described the first control signal is in the second electrical level different from the first level, one end of described capacitor couples by described the first specific node and described the first reference voltage, and the other end of described capacitor and described the second reference voltage couple.
16. circuit for driving transistors according to claim 14, is characterized in that, described control further produces the first control signal and the second control signal; Described the first control signal and described the second control signal right and wrong are overlapping; When described the first control signal is in particular level, described capacitor is coupled between described the first specific node and described transistorized connected node; And when described the second control signal is in described particular level, one end of described capacitor is couple to described the first reference voltage by described the first specific node; And the other end of described capacitor and described the second reference voltage couple.
17. circuit for driving transistors according to claim 1, is characterized in that, further comprise:
Control circuit, couples with described drive circuit, and described control circuit arrives described drive circuit for generation of enable signal;
Wherein, described drive circuit is according to the voltage of described the first specific node, and the voltage of described the second specific node and described enable signal, be couple to described the 3rd specific node by described the first specific node.
18. circuit for driving transistors according to claim 17, it is characterized in that, when described enable signal is in the first level, described drive circuit, according to the voltage of the voltage of described the first specific node and described the second specific node, is couple to described the 3rd specific node by described the first specific node; When described enable signal is in being different from the second electrical level of the first level, described drive circuit is not couple to described the 3rd specific node by described the first specific node.
19. circuit for driving transistors according to claim 18, is characterized in that, also comprise:
Switching device, is controlled by described enable signal, and wherein, when described enable signal is in described second electrical level, described switching device couples described the 3rd specific node and reference voltage.
20. circuit for driving transistors according to claim 18, is characterized in that, described drive circuit comprises:
The first transistor switch, has the control node coupling with described the second specific node, the first connected node, and the second connected node coupling with described the first specific node; And transistor seconds switch, there is control node, the first connected node coupling with described transistorized control node, and the second connected node coupling with the first connected node of described the first transistor switch, wherein, when described enable signal is in described the first level, the control node of described transistor seconds switch is coupled to the voltage of described transistorized connected node, and when described enable signal is in described second electrical level, the control node of described transistor seconds switch is coupled to reference voltage.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201361816957P | 2013-04-29 | 2013-04-29 | |
| US61/816,957 | 2013-04-29 | ||
| US14/257,983 US9065437B2 (en) | 2013-04-29 | 2014-04-21 | Circuit for driving high-side transistor utilizing voltage boost circuits |
| US14/257,983 | 2014-04-21 |
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|---|---|
| CN104124951A true CN104124951A (en) | 2014-10-29 |
| CN104124951B CN104124951B (en) | 2017-05-17 |
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| CN201410176171.XA Active CN104124951B (en) | 2013-04-29 | 2014-04-29 | Circuit for driving high-side transistor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106130555A (en) * | 2016-07-06 | 2016-11-16 | 中国电子科技集团公司第二十四研究所 | The bootstrap voltage mode of bootstrapped switch produces circuit |
| CN107993618A (en) * | 2017-11-01 | 2018-05-04 | 昆山龙腾光电有限公司 | The level generation circuit of display device |
| CN108599750A (en) * | 2018-01-23 | 2018-09-28 | 电子科技大学 | A kind of single supply driving circuit of SiC-BJT |
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| TW201316685A (en) * | 2011-10-12 | 2013-04-16 | On Bright Electronics Shanghai | Systems and methods for driving transistors with high threshold voltages |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106130555A (en) * | 2016-07-06 | 2016-11-16 | 中国电子科技集团公司第二十四研究所 | The bootstrap voltage mode of bootstrapped switch produces circuit |
| CN107993618A (en) * | 2017-11-01 | 2018-05-04 | 昆山龙腾光电有限公司 | The level generation circuit of display device |
| CN107993618B (en) * | 2017-11-01 | 2020-09-29 | 昆山龙腾光电股份有限公司 | Level generating circuit of display device |
| CN108599750A (en) * | 2018-01-23 | 2018-09-28 | 电子科技大学 | A kind of single supply driving circuit of SiC-BJT |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124951B (en) | 2017-05-17 |
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