CN102098027B - Clock signal generating circuit - Google Patents
Clock signal generating circuit Download PDFInfo
- Publication number
- CN102098027B CN102098027B CN200910242514.7A CN200910242514A CN102098027B CN 102098027 B CN102098027 B CN 102098027B CN 200910242514 A CN200910242514 A CN 200910242514A CN 102098027 B CN102098027 B CN 102098027B
- Authority
- CN
- China
- Prior art keywords
- unit
- nmos pass
- pass transistor
- transistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000013078 crystal Substances 0.000 claims abstract description 75
- 238000007493 shaping process Methods 0.000 claims abstract description 56
- 230000010355 oscillation Effects 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims description 4
- 238000001914 filtration Methods 0.000 claims description 3
- 230000001737 promoting effect Effects 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 abstract description 4
- 230000001276 controlling effect Effects 0.000 abstract description 3
- IOJNPSPGHUEJAQ-UHFFFAOYSA-N n,n-dimethyl-4-(pyridin-2-yldiazenyl)aniline Chemical compound C1=CC(N(C)C)=CC=C1N=NC1=CC=CC=N1 IOJNPSPGHUEJAQ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000033228 biological regulation Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000002407 reforming Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
The invention provides a clock signal generating circuit which comprises a crystal oscillation unit and a clock shaping unit, wherein the crystal oscillation unit generates an initial clock signal, and the clock shaping unit is used for shaping the initial clock signal and then outputting a standard clock signal. The clock signal generating circuit also comprises a current bias unit connected with the crystal oscillation unit and the clock shaping unit, wherein the crystal oscillation unit and the clock shaping unit mirror the bias current of the current bias unit, and the mirror current is used as a working current, so that the currents of the crystal oscillation unit and the clock shaping unit can be controlled and regulated by controlling the current of the current bias unit.
Description
[technical field]
The invention relates to electronic circuit field, particularly about a kind of clock generating circuit improving power consumption.
[background technology]
At microelectronic, particularly in various electronic chip, often need to use the control signal of standard clock signal as other circuit that amplitude is the square-wave waveform of 0 and 1.For providing this standard clock signal, usually need to design clock signal generating circuit.As shown in Figure 1, the clock generation circuit of the CMOS chip that its display is at present conventional, it comprises the crystal oscillation unit that is made up of external crystal U3, load capacitance CL1, CL2 and crystal inside oscillator and clock shaping circuit forms.
An external crystal U3 and two load capacitance CL1, CL2 connect mutually, wherein interconnective one end ground connection of two electric capacity CL1, CL2.The two ends of external crystal U3 are respectively as two output PADA and PADB.Crystal inside pierce circuit comprises an a circuit R and inverting amplifier A1 in parallel with resistance R.Clock shaping circuit comprises an inverter A2.Two output PADA and PADB of external oscillation circuit are connected to the two ends of the inverting amplifier A1 of crystal inside pierce circuit.
Crystal oscillation unit produces original clock signal X, the clock signal of this original clock signal X square-wave waveform of outputting standard after the inverter A2 shaping of oversampling clock shaping circuit.
But existing this clock signal generating circuit, the original clock signal exported due to crystal oscillation unit directly carries out shaping via the inverter of clock shaping circuit, the electric current of crystal oscillation unit and clock shaping circuit is uncontrollable, the power dissipation ratio of whole clock signal generating circuit is comparatively large, also can increase the power consumption of chip for whole chip.
Therefore, for reducing the power consumption of clock signal generating circuit in existing CMOS chip, need to develop a kind of new clock signal generating circuit.
[summary of the invention]
The object of the present invention is to provide the clock signal generating circuit that a kind of power consumption is lower.
For reaching aforementioned object, a kind of clock generating circuit of the present invention, it comprises: crystal oscillation unit and clock shaping unit; Crystal oscillation unit produces original clock signal, clock shaping unit is to outputting standard clock signal after described original clock signal shaping, it also comprises the current offset unit being connected to crystal oscillation unit and clock shaping unit, the bias current of crystal oscillation unit and clock shaping unit mirror-current bias unit, and using this image current as operating current, then control the electric current that current offset cell current could control and regulate crystal oscillation unit and clock shaping unit.
Further, preceding clock shaping unit comprises: voltage shifts unit, low-pass filter unit, voltage comparison unit and inverter module; The original clock signal that crystal oscillation unit produces exports to voltage shifts unit, the magnitude of voltage of voltage shifts unit to original clock signal adjusts, and the clock signal after output adjustment is given to low-pass filter unit, low-pass filter unit leaches the DC component of the clock signal after adjustment, the DC component of the clock signal after voltage comparison unit is adjusted by comparison of aforementioned and this clock signal exports square-like clock signal, inverter module, to the further shaping of aforementioned square-wave signal, forms rise and fall along precipitous standard block clock signal; The wherein bias current of voltage shifts unit, voltage comparison unit and inverter module mirror-current bias unit, and using this image current as operating current.
Further, described clock generating circuit also comprises the clock driver cell of the inverter module output being connected to clock shaping unit, this clock driver cell comprises the inverter of some mutual series connection, the clock signal that aforementioned inverter module exports is driven, to improve the magnitude of voltage of clock signal.
Further, aforementioned currents bias unit comprises PMOS transistor and nmos pass transistor, and the node being connected to PMOS transistor grid in current offset unit, as the first output, is connected to the node of nmos pass transistor grid as the second output.
Further, aforementioned crystal oscillator unit comprises the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the first PMOS transistor, the second PMOS transistor, the grounded drain of the first nmos pass transistor, grid is connected to the first output of oscillator signal generating unit, source electrode is connected to the output node of crystal oscillator unit, second nmos pass transistor, the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor is all connected to voltage signal VDD, the drain electrode of the second nmos pass transistor is connected to the source electrode of the 3rd nmos pass transistor, the drain electrode of the 3rd nmos pass transistor is connected to the source electrode of the 4th nmos pass transistor, the source electrode of the second nmos pass transistor is connected to the first output of oscillator signal generating unit, the drain electrode of the 4th nmos pass transistor is connected to aforementioned output node, the grid of the first PMOS transistor is connected to the first output of oscillator signal generating unit, source electrode is connected to the output node of crystal oscillator, drain electrode and substrate are connected to the source electrode of the second PMOS transistor, second PMOS transistor grid is connected to the first output of current offset unit, and drain electrode is connected to voltage signal VDD.
Further, aforesaid voltage translation unit comprises the 3rd PMOS transistor and the 4th PMOS transistor, the grid of the 3rd PMOS transistor is connected to the output of aforementioned crystal oscillator unit, source ground, drain electrode is connected to the output node of voltage shifts unit, the grid of the 4th PMOS transistor is connected to the first output of current offset unit, and drain electrode is connected to voltage signal VDD, and source electrode is connected to the output of voltage shifts circuit.
Further, aforementioned low-pass filter unit comprises the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th nmos pass transistor and the 8th nmos pass transistor; The grounded-grid of the 5th nmos pass transistor, the 6th nmos pass transistor and the 7th nmos pass transistor, the drain electrode of the 5th nmos pass transistor is connected to the source electrode of the 6th nmos pass transistor, the drain electrode of the 6th nmos pass transistor is connected to the source electrode of the 7th nmos pass transistor, the drain electrode of the 5th nmos pass transistor is connected to the output of aforesaid voltage translation unit, and the drain electrode of the 7th nmos pass transistor is connected to the output node of low-pass filter unit; The grid of the 8th nmos pass transistor is connected to output node, source electrode and the grounded drain of this low-pass filter unit.
Further, aforesaid voltage comparing unit comprises the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the 5th PMOS transistor and the 6th PMOS transistor; The grid of the 9th nmos pass transistor is connected to the second output of aforementioned currents bias unit, source ground, and drain electrode is connected to the first node E of voltage comparison unit; The grid of the tenth nmos pass transistor is connected to the output of low-pass filter unit, drain electrode is connected to the first node E of voltage comparison unit, source electrode is connected to the source electrode of the 5th PMOS transistor, the grid of the 11 nmos pass transistor is connected to the output of aforesaid voltage translation unit, drain electrode is connected to the first node E of voltage comparison unit, source electrode is connected to the source electrode of the 6th PMOS transistor, and the 5th PMOS transistor is connected with the grid of the 6th PMOS transistor, and drain electrode is connected to voltage signal VDD.
Further, aforementioned inverter module comprises the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 7th PMOS transistor and the 8th PMOS transistor, the grid of the tenth bi-NMOS transistor is connected to the second output of aforementioned currents bias unit, source ground, drain electrode is connected to the drain electrode of the 13 nmos pass transistor, the grid of the 13 nmos pass transistor is connected to the output of voltage comparison unit, and source electrode is connected to the output node of inverter module; The grid of the 7th PMOS transistor is connected to the first output of aforementioned currents bias unit, drain electrode is connected to voltage signal VDD, source electrode is connected to the drain electrode of the 8th PMOS transistor, the grid of the 8th PMOS transistor is connected to the output of voltage comparison unit, and source electrode is connected to the output node of inverter module.
Further, described clock generating circuit also comprises the frequency unit being connected to clock driver cell output, and this frequency unit carries out frequency division to form the identical square-like clock signal of duty ratio to the clock signal that clock driver cell exports.
Compared with prior art, clock generating circuit of the present invention, the reference current of crystal oscillator unit and clock shaping unit mirror-current bias unit is as operating current, then regulate the reference current of current offset unit, the i.e. electric current of each unit of adjustable whole clock generating circuit, so can reduce the power consumption of whole circuit.
About other objects of the present invention, feature and advantage, describe in detail in a specific embodiment below in conjunction with accompanying drawing.
[accompanying drawing explanation]
Ensuing embodiment, following claim and accompanying drawing will contribute to understanding specific features of the present invention, each embodiment and advantage, wherein:
Fig. 1 is the structural representation of the clock signal generating circuit of prior art.
Fig. 2 is the structured flowchart of clock signal generating circuit of the present invention.
Fig. 3 is the circuit structure diagram of the current offset unit of clock signal generating circuit of the present invention.
Fig. 4 is the crystal oscillator unit of clock signal generating circuit of the present invention and the circuit structure diagram of clock shaping unit.
[embodiment]
Refer to shown in Fig. 2, the structured flowchart of its display clock signal generating circuit of the present invention.In the present invention, clock signal generating circuit comprises crystal oscillation unit U0, current offset unit U2 and clock shaping unit U10.
Crystal oscillation unit produces an original clock signal X, then this original clock signal X input clock shaping unit U10 is carried out shaping, and the standard clock signal of the square-wave waveform of final outputting standard.In whole clock signal generation and reforming process, current offset unit U2 produces reference current (or being referred to as bias current), the reference current of crystal oscillation unit and clock shaping unit mirror-current bias unit, and the operating current using this image current as each unit, then control and regulate the reference circuit of current offset unit, can control and regulate the electric current of whole circuit, so the power consumption of whole circuit can be reduced.
As shown in Figure 2, clock shaping unit U10 comprises again interconnective voltage shifts unit U3, low-pass filter unit U4, voltage comparison unit U5, inverter module U6 and clock driver cell U7.Brief description is done below in conjunction with each unit of Fig. 2 to the clock shaping unit of clock generating circuit.
The original clock signal X produced by crystal oscillation unit U0 generally includes DC component and alternating current component, its magnitude of voltage is V=Vdc+Vac, when carrying out shaping to original clock signal X, electric current due to crystal oscillation unit is subject to the control of the reference current of current biasing circuit, for controlling power consumption, the magnitude of voltage of this original clock signal X that crystal oscillation unit exports is smaller, when follow-up shaping, signal is too weak is not easy to shaping and starts other unit, therefore first clock shaping unit U10 comprises a voltage shifts unit U3, first adjusted by the DC component of voltage shifts unit U3 to this original clock signal during this original clock signal X input clock shaping unit U10, preferably can promote the DC component of original clock signal, such as original magnitude of voltage may be V=Vdc+Vac=1v+Vac, after voltage shifts unit U3 promotes, the magnitude of voltage that voltage shifts unit U3 exports can become V=Vdc+Vac=3v+Vac, the AC wave shape being equivalent to whole signal is shifted 2V relative on X direction.Be convenient to so follow-uply carry out shaping to this clock signal and the voltage signal after utilizing this translation starts other shaping units.The wherein reference current of voltage shifts unit mirror-current bias unit, and using this image current as operating current, then control and regulate the reference circuit of current offset unit, the electric current with regulation voltage translation unit can be controlled.
Voltage shifts unit U3 carries out exporting the clock signal Y (also can be referred to as translation clock signal) after adjustment after voltage promotes to original clock signal X, a wherein input of a road clock signal Y direct input voltage comparing unit U5, another road clock signal Y inputs low-pass filter unit U4.Because this clock signal Y comprises the simple alternating current component Vac of DC component Vdc and alternation, after low-pass filter unit U4, alternating current component is filtered, and output DC component Vdc is called the DC component y of the clock signal Y after adjustment.
Through another input of the DC component y input voltage comparing unit U5 of the filtered clock signal Y of low-pass filter unit U4, voltage compare is carried out with the clock signal Y of aforementioned direct input, when clock signal Y is greater than the DC component y of clock signal Y, then voltage comparator exports high level VDD, when alternate clock signal Y is less than the DC component y of clock signal Y, then voltage comparator output low level 0v, like this after voltage comparison unit U5 shaping, the clock signal that voltage comparison unit exports is the square-wave signal Z that magnitude of voltage is 0v and VDD.The wherein reference current of voltage comparison unit mirror-current bias unit, and using this image current as operating current, then control and regulate the reference circuit of current offset unit, the electric current with regulation voltage comparing unit can be controlled.
The square-wave signal Z that voltage comparison unit U5 exports, possible waveform effect is not the square wave of special standard, the rising (decline) of such as waveform is along precipitous not, (decline) time of rising is longer, and the square-wave signal Z that therefore voltage comparison unit U5 exports needs through a further shaping of inverter module U6.Square-wave signal Z is through inverter module U6, if the signal of input is VDD, the signal that then inverter module U6 exports is 0, if the signal of input is 0, the signal that then inverter module U6 exports is VDD, after inverter module U6 shaping, namely clock signal Z becomes the square-wave signal of rising (decline) along precipitous waveform standard.The wherein reference current of inverter module mirror-current bias unit, and using this image current as operating current, then control and regulate the reference circuit of current offset unit, can control and regulate the electric current of inverter module.
Electric current due to multiple unit of preceding clock shaping unit is all controlled by the reference current of aforementioned currents bias unit, for controlling the power consumption of whole circuit, the operating current of aforementioned each unit may be all less, for exporting the clock signal that can be used as drive singal, clock driver cell U7 can be increased after aforementioned inverter module U6, the standard block signal that inverter module U6 exports is driven.
In the clock signal after preceding clock drive unit drives, the duty ratio of possible high level VDD and low level 0v may not be respectively account for 50%, the square-wave signal such as exported is in one-period, high level accounts for 40%, and low level accounts for 60%, can by increasing frequency unit (not shown) to the further shaping of preceding clock signal.After clock signal carries out frequency division shaping, then can export the standard frequency clock signal that VDD and 0v respectively accounts for 50%.
Elaborate below in conjunction with the particular circuit configurations of accompanying drawing to each unit.
Refer to shown in Fig. 3, the circuit structure diagram of the current offset unit adopted in its display one embodiment of the present of invention.
As shown in Figure 3, this current offset unit comprises the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3, the 4th nmos pass transistor N4 and the 5th nmos pass transistor N5, the first PMOS transistor P1, the second PMOS transistor P2, the 3rd PMOS transistor P3, the 4th PMOS transistor P4, the 5th PMOS transistor P5, the 6th PMOS transistor P6 and the 7th PMOS transistor P7.
The grid of the first nmos pass transistor N1 is connected to the first end of a resistance R, and source electrode is connected to voltage signal VSS (i.e. low level signal can be ground connection), and drain electrode is connected to first node A.The grid of the first PMOS transistor P1 is connected to the 3rd node C, and source electrode is connected to voltage signal VDD, and drain electrode is connected to the source electrode of the 3rd PMOS transistor P3, and the drain electrode of the 3rd PMOS transistor P3 is connected to first node A, and grid is connected to Section Point B.
The grid of the second PMOS transistor P2 is connected to the 3rd node C, and drain electrode is connected to the source electrode of the 4th PMOS transistor, and source electrode is connected to voltage signal VDD.The grid of the 4th PMOS transistor P4 is connected to aforementioned Section Point B, and drain electrode is connected to aforementioned 3rd node C.A resistance Rb1 is also connected with between Section Point B and the drain electrode of the 4th PMOS transistor P4.The grid of the second nmos pass transistor N2 is connected to said first node A, and source electrode is connected to the first end of a resistance R, and drain electrode is connected to Section Point B.Second end of resistance R is connected to voltage signal VSS.Because the second PMOS P2 and the first PMOS P1 forms mirror image circuit, then the electric current of the Mirroring of tributary second PMOS P2 place branch road at the first PMOS P1 place.And the electric current of the second PMOS P2 place branch road is as reference current, can calculates and be about Vth/R, wherein Vth is the threshold voltage of the first nmos pass transistor N1.
The grid of the 3rd nmos pass transistor N3 is connected to the 4th node D, and source electrode is connected to voltage signal VSS, and drain electrode is connected to the source electrode of the 4th nmos pass transistor N4.The grid of the 4th nmos pass transistor N4 is connected to the source electrode of the 6th PMOS transistor P6, and drain electrode is connected to aforementioned 4th node D.A resistance Rb2 is connected with between the drain electrode and the drain electrode of the 6th PMOS transistor P6 of the 4th nmos pass transistor N4.The grid of the 6th PMOS transistor P6 is connected to aforementioned Section Point B, and source electrode is connected to the drain electrode of the 5th PMOS transistor P5.The grid of the 5th PMOS transistor P5 is connected to aforementioned 3rd node C, and source electrode is connected to voltage signal VDD.Because the 5th PMOS P5 and the second PMOS P2 forms mirror image circuit, then the electric current of the Mirroring of tributary second PMOS P2 place branch road at the 5th PMOS P5 place.
The 3rd node C connected by first PMOS P1 grid draws the first output VBP as current offset unit.The 4th node D connected by 3rd NMOS tube N3 grid is as the second output VBN of current offset unit.
The grid of the 7th PMOS P7 is connected to the first output VBP, and source electrode and drain electrode are connected to voltage signal VDD.The grid of the 5th NMOS tube N5 is connected to the second output VBN, and source electrode and drain electrode are connected to voltage signal V.
Refer to Fig. 4 and shown in composition graphs 1, the circuit structure diagram in one embodiment of each unit of its display crystal oscillation unit U1 of the present invention and clock shaping unit U10.
Crystal oscillation unit U0 of the present invention can comprise external crystal circuit and crystal inside oscillator unit U1, wherein external crystal circuit can be identical with the external oscillation circuit structure shown in Fig. 1, as shown in Figure 1, it is mutually connected by crystal U3 and load capacitance CL1, CL2 to be formed equally, wherein interconnective one end ground connection of two load capacitance CL1, CL2.The two ends of crystal U3 are as the first output PADA and the second output PADB.
As shown in Figure 4, crystal inside oscillator unit U1 comprises the first nmos pass transistor NM1, the second nmos pass transistor NM2, the 3rd nmos pass transistor NM3, the 4th nmos pass transistor NM4, and the first PMOS transistor PM1, the second PMOS transistor PM2.The source ground of the first nmos pass transistor NM1, grid is connected to the first output PADA of oscillator signal generating unit, and drain electrode is connected to the output node X of crystal oscillator unit.The grid of the second nmos pass transistor NM2, the 3rd nmos pass transistor NM3 and the 4th nmos pass transistor NM4 is all connected to voltage signal VDD, the source electrode of the second nmos pass transistor NM2 is connected to the drain electrode of the 3rd nmos pass transistor NM3, the source electrode of the 3rd nmos pass transistor NM3 is connected to the drain electrode of the 4th nmos pass transistor NM4, the drain electrode of the second nmos pass transistor is connected to the first output PADA of the crystal of external crystal-controlled oscillation, and the source electrode of the 4th nmos pass transistor NM4 is connected to aforementioned output node.The grid of the first PMOS transistor PM1 is connected to the first output PADA of oscillator signal generating unit, source electrode and substrate are connected to the drain electrode of the second PMOS transistor PM2, drain electrode is connected to the output node X of crystal oscillator, the grid of the second PMOS transistor PM2 is connected to the first current output terminal VBP of current offset unit, and source electrode is connected to voltage signal VDD.
Grid due to the second PMOS transistor PM2 of crystal inside oscillator unit U1 and the second PMOS transistor P2 of current offset unit U2 is all connected to the first output VBP of current offset unit, and the source electrode of the second PMOS transistor PM2 of crystal oscillator unit U1 and the second PMOS transistor P2 of current offset unit is all connected to voltage VDD, therefore the second PMOS transistor PM2 of crystal inside oscillator unit U1 and the second PMOS transistor P2 of current offset unit forms mirror image circuit, the reference current of crystal inside oscillator unit U1 mirror-current bias unit U2, when chip structure is fixed, then can by the mirror image operating current regulating the reference current of current offset unit to regulate crystal oscillator unit.
As shown in Figure 4, aforesaid voltage translation unit U3 comprises the 3rd PMOS transistor PM3 and the 4th PMOS transistor PM4, the grid of the 3rd PMOS transistor PM3 is connected to the output of aforementioned crystal oscillator unit, grounded drain, and source electrode is connected to the output node of voltage shifts unit.The grid of the 4th PMOS transistor PM4 is connected to the first output VBP of current offset unit, and source electrode is connected to voltage signal VDD, and drain electrode is connected to the output of voltage shifts circuit.
Grid due to the 4th PMOS transistor PM4 of voltage shifts unit U3 and the second PMOS transistor P2 of current offset unit U2 is all connected to the first output VBP of current offset unit, and the source electrode of the 4th PMOS transistor PM4 of voltage shifts unit U3 and the second PMOS transistor P2 of current offset unit is all connected to voltage VDD, therefore the 4th PMOS transistor PM4 of voltage shifts unit U3 and the second PMOS transistor P2 of current offset unit forms mirror image circuit, the electric current of voltage shifts unit U3 mirror-current bias unit U2, when chip structure is fixed, then can by regulating the mirror image operating current of the reference current regulation voltage translation unit U3 of current offset unit.
As shown in Figure 4, aforementioned low-pass filter unit U4 comprises the 5th nmos pass transistor NM5, the 6th nmos pass transistor NM6, the 7th nmos pass transistor NM7 and the 8th nmos pass transistor NM8.The grounded-grid of the 5th nmos pass transistor NM5, the 6th nmos pass transistor NM6 and the 7th nmos pass transistor NM7, the source electrode of the 5th nmos pass transistor NM5 is connected to the drain electrode of the 6th nmos pass transistor NM6, the source electrode of the 6th nmos pass transistor NM6 is connected to the drain electrode of the 7th nmos pass transistor NM7, the drain electrode of the 5th nmos pass transistor NM5 is connected to the output of aforesaid voltage translation unit, and the source electrode of the 7th nmos pass transistor NM7 is connected to the output node of low-pass filter unit.The grid of the 8th nmos pass transistor NM8 is connected to output node, source electrode and the grounded drain of this low-pass filter unit.
As shown in Figure 4, aforesaid voltage comparing unit U5 comprises the 9th nmos pass transistor NM9, the tenth nmos pass transistor NM10, the 11 nmos pass transistor NM11, the 5th PMOS transistor PM5 and the 6th PMOS transistor PM6; The grid of the 9th nmos pass transistor NM9 is connected to the second output VBN of aforementioned currents bias unit, source ground, and drain electrode is connected to the first node E of voltage comparison unit.The grid of the tenth nmos pass transistor NM10 is connected to the output of low-pass filter unit, and source electrode is connected to the circuit node E of voltage comparison unit, and drain electrode is connected to the drain electrode of the 5th PMOS transistor PM5.The grid of the 11 nmos pass transistor NM11 is connected to the output of aforesaid voltage translation unit, and source electrode is connected to the circuit node E of voltage comparison unit, and drain electrode is connected to the drain electrode of the 6th PMOS transistor PM6.5th PMOS transistor PM5 is connected with the grid of the 6th PMOS transistor PM6, and source electrode is all connected to voltage signal VDD.
Grid due to the 9th nmos pass transistor NM9 of comparator unit U5 and the 3rd nmos pass transistor N3 of current offset unit is all connected to the second output VBN of current offset unit, and the source grounding of the 9th nmos pass transistor NM9 of comparator unit U5 and the 3rd nmos pass transistor N3 of current offset unit, therefore the 9th nmos pass transistor NM9 of comparator unit U5 and the 3rd nmos pass transistor N3 of current offset unit forms mirror image circuit, the electric current of comparator unit U5 mirror-current bias unit U2, when chip structure is fixed, then can by the mirror image operating current regulating the reference current of current offset unit to regulate comparator unit U5.
As shown in Figure 4, aforementioned inverter module U6 comprises the tenth bi-NMOS transistor NM12, the 13 nmos pass transistor NM13, the 7th PMOS transistor PM7 and the 8th PMOS transistor PM8.The grid of the tenth bi-NMOS transistor NM12 is connected to the second output VBN of aforementioned currents bias unit, source ground, and drain electrode is connected to the source electrode of the 13 nmos pass transistor NM13.The grid of the 13 nmos pass transistor NM13 is connected to the output of voltage comparison unit, and drain electrode is connected to the output node of inverter module.The grid of the 7th PMOS transistor PM7 is connected to the first output VBP of aforementioned currents bias unit, source electrode is connected to voltage signal VDD, drain electrode is connected to the source electrode of the 8th PMOS transistor PM8, the grid of the 8th PMOS transistor PM8 is connected to the output of voltage comparison unit, and drain electrode is connected to the output node of inverter module.
Grid due to the tenth bi-NMOS transistor NM12 of inverter module U6 and the 3rd nmos pass transistor N3 of current offset unit is all connected to the second output VBN of current offset unit, and the source grounding of the tenth bi-NMOS transistor NM12 of inverter module U6 and the 3rd nmos pass transistor N3 of current offset unit, therefore the tenth bi-NMOS transistor NM12 of inverter module U6 and the 3rd nmos pass transistor N3 of current offset unit forms mirror image circuit, inverter module U6 is by being connected to the electric current of the tenth bi-NMOS transistor NM12 mirror-current bias unit U2 of the second output VBN of current offset unit.Equally, 7th PMOS transistor PM7 of inverter module and the first PMOS transistor P1 of current offset unit forms mirror image circuit, and inverter module U6 is by being connected to the electric current of the 7th PMOS transistor PM7 mirror-current bias unit U2 of the first output VBP of current offset unit.The concrete structure of the transistor of such adjustment inverter module U6 realizes the control to inverter module U6 electric current.
As shown in Figure 4, preceding clock driver element U7 comprises three inverters (non-label) of mutually connecting, and the clock signal exported inverter module is driven the magnitude of voltage improving signal by it.
Clock signal generating circuit of the present invention, wherein oscillator signal generating unit U0 produces resonance signal under external force, input to crystal oscillator unit U1, after crystal oscillator unit U1 receives the resonance signal of oscillator signal generating unit U0 input, shaping is carried out to this resonance signal and exports an original clock signal X, then this original clock signal X input clock shaping unit U10 is carried out shaping, first promote through the magnitude of voltage of voltage shifts unit U3 to clock signal, then through low-pass filter unit U4, the DC component signal of low-pass filtering clocking is carried out to clock signal, through comparing unit U5, the DC component of clock signal and clock signal is compared again, obtain square-like clock signal, then by inverter module U6 shaping, the precipitous standard block signal of waveform is become to square-like clock signal, and the lifting of signal voltage value can be carried out through clock driver cell U7 to standard block clock signal again, and by frequency unit, frequency division is carried out to clock signal, and final output high level VDD and low level 0v duty ratio are respectively the standard clock signal of 50%.In whole clock signal generation and reforming process, the reference current of several unit mirror-current bias unit of crystal oscillator unit and clock shaping unit, then regulate the reference current of current offset unit can control and regulate the electric current of whole clock generating circuit, so the power consumption of whole circuit can be reduced.
Above-mentioned explanation fully discloses the specific embodiment of the present invention.It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (9)
1. a clock generating circuit, it comprises: crystal oscillation unit and clock shaping unit; Crystal oscillation unit produces original clock signal, clock shaping unit is to outputting standard clock signal after described original clock signal shaping, it is characterized in that: it also comprises the current offset unit being connected to crystal oscillation unit and clock shaping unit, the bias current of crystal oscillation unit and clock shaping unit difference mirror-current bias unit, and using image current as operating current
Wherein, aforementioned currents bias unit comprises PMOS transistor and nmos pass transistor, be connected to the node of PMOS transistor grid in current offset unit as the first output, be connected to the node of nmos pass transistor grid as the second output, and, aforementioned crystal oscillation unit comprises the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the first PMOS transistor, the second PMOS transistor, the grounded drain of the first nmos pass transistor, grid is connected to the first output of crystal oscillation unit, source electrode is connected to the output node of crystal oscillation unit, second nmos pass transistor, the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor is all connected to voltage signal VDD, the drain electrode of the second nmos pass transistor is connected to the source electrode of the 3rd nmos pass transistor, the drain electrode of the 3rd nmos pass transistor is connected to the source electrode of the 4th nmos pass transistor, the source electrode of the second nmos pass transistor is connected to the first output of crystal oscillation unit, the drain electrode of the 4th nmos pass transistor is connected to the output node of crystal oscillation unit, the grid of the first PMOS transistor is connected to the first output of crystal oscillation unit, source electrode is connected to the output node of crystal oscillation unit, drain electrode and substrate are connected to the source electrode of the second PMOS transistor, second PMOS transistor grid is connected to described first output of described current offset unit, and drain electrode is connected to voltage signal VDD.
2. clock generating circuit as claimed in claim 1, is characterized in that: preceding clock shaping unit comprises: voltage shifts unit, low-pass filter unit, voltage comparison unit and inverter module, the original clock signal that crystal oscillation unit produces exports to voltage shifts unit, voltage shifts unit carries out DC component adjustment to original clock signal, and the clock signal exported after adjustment is to low-pass filter unit, low-pass filter unit carries out low-pass filtering to obtain the DC component of the clock signal after described adjustment to the clock signal after described adjustment, the DC component of the clock signal after voltage comparison unit is adjusted by comparison of aforementioned and this clock signal exports square-like clock signal, inverter module carries out anti-phase to obtain standard block clock signal to aforementioned square-like clock signal, the wherein bias current of voltage shifts unit, voltage comparison unit and inverter module difference mirror-current bias unit, and using image current as operating current.
3. clock generating circuit as claimed in claim 2, it is characterized in that: it also comprises the clock driver cell of the inverter module output being connected to clock shaping unit, this clock driver cell comprises the inverter of some mutual series connection, drives the clock signal that aforementioned inverter module exports.
4. clock generating circuit as claimed in claim 1, it is characterized in that: aforesaid voltage translation unit comprises the 3rd PMOS transistor and the 4th PMOS transistor, the grid of the 3rd PMOS transistor is connected to the output of aforementioned crystal oscillation unit, source ground, drain electrode is connected to the output node of voltage shifts unit, the grid of the 4th PMOS transistor is connected to the first output of current offset unit, and drain electrode is connected to voltage signal VDD, and source electrode is connected to the output of voltage shifts circuit.
5. clock generating circuit as claimed in claim 4, is characterized in that: aforementioned low-pass filter unit comprises the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th nmos pass transistor and the 8th nmos pass transistor; The grounded-grid of the 5th nmos pass transistor, the 6th nmos pass transistor and the 7th nmos pass transistor, the drain electrode of the 5th nmos pass transistor is connected to the source electrode of the 6th nmos pass transistor, the drain electrode of the 6th nmos pass transistor is connected to the source electrode of the 7th nmos pass transistor, the drain electrode of the 5th nmos pass transistor is connected to the output of aforesaid voltage translation unit, and the drain electrode of the 7th nmos pass transistor is connected to the output node of low-pass filter unit; The grid of the 8th nmos pass transistor is connected to output node, source electrode and the grounded drain of this low-pass filter unit.
6. clock generating circuit as claimed in claim 5, is characterized in that: aforesaid voltage comparing unit comprises the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the 5th PMOS transistor and the 6th PMOS transistor; The grid of the 9th nmos pass transistor is connected to the second output of aforementioned currents bias unit, source ground, and drain electrode is connected to the first node E of voltage comparison unit; The grid of the tenth nmos pass transistor is connected to the output of low-pass filter unit, drain electrode is connected to the first node E of voltage comparison unit, source electrode is connected to the source electrode of the 5th PMOS transistor, the grid of the 11 nmos pass transistor is connected to the output of aforesaid voltage translation unit, drain electrode is connected to the first node E of voltage comparison unit, source electrode is connected to the source electrode of the 6th PMOS transistor, and the 5th PMOS transistor is connected with the grid of the 6th PMOS transistor, and drain electrode is connected to voltage signal VDD.
7. clock generating circuit as claimed in claim 6, it is characterized in that: aforementioned inverter module comprises the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 7th PMOS transistor and the 8th PMOS transistor, the grid of the tenth bi-NMOS transistor is connected to the second output of aforementioned currents bias unit, source ground, drain electrode is connected to the drain electrode of the 13 nmos pass transistor, the grid of the 13 nmos pass transistor is connected to the output of voltage comparison unit, and source electrode is connected to the output node of inverter module; The grid of the 7th PMOS transistor is connected to the first output of aforementioned currents bias unit, drain electrode is connected to voltage signal VDD, source electrode is connected to the drain electrode of the 8th PMOS transistor, the grid of the 8th PMOS transistor is connected to the output of voltage comparison unit, and source electrode is connected to the output node of inverter module.
8. clock generating circuit as claimed in claim 3, it is characterized in that: it also comprises the frequency unit being connected to clock driver cell output, this frequency unit carries out frequency division to the clock signal that clock driver cell exports can form the identical square-like clock signal of low and high level duty ratio.
9. a clock generating circuit, is characterized in that, it comprises:
Current biasing circuit, for providing reference current;
The crystal oscillation unit being operating current with the image current of described reference current, for generation of original clock signal;
The voltage shifts circuit being operating current with the image current of described reference current, for promoting the DC component of described original clock signal to obtain translation clock signal;
Low-pass filter circuit, for carrying out low-pass filtering to obtain the DC component of described translation clock signal to described translation clock signal;
With the voltage comparator circuit that the image current of described reference current is operating current, obtain square-like clock signal by the DC component of more described translation clock signal and described translation clock signal; With
It is with the inverter circuit that the image current of described reference current is operating current, anti-phase to obtain standard block clock signal for carrying out described square-like clock signal,
Wherein, aforementioned currents bias unit comprises PMOS transistor and nmos pass transistor, be connected to the node of PMOS transistor grid in current offset unit as the first output, be connected to the node of nmos pass transistor grid as the second output, and, aforementioned crystal oscillation unit comprises the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor and the first PMOS transistor, the second PMOS transistor, the grounded drain of the first nmos pass transistor, grid is connected to the first output of crystal oscillation unit, source electrode is connected to the output node of crystal oscillation unit, second nmos pass transistor, the grid of the 3rd nmos pass transistor and the 4th nmos pass transistor is all connected to voltage signal VDD, the drain electrode of the second nmos pass transistor is connected to the source electrode of the 3rd nmos pass transistor, the drain electrode of the 3rd nmos pass transistor is connected to the source electrode of the 4th nmos pass transistor, the source electrode of the second nmos pass transistor is connected to the first output of crystal oscillation unit, the drain electrode of the 4th nmos pass transistor is connected to the output node of crystal oscillation unit, the grid of the first PMOS transistor is connected to the first output of crystal oscillation unit, source electrode is connected to the output node of crystal oscillation unit, drain electrode and substrate are connected to the source electrode of the second PMOS transistor, second PMOS transistor grid is connected to described first output of described current offset unit, and drain electrode is connected to voltage signal VDD.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910242514.7A CN102098027B (en) | 2009-12-15 | 2009-12-15 | Clock signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910242514.7A CN102098027B (en) | 2009-12-15 | 2009-12-15 | Clock signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102098027A CN102098027A (en) | 2011-06-15 |
| CN102098027B true CN102098027B (en) | 2015-05-06 |
Family
ID=44130920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910242514.7A Expired - Fee Related CN102098027B (en) | 2009-12-15 | 2009-12-15 | Clock signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102098027B (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394604B (en) * | 2011-09-23 | 2015-02-11 | 惠州Tcl移动通信有限公司 | System and method for providing required clock signal for near-field wireless communication chip |
| CN103248321B (en) * | 2012-02-09 | 2016-06-08 | 安凯(广州)微电子技术有限公司 | A kind of quartz oscillator circuit and chip |
| CN103166604B (en) * | 2013-01-29 | 2015-10-28 | 殷明 | A kind of low-power consumption sheet internal clock produces circuit |
| CN104426523A (en) * | 2013-08-27 | 2015-03-18 | 飞思卡尔半导体公司 | Waveform transformation circuit with reduced jitter |
| CN104569518A (en) * | 2014-12-26 | 2015-04-29 | 上海贝岭股份有限公司 | Trans-impedance amplifier mass production test signal source |
| CN107294513B (en) * | 2016-03-30 | 2021-02-02 | 中芯国际集成电路制造(上海)有限公司 | Crystal oscillator circuit |
| CN110098836B (en) * | 2018-01-31 | 2024-03-01 | 长沙泰科阳微电子有限公司 | MDAC structure suitable for assembly line ADC |
| CN110113032B (en) * | 2019-05-17 | 2023-06-02 | 芯翼信息科技(南京)有限公司 | Crystal oscillation control circuit and control method thereof |
| CN116526978B (en) * | 2023-04-06 | 2024-06-11 | 北京兆讯恒达技术有限公司 | Anti-interference fast-starting single-ended crystal oscillator circuit and electronic equipment |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200973069Y (en) * | 2006-11-30 | 2007-11-07 | 深圳国人通信有限公司 | Feed forward power amplifier circuit and pick-up device of its adjacent power |
| CN101183862A (en) * | 2007-11-27 | 2008-05-21 | 北京中星微电子有限公司 | Self-starting current biasing circuit |
| CN101202540A (en) * | 2007-12-06 | 2008-06-18 | 北京芯技佳易微电子科技有限公司 | Oscillator and design method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101594145A (en) * | 2008-05-26 | 2009-12-02 | 中芯国际集成电路制造(上海)有限公司 | Self-biased phase-locked loop |
-
2009
- 2009-12-15 CN CN200910242514.7A patent/CN102098027B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN200973069Y (en) * | 2006-11-30 | 2007-11-07 | 深圳国人通信有限公司 | Feed forward power amplifier circuit and pick-up device of its adjacent power |
| CN101183862A (en) * | 2007-11-27 | 2008-05-21 | 北京中星微电子有限公司 | Self-starting current biasing circuit |
| CN101202540A (en) * | 2007-12-06 | 2008-06-18 | 北京芯技佳易微电子科技有限公司 | Oscillator and design method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102098027A (en) | 2011-06-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102098027B (en) | Clock signal generating circuit | |
| KR100841730B1 (en) | Osillator using the schmitt triger circuit | |
| CN107294506A (en) | Crystal-oscillator circuit | |
| CN103560686B (en) | The diodeless full-wave rectifier of AC/DC conversion on lower powered chip | |
| CN103401544B (en) | For the drive circuit of charging management chip external high pressure NMOS pipe | |
| CN103580606A (en) | Semiconductor device and control method thereof | |
| CN103825554A (en) | Crystal oscillator and method of generating oscillation signal | |
| CN102097923B (en) | Driving circuit with zero turn-off current and driving method thereof | |
| CN103546121A (en) | Rc oscillator | |
| US7710378B2 (en) | Drive apparatus of liquid crystal display device | |
| CN103151944A (en) | A self-starting transistor full-wave rectifier for alternating current-direct current conversion on a chip | |
| CN102594299A (en) | Square-wave generator circuit | |
| CN204013481U (en) | Realize the circuit structure that low-voltage crystal oscillator drives | |
| CN107294513A (en) | Crystal-oscillator circuit | |
| CN102545589B (en) | Direct current voltage conversion circuit | |
| CN104503532A (en) | Reference voltage production circuit of charge pump | |
| CN111867183B (en) | LED drive circuit, power frequency square wave signal sampling circuit and method | |
| CN101577537A (en) | Relaxation oscillator | |
| CN104993816B (en) | Voltage-multiplying circuit | |
| JP2007311846A (en) | Oscillation circuit | |
| CN101361410A (en) | High-frequency power supply circuit | |
| CN203590176U (en) | Rc oscillator | |
| CN104426480A (en) | Semiconductor integrated circuit and oscillation system | |
| CN105278322B (en) | Analog electronic clock | |
| CN101277562A (en) | Power supply circuit and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20191215 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |