CN102394604B

CN102394604B - System and method for providing required clock signal for near-field wireless communication chip

Info

Publication number: CN102394604B
Application number: CN201110285821.0A
Authority: CN
Inventors: 罗洪广; 贾强利
Original assignee: Huizhou TCL Mobile Communication Co Ltd
Current assignee: Huizhou TCL Mobile Communication Co Ltd
Priority date: 2011-09-23
Filing date: 2011-09-23
Publication date: 2015-02-11
Anticipated expiration: 2031-09-23
Also published as: CN102394604A; WO2013040947A1

Abstract

The invention is applicable to the technical field of mobile terminals and provides a system and a method for providing a required clock signal for a near-field wireless communication chip. The method comprises the following steps that: a voltage-controlled crystal oscillator generates a clock frequency of a power management chip and outputs a sine wave analog clock signal to a phase inverter; the phase inverter outputs a first rectangular wave digital clock signal to the power management chip; the power management chip outputs a second rectangular wave digital clock signal to a double-power power-supply conversion buffer; and the double-power power-supply conversion buffer converts the second rectangular wave digital clock signal into a third rectangular wave digital clock signal which is required for the near-field wireless communication chip. By arranging the double-power power-supply conversion buffer which is low in power consumption between the power management chip of the system and the near-field wireless communication chip, a load distance is realized, a system load is not increased, requirements on the functions of the wireless communication chip can be met, an external crystal oscillator is saved, the cost of products is effectively reduced, and the competitiveness of the products is improved.

Description

A kind ofly provide the system and method for required clock signal near field wireless communications chips

Technical field

The invention belongs to technical field of mobile terminals, particularly relating to a kind ofly provides the system and method for required clock signal near field wireless communications chips.

Background technology

Along with the development of society, the mobility of people's work and life is constantly strengthened, so also increasing to the demand of mobile terminal, people utilize mobile terminal except carrying out voice and messaging communication, mobile phone is also utilized to carry out the function services such as online payment, mobile-phone payment function has been subjected to the favor of more and more operator and user now, by NFC(Near Field Communication, near field wireless telecommunications) the technology smart mobile phone that realizes mobile-phone payment has boundless application prospect.

In prior art, integrated NFC function is just becoming a large attraction of mobile phone, on the MSM7227 platform of high pass (Qualcomm) company, the digital dock level being 2.6V@19.2MHz(and frequency 19.2MHz due to internal system clock signal is 2.6V), and internal system is 10-40MHz for realizing the clock request scope of the integrated NFC chip of online payment (model is PN544/65N), level is no more than 1.8 V, in order to ensure that NFC chip PN544/65N operationally inputs the clock signal meeting its needs, it is that chip PN544/65N improves the clock signal met the demands that current system adopts special frequency to be 27.12MHz external crystal, but special external crystal-controlled oscillation, expensive, and system is load-carrying limited in one's ability.

So prior art Shortcomings, need to be improved and enhanced.

Summary of the invention

The object of the present invention is to provide a kind of with low cost, circuit simple and power consumption is low for internal system NFC chip provides the system and method for required clock signal.

The present invention realizes like this, a kind ofly provide the system of required clock signal near field wireless communications chips, comprise VCXO, inverter, power management chip, described VCXO is for generation of the clock frequency of described power management chip, sine wave output simulated clock simulation clock signal gives described inverter, the first square wave dagital clock signal will be exported after described sinusoidal wave simulated clock simulation clock signal inversion to described power management chip by described inverter, described power management chip exports the second square wave dagital clock signal, it is characterized in that, also comprise power supply translation buffer and near field wireless communications chips, described power supply translation buffer signal input part is connected with described power management chip, its signal output part connects described near field wireless communications chips, described power supply translation buffer is used for the 3rd square wave dagital clock signal be converted to by described second square wave dagital clock signal required by the wireless communications chips of described near field.

Wherein, the clock frequency of described second square wave dagital clock signal is 19.2 megahertzes, and clock level is 2.6 volts, and the clock frequency of described 3rd square wave dagital clock signal is 19.2 megahertzes, and clock level is 1.8 volts.

Wherein, described power supply translation buffer is dual power supply translation buffer, comprise the first power supply and the second power supply, described first power supply is used for providing power supply for the input of described power supply translation buffer, and described second power supply is used for providing power supply for the output of described power supply translation buffer.

Wherein, described first power supply is power supply able to programme, and described power supply able to programme connects described power management chip, for controlling power supply.

Wherein, described dual power supply translation buffer model is 74AUP1T34GF.

Wherein, the pin 1 of described dual power supply translation buffer connects described first power supply, and pin 2 connects described power management chip, and pin 4 connects described near field wireless communications chips, and pin 6 connects described second power supply.

For near field wireless communications chips provides a method for required clock signal, it is characterized in that, described method comprises the steps:

A, VCXO produce power management chip clock frequency, and sine wave output simulated clock simulation clock signal gives described inverter, export the first square wave dagital clock signal to described power management chip after described inverter is anti-phase;

B, described power management chip export the second square wave dagital clock signal to power supply translation buffer;

Described second square wave dagital clock signal is converted to the 3rd square wave dagital clock signal needed for the wireless communications chips of near field by C, described power supply translation buffer.

Wherein, described power supply translation buffer is dual power supply translation buffer, comprise the first power supply and the second power supply, described first power supply is used for the supplying power for input end power supply for described power supply translation buffer, and described second power supply is used for providing power supply for the output of described power supply translation buffer.

Wherein, described dual power supply translation buffer model is 74AUP1T34GF, the pin 1 of described dual power supply translation buffer connects described first power supply, pin 2 connects described power management chip, pin 4 connects described near field wireless communications chips, and pin 6 connects described second power supply.

Beneficial effect of the present invention is: the invention provides a kind ofly provides the system and method for required clock signal near field wireless communications chips, by increasing a low-power consumption dual power supply translation buffer in system, achieve load isolation and do not increase system load, both NFC chip functional requirement can be met, save an external crystal-controlled oscillation again, effectively reduce the cost of product, improve the competitiveness of product.

Accompanying drawing explanation

Fig. 1 is circuit for switching between two clocks system block diagram of the present invention.

Fig. 2 is circuit for switching between two clocks schematic diagram of the present invention.

Fig. 3 to Figure 10 is the test waveform schematic diagram under circuit for switching between two clocks different operating state of the present invention.

Embodiment

The invention provides a kind ofly provides the system and method for required clock signal near field wireless communications chips, need to use special external crystal-controlled oscillation to solve in prior art to provide during satisfactory clock signal near field wireless communications chips, cause the problem that system cost is high like this, the present invention increases a low-power consumption dual power supply translation buffer between power supply managing chip and NFC chip (PN544/65N), the 2.6V@19.2MHz(frequency exported by power management chip is 19.2MHz, clock level is 2.6V) system digits clock signal, being converted to the 1.8V@19.2MHz(frequency meeting NFC chip requirement is 19.2MHz, clock level is 1.8V) dagital clock signal, and select programmable voltage input source to provide input power supply to power supply translation buffer, can ensure while mobile phone enters holding state, the power supply of buffer input is made also to enter holding state, thus reduce buffer power consumption.

For making object of the present invention, technical scheme and advantage clearly, clearly, developing simultaneously referring to accompanying drawing, the present invention is described in more detail for embodiment.

Accompanying drawing 1 is circuit for switching between two clocks system block diagram of the present invention, system comprises VCXO 100, inverter 200, power management chip 300, dual power supply translation buffer 400 and the wireless telecommunications of NFC(near field) chip 500, wherein, VCXO 100, for generation of the necessary clock frequency of power management chip 300, exports 19.2MHz(megahertz) sinusoidal wave simulated clock simulation clock signal is to inverter 200; Inverter 200 one end connects the output of VCXO 100, one end connects the input of power management chip 300, for the sine wave of reception being exported after inverter 200 first square wave dagital clock signal (frequency is 19.2MHz, and clock level is 2.85 volts) to power management chip 300; The output of power management chip 300 connects dual power supply translation buffer 400, power management chip 300 receive the first square wave dagital clock signal and the square wave (this square wave dagital clock signal is the second square wave dagital clock signal, and namely frequency is 19.2MH, digital dock level is 2.6 volts) exporting same frequency different digital clock level to dual power supply translation buffer 400; Dual power supply translation buffer 400 signal input part and signal output part are connected power management chip 300 and NFC chip 500 respectively, for the second square wave dagital clock signal received being converted to clock signal required by NFC chip 500 (i.e. the 3rd square wave dagital clock signal, its frequency is 19.2MHz, digital dock level is 1.8 volts); The present invention is in order to reduce the power consumption of buffer, have employed the translation buffer of dual power supply, divide two-way power supply for translation buffer 500, namely the power supply input and output of translation buffer 500 individually use different power supplies, input power supply is the first power supply, and output end power is the second power supply.

Accompanying drawing 2 is circuit for switching between two clocks schematic diagrams of the present invention, see Fig. 2, internal circuit of the present invention is described in detail, the present invention is based on MSM7227 platform, the operation principle of this platform is: system clock adopts the voltage controlled temperature compensated crystal oscillator KT3225P of 19.2MHz as clock oscillation source, binding post receives TRK_LO_ADJ signal (crystal oscillator frequency adjustment control signal), it is 100 ohm through resistance R1(resistance), signal is inputed to pin 1 end (the VCXO model selected by the present invention is KT3225P) of VCXO 100, the wherein pin 1 of one end difference contact resistance R1 and KT3225P of electric capacity C1, the other end ground connection of electric capacity C1, electric capacity C1 is 10nf, VCXO KT3225P comprises four pins, pin 1 is VCON, for voltage counting, pin 2 is grounding pin, pin 3 is output pin, for exporting 19.2MHz sine wave, pin 4 is supply voltage pin, by VREG_TCXO Power supply (wherein, VREG_TCXO is exclusively used in the voltage into VCTCXO circuit supply), the pin 3 inverter model connected selected by inverter 200(the present invention of VCXO KT3225P is 74LVC1G04GM), being 10nf through electric capacity C2(capacitance) capacitance filters the pin 2 of direct current (DC) bias to inverter 74LVC1G04GM, wherein inverter 74LVC1G04GM also comprises pin 1 and pin 5 is all unsettled, pin 3 ground connection, pin 6 is exclusively used in the voltage into VC_TCXO circuit supply for VREG_TCXO() Power supply, pin 4 exports the first square wave dagital clock signal (RF_TCXO: represent the signal branched away to the reference clock that RF chip provides from voltage controlled oscillator) and is 51 ohm through resistance R3(resistance) and electric capacity C3 (its capacitance is 100pf) power management chip model clock signal inputed to selected by power management chip 300(the present invention be PM7540), electric capacity C3 is an ac coupling capacitor, string is on the clock line of 19.2MHz, be used for stopping direct current, remove the offset voltage on clock line, at inverter 74LVC1G04GM pin 2 and pin 4 two ends, also a resistance R2(resistance in parallel is 100K ohm), the pin K12(K12 that first square wave dagital clock signal (frequency be 19.2MH, digital dock level be 2.85V) sends into power management chip PM7540 is TCXO_IN, clock signal input terminal), the pin D9 of power management chip PM7540 is TCXO_EN (TCXO_EN is the enable pin of clock signal), and the pin G10 of power management chip PM7540 is TCXO_OUT(clock signal output terminal).

First square wave dagital clock signal is by the buffer(buffer of power management chip 300 inside, not shown in FIG., hold buffer for receiving the square-wave signal of 19.2MHz at clock signal input TCXO_IN, the input of this pin must be that AC coupled is to avoid damaging inner direct current biasing) carry out power management and control, then exporting second this clock signal of square wave dagital clock signal PMIC_TCXO(through pin G10 is 2.6V@19.2MHz) do clock source use to system components, PMIC_TCXO is 74AUP1T34GF by the dual power supply translation buffer model selected by dual power supply translation buffer 400(the present invention) pin 2 input in 74AUP1T34GF, 74AUP1T34GF buffer also comprises pin 1 and powers as 74AUP1T34GF power input for VREG_TCXO, for connecting buffer input power (the first power supply), VREG_TCXO end provides 2.85 volts of power supplys, first power supply is that programmable power supply realizes standby management, programmable control and management is carried out by power management chip 300 pairs of input powers, when judgement system is when paying, there is provided power supply to 74AUP1T34GF buffer by the first power supply, when judging system not when paying, disconnect the power supply of 74AUP1T34GF, select a kind of programmable voltage source to provide input power supply to buffer, can ensure when mobile phone enters holding state, make the power supply of buffer input also enter holding state, thus reduce buffer power consumption, the pin 6 of 74AUP1T34GF meets VREG_MSME(VREG_MSME and holds as 74AUP1T34GF buffer output end is powered, and provides the supply power voltage of 1.8V), for connecting the second power supply, pin 3 ground connection, pin 5 is unsettled, pin 4 is signal output part and is connected to crystal oscillator or the external clock input pin that NFC chip (PN544/65N) pin E1(is XTAL1:NFC chip), 74AUP1T34GF buffer is used for the second square wave dagital clock signal (PMIC_TCXO) to be converted to and meets the 3rd square wave dagital clock signal that NFC chip (PN544/65N) requires (frequency is 19.2MHz, clock level is 1.8 volts) be transferred to NFC chip (PN544/65N) pin E1 by the pin 4 of 74AUP1T34GF buffer, NFC chip (PN544/65N) pin F1 is the external crystal-controlled oscillation output pin of XTAL2(NFC chip), by the capacity earth of 10pf, XTAL1 pin is when NFC chip is without external crystal-controlled oscillation, external clock can be connect.It should be noted that: power management chip of the present invention (PM7540) and NFC chip (PN544/65N) have a lot of pin herein, the pin that parts related to the present invention are connected only is depicted in circuit diagram of the present invention, remaining pin does not draw, all omit, but do not affect enforcement of the present invention.

PN544/65N chip is when realizing read write line function, the clock of 13.56MHz is needed to be used as time reference, the clock that the clock that this chip can utilize cell phone platform system to input needs to be converted to chip internal, different frequency clock signal can be accepted, the system clock of high pass MSM7227 platform is 19.2MHz, as the timing reference input of NFC chip, can comprise multi-frequency available: 13MHz, 19.2MHz, 26MHz and 38MHz.

PN544/65N input clock XTAL(XTAL1 and XTAL2 pin) parameter is shown in table 1 below:

Parameter	Index/condition	Minimum value	Type	Maximum	Unit
						Incoming frequency	10		40	MHz
Incoming frequency precision		-400		400	ppm
						Background noise angular frequency		50		KHz
Background noise	Frequency departure > 50kHz			-140	dBc/Hz
						Peak input voltage	0.2		1.8	V
Duty ratio		35		65	%

Can obtain from table 1, the peak input voltage of PN544/65N is 1.8 volts, by 74AUP1T34GF buffer conversion of the present invention, can meet the job requirement of this chip.

Accompanying drawing 3 to Figure 10 is the test waveform schematic diagram under circuit for switching between two clocks different operating state of the present invention, describe below in conjunction with accompanying drawing, Fig. 3 is under mobile phone state of activation, 74AUP1T34GF buffer input (VREG_TCXO end) power supply test waveform figure, Fig. 4 is under holding state, 74AUP1T34GF buffer input (VREG_TCXO end) power supply, compare can learn from Fig. 3 and Fig. 4, due to 74AUP1T34GF(VREG_TCXO) input be power supply able to programme input, so when mobile phone enters idle idle pattern, 74AUP1T34GF buffer input power supply also enters idle idle condition, so show the most of the time in oscillogram there is no electrical source consumption, thus reduce the power consumption of low-power dual power supply translation buffer 74AUP1T34GF.

Fig. 5 is under state of activation, 74AUP1T34GF buffer exports (VREG _ MSME end) power supply test waveform figure, Fig. 6 is under holding state, 74AUP1T34GF buffer exports (VREG _ MSME end) power supply test waveform figure, compare can learn from Fig. 5 and Fig. 6, because the Power supply of 74AUP1T34GF output does not adopt PLC technology, so output one direct power supply, test waveform can be found out, VREG_MSME is that the output of buffer 74AUPT34GF is powered, and the clock for buffer output provides the level reference of 1.8V.

Fig. 7 is internal system clock signal PMIC_TCXO(power management chip clock signal) test waveform figure, the crest voltage of this oscillogram is 2.63V, clock frequency is 19.2MHz, Fig. 8 is for being input to NFC chip XTAL1 pin clock signal, frequency is still 19.2MHz, but the crest voltage of this oscillogram reduces to 1.795V, as can be seen from test waveform figure, the system digits clock PMIC_TCXO of the 2.6V@19.2MHz that power management chip PM7540 exports is after buffer 74AUP1T34GF, the clock becoming the NFC_19.2MHz of 1.8V@19.2MHz is input to PN544/65N XTAL1 pin, parameters index all meets the clock request of 19.2MHz and the clock request of NFC chip, empirical tests, NFC chip utilizes this clock, all can normally work under reader pattern and P2P pattern.

Fig. 9 is input clock under state of activation and output clock: the level of input clock (PMIC_TCXO) is 2.59V, and export (19.2MHz_NFC) clock level and just reduce to 1.75V, Figure 10 is input clock under holding state and output clock: input clock (PMIC_TCXO) and export (19.2MHz_NFC) clock, as can be seen from test waveform, input clock PMIC_TCXO and output clock NFC_19.2MHZ is after mobile phone enters standby mode, all can enter idle idle state, thus extra stand-by power consumption can not be introduced.

In sum, the present invention increases a low-power consumption dual power supply translation buffer between power supply managing chip and NFC chip, by the system digits clock of the 2.6V@19.2MHz that power management chip exports, be converted to the digital dock meeting the 1.8V@19.2MHz that NFC chip requires, and the programmable voltage input source selected provides input power supply to power supply translation buffer, can ensure while mobile phone enters holding state, the power supply of buffer input is made also to enter holding state, thus reduce buffer power consumption, provide simple, the circuit for switching between two clocks of power saving.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims

1. one kind provides the system of required clock signal near field wireless communications chips, comprise VCXO, inverter, power management chip, described VCXO is for generation of the clock frequency of described power management chip, sine wave output simulated clock simulation clock signal gives described inverter, the first square wave dagital clock signal will be exported after described sinusoidal wave simulated clock simulation clock signal inversion to described power management chip by described inverter, described power management chip exports the second square wave dagital clock signal, it is characterized in that, also comprise power supply translation buffer and near field wireless communications chips, described power supply translation buffer signal input part is connected with described power management chip, its signal output part connects described near field wireless communications chips, described power supply translation buffer is used for the 3rd square wave dagital clock signal be converted to by described second square wave dagital clock signal required by the wireless communications chips of described near field.

2. according to claim 1ly provide the system of required clock signal near field wireless communications chips, it is characterized in that, the clock frequency of described second square wave dagital clock signal is 19.2 megahertzes, clock level is 2.6 volts, the clock frequency of described 3rd square wave dagital clock signal is 19.2 megahertzes, and clock level is 1.8 volts.

3. according to claim 1ly provide the system of required clock signal near field wireless communications chips, it is characterized in that, described power supply translation buffer is dual power supply translation buffer, described system comprises the first power supply and the second power supply, described first power supply is used for providing power supply for the input of described power supply translation buffer, and described second power supply is used for providing power supply for the output of described power supply translation buffer.

4. according to claim 3ly provide the system of required clock signal near field wireless communications chips, it is characterized in that, described first power supply is power supply able to programme, and described power supply able to programme connects described power management chip, for controlling power supply.

5. according to claim 3ly provide the system of required clock signal near field wireless communications chips, it is characterized in that, described dual power supply translation buffer model is 74AUP1T34GF.

6. according to claim 5ly provide the system of required clock signal near field wireless communications chips, it is characterized in that, the pin 1 of described dual power supply translation buffer connects described first power supply, pin 2 connects described power management chip, pin 4 connects described near field wireless communications chips, and pin 6 connects described second power supply.

7. near field wireless communications chips provides a method for required clock signal, it is characterized in that, described method comprises the steps:

VCXO produces power management chip clock frequency, and sine wave output simulated clock simulation clock signal is to inverter, exports the first square wave dagital clock signal to described power management chip after described inverter is anti-phase;

Described power management chip exports the second square wave dagital clock signal to power supply translation buffer;

Described second square wave dagital clock signal is converted to the 3rd square wave dagital clock signal needed for the wireless communications chips of near field by described power supply translation buffer.

8. according to claim 7ly provide the method for required clock signal near field wireless communications chips, it is characterized in that, the clock frequency of described second square wave dagital clock signal is 19.2 megahertzes, clock level is 2.6 volts, the clock frequency of described 3rd square wave dagital clock signal is 19.2 megahertzes, and clock level is 1.8 volts.

9. according to claim 7ly provide the method for required clock signal near field wireless communications chips, it is characterized in that, described power supply translation buffer is dual power supply translation buffer, for near field wireless communications chips provides the system of required clock signal to comprise the first power supply and the second power supply, described first power supply is used for providing power supply for the input of described power supply translation buffer, and described second power supply is used for providing power supply for the output of described power supply translation buffer.

10. according to claim 9ly provide the method for required clock signal near field wireless communications chips, it is characterized in that, described dual power supply translation buffer model is 74AUP1T34GF, the pin 1 of described dual power supply translation buffer connects described first power supply, pin 2 connects described power management chip, pin 4 connects described near field wireless communications chips, and pin 6 connects described second power supply.