CN101202540A - Oscillator and design method thereof - Google Patents
Oscillator and design method thereof Download PDFInfo
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- CN101202540A CN101202540A CN200710178885.4A CN200710178885A CN101202540A CN 101202540 A CN101202540 A CN 101202540A CN 200710178885 A CN200710178885 A CN 200710178885A CN 101202540 A CN101202540 A CN 101202540A
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Abstract
The invention discloses an oscillator and a design method thereof, comprising an offset module, a delaying module, a conversion module, a damping module and an output module; wherein, the offset module is used for generating an offset current according to an input signal; the delaying module is used for receiving the offset current which is generated by the offset module and generates the oscillation signals with scheduled periods according to the offset signal; the delaying module comprises a current source submodule, a variable resistance submodule and an inverter submodule; the maximum up-pulling current and the maximum down-pulling current of the delaying module are controlled by the power source submodule, thus controlling the power loss current of the delaying module; the delaying time of the delaying module is controlled by the variable resistance submodule; the gate capacitance of the delaying module is adjusted by the inverter submodule, thus controlling the power loss of the delaying module. The conversion module reduces the power loss of the oscillator by further reducing the DC current. The invention provides the oscillator which has simple structure, high efficiency, side application range and ultra-low power loss, and is especially suitable for low frequency application.
Description
Technical field
The present invention relates generally to the integrated circuit (IC) design field, relates in particular to a kind of oscillator and method for designing thereof.
Background technology
Oscillator is as the basic circuit of electronic system, in order to the needed various clock signals of generation system.For the dynamic power consumption during for system's operate as normal, the power consumption of oscillator is less relatively.But when system was in holding state, the power consumption of system was very little, if oscillator is still being worked, then its power consumption just seems very important as the part of stand-by power consumption.Especially for for battery powered mobile system, because stand-by power consumption is regarded as a key index of mobile system work, therefore the oscillator power consumption as the important component part of stand-by power consumption seems of crucial importance.
Dynamic random access memory (DRAM, Dynamic Random Access Memory) or pseudo-static random access memory (PSRAM, Pseudo Static Random Access Memory) as memory cell, are the important component parts of mobile system.Because there is leaky in memory cell, therefore, DRAM or PSRAM need periodically memory cell to be refreshed, the refresh clock signal control that refresh interval is produced by the sheet internal oscillator.The refresh interval of DRAM generally is controlled at a millisecond magnitude, and 15 milliseconds is a representative value.For capacity is that 1Mbit, storage array are 1024 * 1024 DRAM, if refresh i.e. 1024 memory cell of row at every turn, then need 1024 refresh clock cycles to finish refreshing of whole memory, therefore, for a duration be 15 milliseconds refresh time at interval, the clock cycle maximum that just requires to refresh is 15 microseconds.For the designer, designed power consumption in order to the oscillator that produces refresh clock signal should be low as much as possible, thereby reduce the power consumption as the DRAM or the PSRAM of memory cell, and then reduce the stand-by power consumption of whole mobile system.
In numerous oscillators, the advantage of circular type shaker is to be easy to integratedly, thereby is widely used as the sheet internal oscillator.Fig. 1 be in the prior art based on the circular type shaker of inverter, it is formed by joining end to end more than or equal to 3 odd number inverter, the cycle of output clock is approximately equal to the inverter number and multiply by time-delay of inverter rising edge and trailing edge time-delay sum.Therefore, in case determined the time-delay of inverter, just can calculate the output clock cycle by the time-delay and the progression of inverter.In order to realize the clock cycle of microsecond level, with a lot of progression of needs and the very big inverter of time-delay.
For the integrated circuit fabrication process of sub-micron, adopting the time-delay of the inverter of minimum channel length only is tens psecs.Though, consider, will be the most effectual way that increases the inverter time-delay by increasing transistorized channel length from area and power consumption for inverter adds the time-delay that capacitive load can increase inverter.For long channel transistor, electric current and transistorized channel length are inversely proportional to during transistor turns, and the load of inverter is directly proportional with transistorized channel length in oscillator, so square being directly proportional of the time-delay of inverter and transistor channel length.Yet for low frequency applications, when being the microsecond level as the clock cycle, the chip area that circular type shaker shown in Figure 1 takies is still bigger.
Fig. 2 be in the prior art in the circular oscillator running inverter at the corresponding levels to next stage inverter charging and discharge process schematic diagram.Among Fig. 2, in inverter charging process at the corresponding levels, from the one part of current I of source current
1Gate capacitance and output capacitance at the corresponding levels to the next stage inverter are charged, from the remainder electric current I of source current
2Then flow directly into the earth polar; In inverter discharge process at the corresponding levels, the electric current that flows into the earth polar comprises the electric current I of forming by from the discharging current of the gate capacitance of next stage inverter and output capacitance at the corresponding levels
3With electric current I from power supply
4In a cycle of oscillation, the average power consumption electric current of oscillator equals from source current I
1, I
2, I
4The mean value of sum also equals to flow to the earth polar electric current I
2, I
3, I
4The mean value of sum this shows, to the charging current I of electric capacity
1Mean value equal discharging current I
3Mean value.
On the one hand, to the charging current I of electric capacity
1Or discharging current I
3Mean value determine that by the product of total capacitance value, clock frequency and the supply voltage of oscillator on the other hand, be that resistance and electric capacity amass be directly proportional with the capacitor charge and discharge time constant cycle of oscillation.Therefore, the charging current I of cycle of oscillation and electric capacity
1Or discharging current I3 is directly proportional with supply voltage, and equivalent resistance is inversely proportional to during with capacitor charge and discharge.Therefore, increase the channel length of inverter transistor, the equivalent resistance when promptly increasing capacitor charge and discharge helps reducing the power consumption of oscillator.In addition, for fixing cycle of oscillation, to the charging current I of electric capacity
1Or discharging current I
3There is minimum value.Cycle of oscillation is long more, to the charging current I of electric capacity
1Or discharging current I
3More little.
Another part electric current I as static current of lcd
2, I
4Sum is relevant with the slope of the input signal of inverter.For low frequency applications, in the oscillator time-delay of inverter very big, the input of every grade of inverter is very slow, therefore, electric current I
2, I
4Sum will account for significant proportion in total static current of lcd.In addition, buffer circuit 101 and output circuit 102 among Fig. 1 also can consume one part of current, and this part electric current is also very crucial for the design of super low-power consumption.In a word, the circular type shaker power consumption based on inverter is bigger.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of oscillator and method for designing thereof, by this oscillator and method for designing thereof, be reached for the purpose of oscillator that the user provides a kind of simplicity of design, efficient, applied range, is particularly useful for the super low-power consumption of low frequency applications.
The invention provides a kind of oscillator, comprising:
Biasing module comprises P-type mos PMOS transistor and N type metal oxide semiconductor nmos pass transistor, is used for producing bias current according to input signal;
Time delay module is used for the oscillator signal according to described bias current generation predetermined period;
Described time delay module comprises current source submodule and inverter submodule; Described current source submodule comprises the first current source submodule, the second current source submodule;
The first current source submodule, inverter submodule, the second current source submodule are connected in series in proper order, wherein,
The described first current source submodule comprises the PMOS transistor;
The described second current source submodule comprises nmos pass transistor;
Transistorized size of PMOS in the described first current source submodule and the ratio between the transistorized size of PMOS in the described biasing module are predetermined value, determine the pull-up current of time delay module and the ratio value of bias current by this predetermined value;
Ratio between the size of the nmos pass transistor in the described second current source submodule and the size of the nmos pass transistor in the described biasing module is a predetermined value, determines the pull-down current of time delay module and the ratio value of bias current by this predetermined value.
Described pull-up current of this oscillator and described pull-down current are one of parameter of the static current of lcd of determining time delay module.
The described time delay module of this oscillator also comprises the variable resistor submodule, and described variable resistor submodule comprises: the first variable resistor submodule and the second adjustable resistance submodule,
The described first variable resistor submodule comprises the PMOS transistor, and described the second adjustable resistance submodule comprises nmos pass transistor;
The channel length of the nmos pass transistor in the PMOS transistor AND gate the second adjustable resistance submodule in the described first variable resistor submodule is a predetermined value, the delay time of this predetermined value control time delay module.
In this oscillator,
Described inverter submodule comprises PMOS transistor and nmos pass transistor, wherein,
The channel length and the width of the PMOS transistor AND gate nmos pass transistor in the described inverter submodule are predetermined value, and this predetermined value is determined the gate capacitance value of time delay module;
The capacitance of described delay unit is one of parameter of determining the time delay module power consumption.
This oscillator also comprises:
Modular converter is used for a plurality of oscillator signals that time delay module produces are synthesized, and the output of the oscillator signal after will synthesizing.
The described modular converter of this oscillator can comprise multistage converting unit, and converting unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
In this oscillator,
The bound-time of the oscillator signal after the described conversion is less than the bound-time of the oscillator signal of time delay module generation.
This oscillator also comprises:
Buffer module is used for oscillator signal is carried out shaping, and the oscillator signal after the shaping is exported.
In this oscillator,
Described buffer module comprises the multi-buffer unit, and buffer cell comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
Oscillator signal after the described shaping of this oscillator is a clock signal.
This oscillator also comprises:
Output module is used for outputting oscillation signal.
In this oscillator,
Described output module comprises multistage output unit, and output unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
The described biasing module of this oscillator also comprises electric capacity, is used for the electric current of stabilized oscillator.
In this oscillator, described input signal is current signal or voltage signal.
The present invention also provides a kind of method for designing of oscillator, comprising:
Biasing module is set;
Described biasing module comprises PMOS transistor and nmos pass transistor, is used for producing bias current according to the signal of telecommunication of input;
And, time delay module is set;
Described time delay module is used to receive the bias current that biasing module produces, and produces the oscillator signal of predetermined period according to this bias current;
Described time delay module comprises current source submodule and inverter submodule; Described current source submodule comprises the first current source submodule, the second current source submodule;
The first current source submodule, inverter submodule, the second current source submodule are connected in series in proper order, wherein,
The described first current source submodule comprises the PMOS transistor;
The described second current source submodule comprises nmos pass transistor;
Set transistorized size of PMOS in the described first current source submodule and the ratio value between the transistorized size of PMOS in the described biasing module, determine the pull-up current of time delay module and the ratio value of bias current by this ratio value;
Set the ratio value between the size of the size of the nmos pass transistor in the described second current source submodule and the nmos pass transistor in the described biasing module, determine the pull-down current of time delay module and the ratio value of bias current by this ratio value.
This method is by regulating described pull-up current and described pull-down current is controlled the static current of lcd of time delay module.
This method also comprises:
The variable resistor submodule is set in time delay module;
Described variable resistor submodule comprises the first variable resistor submodule and second power transformation resistance submodule;
The described first variable resistor submodule comprises the PMOS transistor, and described the second adjustable resistance submodule comprises nmos pass transistor;
By setting the channel length of the nmos pass transistor in the PMOS transistor AND gate the second adjustable resistance submodule in the described first variable resistor submodule, the delay time of control time delay module.
In this method,
Described inverter submodule comprises PMOS transistor and nmos pass transistor, wherein,
The channel length by setting the PMOS transistor AND gate nmos pass transistor in the described inverter submodule and the gate capacitance value of width adjusting time delay module; By the gate capacitance value of regulating described time delay module the power consumption of described time delay module is controlled.
This method also comprises:
Modular converter is set;
Described modular converter is used for a plurality of oscillator signals that time delay module produces are synthesized, and the output of the oscillator signal after will synthesizing.
In this method,
Described modular converter can comprise multistage converting unit, and converting unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
In this method,
The bound-time of the oscillator signal after the described conversion is less than the bound-time of the oscillator signal of time delay module generation.
This method also comprises:
Buffer module is set;
Described buffer module is used for oscillator signal is carried out shaping, and the oscillator signal after the shaping is exported.
In this method,
Described buffer module comprises the multi-buffer unit, and buffer cell comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
Oscillator signal after the described shaping of this method is a clock signal.
This method also comprises:
Output module is set;
Described output module is used for outputting oscillation signal.
In this method,
Described output module comprises multistage output unit, and output unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
This method also comprises:
In described biasing module, electric capacity is set, is used for the electric current of stabilized oscillator.
The described input signal of this method is current signal or voltage signal.
Oscillator of the present invention and method for designing thereof, by the biasing module in the oscillator is set, the PMOS transistor group in the time delay module and the version of nmos pass transistor group, channel length, the dimension scale relation, gate capacitance to delay unit in the time delay module, maximum pull-up current and maximum pull-down current and variable resistor control, thereby under the situation that the transistorized size of sum of series of delay unit remains unchanged in guaranteeing time delay module, by reducing bias current, the delay time that increases time delay module is realized bigger cycle of oscillation, and guarantee that chip area can not increase along with the increase of cycle of oscillation, and reduce supply voltage to the influence of cycle of oscillation, for the user provides a kind of simplicity of design, efficiently, applied range, the beneficial effect of oscillator that is particularly useful for the super low-power consumption of low frequency applications.
Description of drawings
Fig. 1 is based on the circular type shaker of inverter in the prior art;
Fig. 2 be in the prior art in the circular oscillator running inverter at the corresponding levels to next stage inverter charging and discharge process schematic diagram;
Fig. 3 is the gate level circuit structure chart of low-power consumption oscillator in the present invention's first specific embodiment;
Fig. 4 is the signal waveforms of oscillator in the present invention's first specific embodiment;
Fig. 5 is the gate level circuit structure chart of low-power consumption oscillator in the present invention's second specific embodiment.
Embodiment
Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.
Fig. 3 comprises among the figure: biasing module 31, time delay module 32, modular converter 33, buffer module 34 and output module 35 for the gate level circuit structure chart of low-power consumption oscillator in the present invention's first specific embodiment.
In the inverter submodule, PMOS transistor P1, P2, P3, P4, P5 and nmos pass transistor N1, the N2 that links to each other with output node, N3, N4, N5 adopt less channel length and width, to reduce the gate capacitance of delay unit.
The current source submodule comprises the first current source submodule and the second current source submodule, the maximum pull-up current and the bias current I of the proportionate relationship decision time delay module 32 between the size of the size of the PMOS transistor P6 in the first current source submodule, P7, P8, P9, P10 and the PMOS transistor P24 in the biasing module 31
BiasProportionate relationship, the maximum pull-down current and the bias current I of proportionate relationship between the size of the size of nmos pass transistor N6, the N7 in the second current source submodule, N8, N9, N10 and the nmos pass transistor N24 in biasing circuit decision time delay module 32
BiasProportionate relationship.
The variable resistor submodule comprises the first variable resistor submodule and the second adjustable resistance submodule, nmos pass transistor N11, N12, N13, N14, N15 in PMOS transistor P11, P12, P13, P14, P15 and the second adjustable resistance submodule in the first variable resistor submodule all adopts long channel length, be used to produce variable resistor, to reduce the influence of supply voltage to cycle of oscillation.
The first variable resistor submodule in the time delay module 32, the first current source submodule, inverter submodule, the second current source submodule and the second adjustable resistance submodule are connected in series from top to bottom, and PMOS in each submodule or nmos pass transistor are corresponding to be connected.
Be that with the difference of oscillator among Fig. 1 the maximum pull-up current and the maximum pull-down current of the biasing module 31 control time delay modules 32 of oscillator among Fig. 3 are by changing bias current I
BiasCan change the time-delay of time delay module 32.When low frequency applications, can the situation that the transistorized size of sum of series of delay unit remains unchanged in guaranteeing time delay module under, by reducing bias current I
Bias, the delay time that increases time delay module 32 realizes bigger cycle of oscillation, thereby guarantees that chip area can not increase along with the increase of cycle of oscillation.
All adopt less channel length and width by PMOS transistor P1, P2, P3, P4, P5 and nmos pass transistor N1, N2, N3, N4, the N5 that will link to each other with output node, the electric capacity that participates in vibration is reduced, thereby electric current or discharging current that the electric capacity that participates in vibration is charged are reduced thereupon.
Make the maximum pull-up current of time delay module 32 and maximum pull-down current very little by biasing module 31, thereby make the through current of time delay module 32 in oscillatory process also very little.Compare with the pierce circuit of Fig. 1, the static current of lcd of the oscillator of Fig. 3 will significantly reduce.For the cycle be the microsecond level, the power consumption of the pierce circuit of Fig. 3 can reach microampere order even littler.
Suppose not exist in the time delay module 32 PMOS transistor P11, P12, P13, P14, P15 and nmos pass transistor N11, N12, N13, N14, N15, then the current mirror of the PMOS transistor P6 in the time delay module 32, P7, P8, P9, P10 and PMOS transistor P24 composition will be controlled the maximum pull-up current of time delay module 32; The current mirror that nmos pass transistor N6, N7 in the time delay module 32, N8, N9, N10 and nmos pass transistor N24 form will be controlled the maximum pull-down current of time delay module 32; Maximum pull-up current and maximum pull-down current all are subjected to bias current I
BiasInfluence, but little with the supply voltage relation.Therefore, along with the rising of supply voltage, the time-delay of time delay module 32 increases, and also increase cycle of oscillation thereupon.Therefore, in order to reduce the influence of supply voltage to cycle of oscillation, just need be at the source of PMOS transistor P6, P7, P8, P9, P10 and nmos pass transistor N6, N7, N8, N9, N10 end serial connection variable resistor, and this variable-resistance resistance is reduced along with the rising of supply voltage, the electric current of delay unit is increased along with the rising of supply voltage, thereby stablize the delay time of delay unit.Time delay module 32 adopts just at the source of PMOS transistor P6, P7, P8, P9, P10 end serial connection PMOS transistor P11, P12, P13, P14, P15, at the source of nmos pass transistor N6, N7, N8, N9, N10 end serial connection nmos pass transistor N11, N12, N13, N14, N15, thereby make PMOS transistor P11, P12, P13, P14, P15 and nmos pass transistor N11, N12, N13, N14, N15 serve as variable resistor, in order to the delay time of control delay unit, thereby reduce the influence of supply voltage to cycle of oscillation.
In most of the cases, need be to the oscillator signal shaping of time delay module 32 generations, the clock signal of the approximate rectangular ripple of final outwards output, in this is specifically implemented, will be by modular converter 33, buffer module 34 and output module 35 are realized.
Fig. 4 is the oscillator signal oscillogram of oscillator in the present invention's first specific embodiment.Among Fig. 4, the first behavior oscillator signal a
31Oscillogram, the second behavior oscillator signal a
33Oscillogram, the third line is oscillator signal b
31Oscillogram, fourth line is oscillator signal b
32Oscillogram, fifth line is oscillator signal b
33Oscillogram.
Be for 300 nanoseconds the cycle of oscillation of above-mentioned 5 oscillator signals, wherein, from oscillator signal a
31Oscillogram as can be seen, oscillator signal a
33Rise time and fall time all more than 140 nanoseconds, if oscillator signal a
33Directly enter buffer module 34, make that PMOS transistor and nmos pass transistor are in conducting state simultaneously in the buffer module 34 in the long time, forms bigger through current, thereby cause the power consumption increase of oscillator.Oscillator signal b after modular converter 33 shapings
31Rise time and fall time be reduced to hundreds of even tens psecs, thereby reduce the static current of lcd of buffer module 34 greatly.Because oscillator signal a
31Phase place than oscillator signal a
33Promptly 72 ° of leading 1/5 cycles, therefore, as oscillator signal a
33During rising, oscillator signal a
31Risen to high level, the nmos pass transistor P17 in the modular converter 33 is turn-offed; As oscillator signal a
33During decline, oscillator signal a
31Dropped to low level, the PMOS transistor N17 of modular converter is turn-offed.Therefore, though oscillator signal a
31, a
33Rise time and fall time very long, but modular converter 33 can't produce through current when switching, and only produces the charge or discharge electric current to buffer module 34.This point is the key point that the present invention's first specific embodiment is realized the super low-power consumption oscillator.
Fig. 5 comprises among the figure: biasing module 51, time delay module 52, modular converter 53, buffer module 54 and output module 55 for the gate level circuit structure chart of low-power consumption oscillator in the present invention's second specific embodiment.
In the inverter submodule, PMOS transistor P1, P2, P3, P4, P5 and nmos pass transistor N1, the N2 that links to each other with output node, N3, N4, N5 adopt less channel length and width, to reduce the gate capacitance of delay unit.
The current source submodule comprises the first current source submodule and the second current source submodule, the maximum pull-up current and the bias current I of the size relationship decision time delay module 52 of the size of the PMOS transistor P6 in the first current source submodule, P7, P8, P9, P10 and the PMOS transistor P24 in the biasing module 51
BiasRatio, the maximum pull-down current and the bias current I of the size relationship of the size of nmos pass transistor N6, the N7 in the second current source submodule, N8, N9, N10 and the nmos pass transistor N24 in biasing circuit decision time delay module 52
BiasRatio.
The variable resistor submodule comprises the first variable resistor submodule and the second adjustable resistance submodule, nmos pass transistor N11, N12, N13, N14, N15 in PMOS transistor P11, P12, P13, P14, P15 and the second adjustable resistance submodule in the first variable resistor submodule all adopts long channel length, be used to produce variable resistor, to reduce the influence of supply voltage to cycle of oscillation.
The first variable resistor submodule in the time delay module 52, the first current source submodule, inverter submodule, the second current source submodule and the second adjustable resistance submodule are connected in series from top to bottom, and PMOS in each submodule or nmos pass transistor are corresponding to be connected.
Be that with the difference of oscillator among Fig. 1 the maximum pull-up current and the maximum pull-down current of the biasing module 51 control time delay modules 52 of oscillator among Fig. 5 are by changing bias current I
BiasCan change the time-delay of time delay module 52.When low frequency applications, can the situation that the transistorized size of sum of series of delay unit remains unchanged in guaranteeing time delay module under, by reducing bias current I
Bias, the delay time that increases time delay module 52 realizes bigger cycle of oscillation, thereby guarantees that chip area can not increase along with the increase of cycle of oscillation.
All adopt less channel length and width by PMOS transistor P1, P2, P3, P4, P5 and nmos pass transistor N1, N2, N3, N4, the N5 that will link to each other with output node, the electric capacity that participates in vibration is reduced, thereby electric current or discharging current that the electric capacity that participates in vibration is charged are reduced thereupon.
Make the maximum pull-up current of time delay module 52 and maximum pull-down current very little by biasing module 51, thereby make the through current of time delay module 52 in oscillatory process also very little.Compare with the pierce circuit of Fig. 1, the static current of lcd of the oscillator of Fig. 5 will significantly reduce.For the cycle be the microsecond level, the power consumption of the pierce circuit of Fig. 5 can reach microampere order even littler.
Suppose not exist in the time delay module 52 PMOS transistor P11, P12, P13, P14, P15 and nmos pass transistor N11, N12, N13, N14, N15, the PMOS transistor P6 in the time delay module 52 then, P7, P8, P9, the current mirror that P10 and PMOS transistor P24 form will be controlled the maximum pull-up current of time delay module 52; Nmos pass transistor N6 in the time delay module 52, N7, N8, N9, the current mirror that N10 and nmos pass transistor N24 form will be controlled the maximum pull-down current of time delay module 52; Maximum pull-up current and maximum pull-down current all are subjected to bias current I
BiasInfluence, but little with the supply voltage relation.Therefore, along with the rising of supply voltage, the time-delay of time delay module 52 increases, and also increase cycle of oscillation thereupon.Therefore, in order to reduce the influence of supply voltage to cycle of oscillation, just need be at PMOS transistor P6, P7, P8, P9, the source end serial connection variable resistor of P10 and nmos pass transistor N6, N7, N8, N9, N10, and this variable-resistance resistance is reduced along with the rising of supply voltage, the electric current of delay unit is increased along with the rising of supply voltage, thereby stablize the delay time of delay unit.Time delay module 52 adopts just at the source of PMOS transistor P6, P7, P8, P9, P10 end serial connection PMOS transistor P11, P12, P13, P14, P15, at the source of nmos pass transistor N6, N7, N8, N9, N10 end serial connection nmos pass transistor N11, N12, N13, N14, N15, thereby make PMOS transistor P11, P12, P13, P14, P15 and nmos pass transistor N11, N12, N13, N14, N15 serve as variable resistor, in order to the delay time of control delay unit, thereby reduce the influence of supply voltage to cycle of oscillation.
In most of the cases, need be to the oscillator signal shaping of time delay module 52 generations, the clock signal of the approximate rectangular ripple of final outwards output, in this is specifically implemented, will be by modular converter 53, buffer module 54 and output module 55 are realized.
In the present embodiment, in order to produce longer cycle of oscillation, modular converter 53 has adopted the two-stage change-over circuit, and the change-over circuit of being made up of PMOS transistor P26, P27 and nmos pass transistor N26, N27 is with oscillator signal a
51And a
53The synthetic oscillator signal b that produces
511, the change-over circuit of being made up of PMOS transistor P28, P29 and nmos pass transistor N28, N29 is with oscillator signal a
53, a
55The synthetic oscillator signal b that produces
512, the second level change-over circuit of being made up of PMOS transistor P16, P17 and nmos pass transistor N16, N17 is with oscillator signal b
511, b
512The synthetic oscillator signal b that produces
51, oscillator signal b
51After the further shaping of buffer circuit, export by output circuit.
In the biasing module 51 in biasing module 31 in the present invention's first specific embodiment and the present invention's second specific embodiment, all adopted capacitor C
1And C
2, its purpose is the electric current of stabilized oscillator, reduces power supply or the ground fluctuation influence to it.
In the specific embodiment of the invention, described less channel length and width are to be no more than minimum channel length value and width value in the logic process manufacturing technology 1.5 times, and it is microsecond level even bigger low frequency applications that described low-power consumption (microampere is following) oscillator is particularly useful for cycle of oscillation.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (28)
1. oscillator comprises:
Biasing module comprises P-type mos PMOS transistor and N type metal oxide semiconductor nmos pass transistor, is used for producing bias current according to input signal;
Time delay module is used for the oscillator signal according to described bias current generation predetermined period;
It is characterized in that described time delay module comprises current source submodule and inverter submodule; Described current source submodule comprises the first current source submodule, the second current source submodule;
The first current source submodule, inverter submodule, the second current source submodule are connected in series in proper order, wherein,
The described first current source submodule comprises the PMOS transistor;
The described second current source submodule comprises nmos pass transistor;
Transistorized size of PMOS in the described first current source submodule and the ratio between the transistorized size of PMOS in the described biasing module are predetermined value, determine the pull-up current of time delay module and the ratio value of bias current by this predetermined value;
Ratio between the size of the nmos pass transistor in the described second current source submodule and the size of the nmos pass transistor in the described biasing module is a predetermined value, determines the pull-down current of time delay module and the ratio value of bias current by this predetermined value.
2. oscillator according to claim 1 is characterized in that, described pull-up current and described pull-down current are one of parameter of the static current of lcd of determining time delay module.
3. oscillator according to claim 1 is characterized in that described time delay module also comprises the variable resistor submodule, and described variable resistor submodule comprises: the first variable resistor submodule and the second adjustable resistance submodule,
The described first variable resistor submodule comprises the PMOS transistor, and described the second adjustable resistance submodule comprises nmos pass transistor;
The channel length of the nmos pass transistor in the PMOS transistor AND gate the second adjustable resistance submodule in the described first variable resistor submodule is a predetermined value, the delay time of this predetermined value control time delay module.
4. oscillator according to claim 1 is characterized in that,
Described inverter submodule comprises PMOS transistor and nmos pass transistor, wherein,
The channel length and the width of the PMOS transistor AND gate nmos pass transistor in the described inverter submodule are predetermined value, and this predetermined value is determined the gate capacitance value of time delay module;
The capacitance of described delay unit is one of parameter of determining the time delay module power consumption.
5. oscillator according to claim 1 is characterized in that, also comprises:
Modular converter is used for a plurality of oscillator signals that time delay module produces are synthesized, and the output of the oscillator signal after will synthesizing.
6. oscillator according to claim 5 is characterized in that described modular converter can comprise multistage converting unit, and converting unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
7. according to claim 5 or 6 described oscillators, it is characterized in that,
The bound-time of the oscillator signal after the described conversion is less than the bound-time of the oscillator signal of time delay module generation.
8. oscillator according to claim 1 is characterized in that, also comprises:
Buffer module is used for oscillator signal is carried out shaping, and the oscillator signal after the shaping is exported.
9. oscillator according to claim 8 is characterized in that,
Described buffer module comprises the multi-buffer unit, and buffer cell comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
10. according to Claim 8 or 9 described oscillators, it is characterized in that the oscillator signal after the described shaping is a clock signal.
11. oscillator according to claim 1 is characterized in that, also comprises:
Output module is used for outputting oscillation signal.
12. oscillator according to claim 11 is characterized in that,
Described output module comprises multistage output unit, and output unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
13. oscillator according to claim 1 is characterized in that, described biasing module also comprises electric capacity, is used for the electric current of stabilized oscillator.
14. oscillator according to claim 1 is characterized in that, described input signal is current signal or voltage signal.
15. the method for designing of an oscillator is characterized in that, comprising:
Biasing module is set;
Described biasing module comprises PMOS transistor and nmos pass transistor, is used for producing bias current according to the signal of telecommunication of input;
And, time delay module is set;
Described time delay module is used to receive the bias current that biasing module produces, and produces the oscillator signal of predetermined period according to this bias current;
It is characterized in that,
Described time delay module comprises current source submodule and inverter submodule; Described current source submodule comprises the first current source submodule, the second current source submodule;
The first current source submodule, inverter submodule, the second current source submodule are connected in series in proper order, wherein,
The described first current source submodule comprises the PMOS transistor;
The described second current source submodule comprises nmos pass transistor;
Set transistorized size of PMOS in the described first current source submodule and the ratio value between the transistorized size of PMOS in the described biasing module, determine the pull-up current of time delay module and the ratio value of bias current by this ratio value;
Set the ratio value between the size of the size of the nmos pass transistor in the described second current source submodule and the nmos pass transistor in the described biasing module, determine the pull-down current of time delay module and the ratio value of bias current by this ratio value.
16. method according to claim 15 is characterized in that, by regulating described pull-up current and described pull-down current is controlled the static current of lcd of time delay module.
17. method according to claim 15 is characterized in that, also comprises:
The variable resistor submodule is set in time delay module;
Described variable resistor submodule comprises the first variable resistor submodule and second power transformation resistance submodule;
The described first variable resistor submodule comprises the PMOS transistor, and described the second adjustable resistance submodule comprises nmos pass transistor;
By setting the channel length of the nmos pass transistor in the PMOS transistor AND gate the second adjustable resistance submodule in the described first variable resistor submodule, the delay time of control time delay module.
18. method according to claim 15 is characterized in that,
Described inverter submodule comprises PMOS transistor and nmos pass transistor, wherein,
The channel length by setting the PMOS transistor AND gate nmos pass transistor in the described inverter submodule and the gate capacitance value of width adjusting time delay module; By the gate capacitance value of regulating described time delay module the power consumption of described time delay module is controlled.
19. method according to claim 15 is characterized in that, also comprises:
Modular converter is set;
Described modular converter is used for a plurality of oscillator signals that time delay module produces are synthesized, and the output of the oscillator signal after will synthesizing.
20. method according to claim 19 is characterized in that,
Described modular converter can comprise multistage converting unit, and converting unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
21. according to claim 19 or 20 described methods, it is characterized in that,
The bound-time of the oscillator signal after the described conversion is less than the bound-time of the oscillator signal of time delay module generation.
22. method according to claim 15 is characterized in that, also comprises:
Buffer module is set;
Described buffer module is used for oscillator signal is carried out shaping, and the oscillator signal after the shaping is exported.
23. method according to claim 22 is characterized in that,
Described buffer module comprises the multi-buffer unit, and buffer cell comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
24., it is characterized in that the oscillator signal after the described shaping is a clock signal according to claim 22 or 23 described methods.
25. method according to claim 15 is characterized in that, also comprises:
Output module is set;
Described output module is used for outputting oscillation signal.
26. method according to claim 25 is characterized in that,
Described output module comprises multistage output unit, and output unit comprises the nmos pass transistor that the PMOS transistor AND gate that is connected in series is connected in series.
27. method according to claim 15 is characterized in that, also comprises:
In described biasing module, electric capacity is set, is used for the electric current of stabilized oscillator.
28. method according to claim 15 is characterized in that, described input signal is current signal or voltage signal.
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| CN200710178885.4A CN100574099C (en) | 2007-12-06 | 2007-12-06 | A kind of oscillator and method for designing thereof |
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| CN200710178885.4A CN100574099C (en) | 2007-12-06 | 2007-12-06 | A kind of oscillator and method for designing thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098027A (en) * | 2009-12-15 | 2011-06-15 | 北京中星微电子有限公司 | Clock signal generating circuit |
| CN102447248A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | Pull-down current input output circuit |
| CN105281749A (en) * | 2015-10-30 | 2016-01-27 | 中国电子科技集团公司第四十四研究所 | Light-frequency conversion circuit |
| CN108809080A (en) * | 2017-04-28 | 2018-11-13 | 合肥格易集成电路有限公司 | A kind of biasing circuit, oscillator and charge pump |
| CN109274375A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of voltage control delay unit and High-precision time-to-digital converter |
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2007
- 2007-12-06 CN CN200710178885.4A patent/CN100574099C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098027A (en) * | 2009-12-15 | 2011-06-15 | 北京中星微电子有限公司 | Clock signal generating circuit |
| CN102098027B (en) * | 2009-12-15 | 2015-05-06 | 北京中星微电子有限公司 | Clock signal generating circuit |
| CN102447248A (en) * | 2010-10-12 | 2012-05-09 | 上海华虹Nec电子有限公司 | Pull-down current input output circuit |
| CN102447248B (en) * | 2010-10-12 | 2014-02-26 | 上海华虹宏力半导体制造有限公司 | Pull-down current input output circuit |
| CN105281749A (en) * | 2015-10-30 | 2016-01-27 | 中国电子科技集团公司第四十四研究所 | Light-frequency conversion circuit |
| CN108809080A (en) * | 2017-04-28 | 2018-11-13 | 合肥格易集成电路有限公司 | A kind of biasing circuit, oscillator and charge pump |
| CN108809080B (en) * | 2017-04-28 | 2024-02-20 | 合肥格易集成电路有限公司 | Bias circuit, oscillator and charge pump |
| CN109274375A (en) * | 2018-09-05 | 2019-01-25 | 东南大学 | A kind of voltage control delay unit and High-precision time-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100574099C (en) | 2009-12-23 |
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