CN115412070A

CN115412070A - Comparator with a comparator circuit

Info

Publication number: CN115412070A
Application number: CN202110587217.7A
Authority: CN
Inventors: 谷银川
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2022-11-29

Abstract

The application provides a comparator, includes: an input circuit having an output for generating a differential signal from an input signal and a reference signal during a sampling phase; the positive feedback circuit is connected with the output end of the input circuit and is used for accelerating the difference between the differential signals; and the output circuit is connected with the output end of the input circuit and is used for carrying out amplification processing and latch processing on the voltage signal of the output end of the input circuit in the regeneration stage so as to output a comparison result. According to the scheme, the positive feedback circuit is used for accelerating the difference between the differential signals, and the time of a sampling stage can be shortened when the size of the reference signal is not appropriate, so that the response rate of the comparator is improved, and the power consumption of the comparator is reduced.

Description

Comparator with a comparator circuit

Technical Field

The present application relates to integrated circuits, and more particularly, to a comparator.

Background

Nowadays, the demand of people for mobile devices such as mobile phones, tablet computers and various wearable accessories is greatly increased, which greatly enriches our daily lives and works.

However, since the battery life is limited, a higher requirement is imposed on the power consumption of each component in the mobile device, and a Dynamic Random Access Memory (DRAM) is an indispensable component in the mobile device, so that the DRAM is also required to realize a lower operating voltage and a lower power consumption. The comparator is an important device for realizing data reading and writing of the DRAM, and the working voltage and the energy consumption of the conventional comparator cannot meet the current use requirement.

Disclosure of Invention

The application provides a comparator, which aims to improve the response rate of the comparator and reduce the power consumption of the comparator.

The application provides a comparator, includes:

an input circuit having an output for generating a differential signal from an input signal and a reference signal during a sampling phase;

the positive feedback circuit is connected with the output end of the input circuit and is used for accelerating the difference between the differential signals;

and the output circuit is connected with the output end of the input circuit and is used for carrying out amplification processing and latch processing on the voltage signal of the output end of the input circuit in the regeneration stage so as to output a comparison result.

Optionally, the input circuit is provided with two output terminals, and the positive feedback circuit comprises:

the control end of the first feedback unit is connected with the first output end of the input circuit, and the first end of the first feedback unit is connected with the second output end of the input circuit;

and the control end of the second feedback unit is connected with the second output end of the input circuit, and the first end of the second feedback unit is connected with the first output end of the input circuit.

Optionally, the first feedback unit includes: a first feedback transistor, a control end of which is an input end of the first feedback unit, and a first end of which is an output end of the first feedback unit;

the second feedback unit includes: and a control end of the second feedback transistor is an input end of the second feedback unit, and a first end of the second feedback transistor is an output end of the second feedback unit.

Optionally, the input circuit comprises:

a first input transistor, a control terminal of which is used for receiving an input signal, a first terminal of which is used as a first output terminal of the input circuit, and a second terminal of which is connected with a second terminal of the first feedback transistor;

a second input transistor, a control terminal of which is used for receiving a reference signal, a first terminal of which is used as a second output terminal of the input circuit, and a second terminal of which is connected with a second terminal of the second feedback transistor;

and a control terminal of the third input transistor is used for receiving the clock signal, a first terminal of the third input transistor is connected with the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor and the second terminal of the second feedback transistor, and a second terminal of the third input transistor is connected with a grounding terminal or a power supply terminal.

Optionally, the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are of the same type.

Optionally, when the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are all N-type transistors, a drain of the N-type transistor is a first end, and a gate of the N-type transistor is a control end;

when the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all P-type transistors, the drain of the P-type transistor is a first end, and the gate of the P-type transistor is a control end.

Optionally, the comparator further comprises:

and the first reset circuit is connected between the first output end of the input circuit and the second output end of the input circuit and is used for resetting the voltage of the first output end of the input circuit and the voltage of the second output end of the input circuit.

Optionally, the comparator further comprises:

the second reset circuit is connected to the first output end of the output circuit and is used for resetting the voltage of the first output end of the output circuit;

and the third reset circuit is connected to the second output end of the output circuit and is used for resetting the voltage of the second output end of the output circuit.

Optionally, the first reset circuit comprises:

a first clocked transistor whose control terminal receives a clock signal and whose second terminal is connected to a first output terminal of the input circuit;

and a second clocked transistor whose control terminal receives the clock signal, whose second terminal is connected to the second output terminal of the input circuit, and whose second terminal is connected to the second terminal of the first clocked transistor.

Optionally, the second reset circuit comprises: a third clock transistor, the control end of which receives the clock signal and the second end of which is connected with the first output end of the output circuit;

the third reset circuit includes: and a fourth clocked transistor having a control terminal receiving the clock signal and a second terminal connected to the second output terminal of the output circuit.

Alternatively, the first, second, third, and fourth clocking transistors are of the same type.

Optionally, the output circuit comprises:

a first output transistor, a second end of which is a first input end of the output circuit;

a second output transistor, a second end of which is a second input end of the output circuit;

a control end of the third output transistor is connected with the control end of the first output transistor, the control end of the third output transistor is also connected with a second end of the fourth output transistor, and the second end of the third output transistor is used as a first output end of the output circuit;

and the control end of the fourth output transistor is connected with the control end of the second output transistor, the control end of the fourth output transistor is also connected with the second end of the third output transistor, and the second end of the fourth output transistor is used as the second output end of the output circuit.

Optionally, the first output transistor and the second output transistor are both N-type transistors, a drain of the N-type transistor is a first end, and a gate of the N-type transistor is a control end;

the third output transistor and the fourth output transistor are both P-type transistors, the first clock-controlled transistor to the fourth clock-controlled transistor are all P-type transistors, a source electrode of each P-type transistor is a first end, and a grid electrode of each P-type transistor is a control end.

Optionally, the first input transistor and the second output transistor are both P-type transistors, a drain of the P-type transistor is a first end, and a gate of the P-type transistor is a control end;

the third output transistor and the fourth output transistor are both N-type transistors, the first clock-controlled transistor to the fourth clock-controlled transistor are both N-type transistors, a source electrode of the N-type transistor is a first end, and a grid electrode of the N-type transistor is a control end.

Optionally, the sizes of the first feedback transistor and the second feedback transistor are the same, the sizes of the first input transistor and the second input transistor are the same, and the size of the first feedback transistor is smaller than one half of the size of the first input transistor.

Optionally, the input circuit is provided with two output terminals, and the positive feedback circuit comprises at least one controllable positive feedback module; wherein each controllable positive feedback module comprises:

the control end of the first feedback unit is connected with the first output end of the input circuit through the first switch, and the first end of the first feedback unit is connected with the second output end of the input circuit;

and the control end of the second feedback unit is connected with the second output end of the input circuit through a second switch, and the first end of the second feedback unit is connected with the first output end of the input circuit.

Optionally, the first feedback unit comprises: a first feedback transistor, a control end of which is an input end of the first feedback unit, and a first end of which is an output end of the first feedback unit;

Optionally, the first switch comprises a first transmission gate controlled by a first enable signal generated according to the operating frequency of the comparator, the input common mode range of the comparator and the test mode signal;

the second switch includes a second transmission gate controlled by a second enable signal generated according to an operating frequency of the comparator, an input common mode range of the comparator, and the test mode signal.

Optionally, the control terminal of the first feedback unit is further connected to a ground terminal or a power terminal through a first zero switch; the control end of the second feedback unit is also connected with a grounding end or a power end through a zeroth switch.

The application provides a comparator, this comparator includes input circuit, output circuit and positive feedback circuit, it is improper when the reference signal selection, the time that input signal and reference signal produced the difference signal at input circuit's output is longer, input circuit generates the difference signal according to input signal and reference signal, and accelerate the difference between the difference signal by positive feedback circuit, shorten the time of sampling stage, reduce the delay time that the comparator gets into the regeneration stage, output circuit carries out the output comparison result after amplification processing and latch processing to the voltage signal of input circuit's output in the regeneration stage, thereby promote the response rate of comparator, reduce the consumption of comparator.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Fig. 1 is a specific circuit diagram of a comparator provided in the present application;

FIG. 2 is a timing diagram illustrating operation of a comparator provided herein;

fig. 3 is a block diagram of a comparator according to the present application;

FIG. 4 is a specific circuit diagram of one of the comparators provided in FIG. 3;

FIG. 5 is a graph showing the relationship between the input signal and the delay time of the regeneration phase when the reference signal is small in the comparator shown in FIG. 4;

FIG. 6 is a graph showing the relationship between input signal and power consumption when the reference signal is small for the comparator shown in FIG. 4;

FIG. 7 is a detailed circuit diagram of another comparator based on the circuit provided in FIG. 3;

FIG. 8 is a graph showing the relationship between the input signal and the delay time of the regeneration phase when the reference signal is relatively large in the comparator shown in FIG. 7;

fig. 9 is a block diagram of a comparator according to the present application;

fig. 10 is a specific circuit diagram based on one of the comparators provided in fig. 9;

FIG. 11 is a detailed circuit diagram of a controllable positive feedback module in the comparator provided in FIG. 10;

FIG. 12 is a detailed circuit diagram of another comparator based on that provided in FIG. 9;

fig. 13 is a detailed circuit diagram of a controllable positive feedback module in the comparator provided in fig. 12.

With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

As shown in fig. 1, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3, the transistor N1 and the transistor N2 constitute a differential transistor pair, a gate of the transistor N1 and a gate of the transistor N2 constitute a first input terminal IP and a second input terminal IN of the input circuit, and a drain of the transistor N1 and a drain of the transistor N2 constitute two output terminals of the input circuit.

The output circuit 102 includes a transistor P1, a transistor P2, a transistor N4, and a transistor N5, the four transistors form a cross-coupled transistor pair, drains of the transistor P1 and the transistor N4 form a first output terminal ON of the output circuit 102, and drains of the transistor P2 and the transistor N5 form a second output terminal OP of the output circuit 102. The reset circuit 103 includes a transistor P3 and a transistor P4.

The working process of the comparator is divided into four stages, namely a reset stage, a sampling stage, a regeneration stage and a decision stage. The operation of the comparator shown in fig. 1 is described below with reference to fig. 2:

in the reset phase, i.e. from time t0 to time t1, the clock signal is at low level, the transistor N3 is turned off, the input circuit and the output circuit stop operating, the transistors P3 and P4 are turned on, and the reset circuit operates to pull the voltages of the drain of the transistor N4 and the drain of the transistor N5 to high level.

During the sampling period, i.e. from time t1 to time t2, the clock signal is high, the transistors P3 and P4 are turned off, and the reset circuit stops operating. The transistor N3 is closed, the input circuit collects input signals through the first input end IP, the input circuit collects reference signals through the second input end IN, the input signals pull the drain voltage of the transistor N1 downwards, and the reference signals pull the drain voltage of the transistor N2 downwards. The drain of transistor N1 pulls the drain voltage of transistor N4 down and the drain of transistor N2 pulls the drain voltage of transistor N5 down. Since the input signal is higher than the reference signal, the rate at which the input signal pulls the drain voltage of the transistor N1 is faster, so that the drain voltage of the transistor N4 is lower than the drain voltage of the transistor N5.

During the regeneration phase, i.e. from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the inversion voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually turned off, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

In the decision phase, i.e. from time t3 to time t4, the transistors P2 and N4 are turned on, the transistors P1 and N5 are turned off, the drain voltage of the transistor N5 continues to be pulled up, the drain voltage of the transistor N4 continues to be pulled down, and the drain voltages of the transistors N4 and N5 are maintained after the drain of the transistor N5 is pulled to a low level and the drain voltage of the transistor N4 is pulled to a high level.

At the next duty cycle, the clock signal goes low, and the drain voltages of the transistors N4 and N5 are reset to high by the transistors P1 and P2.

However, when the selection of the reference signal is not appropriate, the time for the input signal and the reference signal to generate the differential signal at the output terminal of the input circuit is relatively long, which results in a reduction in the response rate of the comparator and also increases the power consumption of the comparator. For example, in the comparator shown in fig. 2, when the reference signal is small, the transistors N1 and N2 need to be turned on for a longer time, so that the charging current at the nodes VP and VN decreases, the transistors N1 and N2 pull the transistors N5 and N4 at a lower rate, the response rate of the comparator decreases, and the power consumption of the comparator also increases.

Fig. 3 is a block diagram of a comparator according to the present application, and as shown in fig. 3, the comparator includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104. The input circuit 101 is provided with an output terminal, the positive feedback circuit 104 is connected with the output terminal of the input circuit 101, and the output circuit 102 is connected with the output terminal of the input circuit 101.

The input circuit 101 is used to generate a differential signal from the input signal and the reference signal during the sampling phase. The differential signal is a pair of voltage signals, the positive feedback circuit 104 is used to accelerate the difference between the differential signals, and the input circuit 101 is further used to output the differential signal after accelerated processing. The output circuit 102 is configured to perform amplification processing and latch processing on the voltage signal at the output end of the input circuit 101 in the regeneration stage, and the voltage signal at the output end of the input circuit 101 is output as a comparison result after the amplification processing and the latch processing.

When the reference signal is not properly selected, the response time of the input circuit 101 becomes longer, i.e., the input circuit 101 needs a longer time to present a differential signal at the output terminal. The positive feedback signal accelerates the difference between the differential signals through a positive feedback mechanism, so as to shorten the time that the input circuit 101 presents the differential signals at the output end, that is, the time that the comparator is in a sampling stage is shortened, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

In an embodiment, the input circuit 101 has two output terminals, which are denoted as a first output terminal VN and a second output terminal VP, the positive feedback circuit 104 includes a first feedback unit 1041 and a second feedback unit 1042, and the first feedback unit 1041 and the second feedback unit 1042 both have a control terminal and a first terminal.

A control terminal of the first feedback unit 1041 is connected to the first output terminal VN of the input circuit 101, and a first terminal of the first feedback unit 1041 is connected to the second output terminal VP of the input circuit 101. The control terminal of the second feedback unit 1042 is connected to the second output terminal VP of the input circuit 101, and the first terminal of the second feedback unit 1042 is connected to the first output terminal VN of the input circuit 101.

The first feedback unit 1041 is configured to pull the voltage of the second output terminal VP of the input circuit 101 according to the voltage of the first output terminal VN of the input circuit 101 in the sampling phase, and the second feedback unit 1042 is configured to pull the voltage of the first output terminal VN of the input circuit 101 according to the voltage of the second output terminal VP of the input circuit 101 in the sampling phase.

The direction in which the first feedback unit 1041 pulls the voltage of the second output terminal VP of the input circuit 101 is the same as the direction in which the second feedback unit 1042 pulls the voltage of the first output terminal VN of the input circuit 101. When the first feedback unit 1041 pulls up the voltage of the second output terminal VP of the input circuit 101, the second feedback unit 1042 also pulls up the voltage of the first output terminal VN of the input circuit 101. When the first feedback unit 1041 pulls down the voltage of the second output terminal VP of the input circuit 101, the second feedback unit 1042 also pulls down the voltage of the first output terminal VN of the input circuit 101.

The following description takes the voltages at the two output terminals of the pull-down input circuit 101 as an example: when the voltage of the first output terminal VN of the input circuit 101 is higher than the voltage of the second output terminal VP of the input circuit 101, the voltage capability of the first feedback unit 1041 pulling the second output terminal VP of the input circuit 101 downwards is stronger, and the voltage capability of the second feedback unit 1042 pulling the first output terminal VN of the input circuit 101 downwards is weaker, that is, the voltage drop rate of the first output terminal VN is lower than the drop rate of the second output terminal VP, so that the voltage difference between the first output terminal VN voltage and the second output terminal VP is larger and larger, and forward feedback is realized.

When the voltage of the first output terminal VN of the input circuit 101 is lower than the voltage of the second output terminal VP of the input circuit 101, the capability of the first feedback unit 1041 to pull the voltage of the second output terminal VP of the input circuit 101 downwards is weaker, and the capability of the second feedback unit 1042 to pull the voltage of the first output terminal VN of the input circuit 101 downwards is stronger, that is, the voltage drop rate of the first output terminal VN is higher than that of the second output terminal VP, so that the voltage difference between the first output terminal VN and the second output terminal is larger and larger, and forward feedback is realized.

In the above technical solution, when the selection of the reference signal is not appropriate, the time for the input signal and the reference signal to generate the differential signal at the output end of the input circuit is relatively long, the input circuit 101 generates the differential signal according to the input signal and the reference signal, and the positive feedback circuit 104 accelerates the difference between the differential signals, so as to shorten the time of the sampling stage, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

Fig. 4 is a schematic circuit structure diagram of a comparator according to another embodiment of the present application, and as shown in fig. 4, the comparator provided in the present application includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104.

The input circuit 101 includes a first input transistor 1011, a second input transistor 1012, and a third input transistor 1013. The control terminal of the first input transistor 1011 serves as the first input terminal IP of the input circuit 101, and the first terminal of the first input transistor 1011 serves as the first output terminal VN of the input circuit 101. A control terminal of the second input transistor 1012 serves as the second input terminal IN of the input circuit 101, and a first terminal of the second input transistor 1012 serves as the second output terminal VP of the input circuit 101. A first terminal of the third input transistor 1013 is connected to the second terminal of the first input transistor 1011 and the second terminal of the second input transistor 1012, and a second terminal of the third input transistor 1013 is connected to the ground terminal.

A control terminal of the third input transistor 1013 is configured to receive a clock signal and to control an operating state of the input circuit 101. When the third input transistor 1013 is closed, the input circuit 101 operates. When the third input transistor 1013 is turned off, the input circuit 101 stops operating.

A control terminal of the first input transistor 1011 is configured to receive an input signal, a control terminal of the second input transistor 1012 is configured to receive a reference signal, and after the input signal and the reference signal are amplified by the first input transistor 1011 and the second input transistor 1012, a differential signal is generated at a first terminal of the first input transistor 1011 and a first terminal of the second input transistor 1012.

The output circuit 102 includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023, and a fourth output transistor 1024, which form a cross-coupled circuit. A first terminal of the first output transistor 1021 is connected to a second terminal of the third output transistor 1023, and a first terminal of the second output transistor 1022 is connected to a second terminal of the fourth output transistor 1024. The control terminal of the first output transistor 1021 is connected to the control terminal of the third output transistor 1023, and then to the second terminal of the fourth output transistor 1024. A control terminal of the second output transistor 1022 is connected to a control terminal of the fourth output transistor 1024, and then to a second terminal of the third output transistor 1023.

A second terminal of the first output transistor 1021 is a first input terminal of the output circuit 102, a second terminal of the second output transistor 1022 is a second input terminal of the output circuit 102, the second terminal of the first output transistor 1021 is connected to a first terminal of the first input transistor 1011, and a second terminal of the second output transistor 1022 is connected to a first terminal of the second input transistor 1012. A second terminal of the third output transistor 1023 is used as the first output terminal ON of the output circuit 102, and a second terminal of the fourth output transistor 104 is used as the second output terminal OP of the output circuit 102.

After the first input transistor 1011 and the second input transistor 1012 are turned on, the voltages of the first terminal of the first output transistor 1021 and the first terminal of the second output transistor 1022 are pulled down, and the pair transistors are turned on when the voltages are pulled down to the inversion voltage. That is, the first output transistor 1021 and the fourth output transistor 1024 are turned on, or the second output transistor 1022 and the third output transistor 1023 are turned on. If the first output transistor 1021 and the fourth output transistor 1024 are turned on, the voltage at the second terminal of the fourth output transistor 1024 is pulled up, and the voltage at the second terminal of the third output transistor 1023 is pulled down. If the second output transistor 1022 and the third output transistor 1023 are turned on, the voltage at the second end of the fourth output transistor 1024 is pulled down, and the voltage at the second end of the third output transistor 1023 is pulled up, so that the voltage signal output by the input circuit 101 is amplified and latched.

In an embodiment, the first feedback unit 1041 includes a first feedback transistor 1043, a control terminal of the first feedback transistor 1043 is a control terminal of the first feedback unit 1041, and a first terminal of the first feedback transistor 1043 is a first terminal of the first feedback unit 1041. A control terminal of the first feedback transistor 1043 is connected to a first terminal of the first input transistor 1011, and a first terminal of the first feedback transistor 1043 is connected to a first terminal of the second input transistor 1012. A second terminal of the first feedback transistor 1043 is connected to a second terminal of the first input transistor 1011. The second terminal of the first feedback transistor 1043 is also connected to the first terminal of the third input transistor 1013.

A control terminal of the second feedback transistor 1044 is a control terminal of the second feedback unit 1042, and a first terminal of the second feedback transistor 1044 is a first terminal of the second feedback unit 1042. A control terminal of the second feedback transistor 1044 is connected to the first terminal of the second input transistor 1012, and a first terminal of the second feedback transistor 1044 is connected to the first terminal of the first input transistor 1011. A second terminal of the second feedback transistor 1044 is connected to the second terminal of the second input transistor 1012, and a second terminal of the second feedback transistor 1044 is further connected to the first terminal of the third input transistor 1013.

In one embodiment, the first input transistor 1011 and the second input transistor 1012 are of the same type such that the first input transistor 1011 and the second input transistor 1012 can generate a differential signal from an input signal and a reference signal.

In an embodiment, the types of the first feedback transistor 1043, the second feedback transistor 1044, the first input transistor 1011 and the second input transistor 1012 are the same, the direction in which the first feedback transistor 1043 pulls the voltage of the second output terminal VP of the input circuit 101 is the same as the direction in which the second feedback transistor 1044 pulls the voltage of the first output terminal VN of the input circuit 101, and the direction in which the feedback transistor pulls the voltage of the output terminal of the input circuit is the same as the direction in which the input transistor pulls the voltage of the output terminal of the input circuit, so that positive feedback is achieved.

When the voltage of the first terminal of the first input transistor 1011 is larger, the capability of the first feedback transistor 1043 to pull the voltage of the first terminal of the second input transistor 1012 downwards is larger, and the voltage of the first terminal of the second input transistor 1012 is reduced faster, a positive feedback mechanism is realized, and the difference of the differential voltage between the first input transistor 1011 and the second input transistor 1012 is accelerated.

In an embodiment, the comparator further comprises a first reset circuit 1031, the first reset circuit 1031 is connected between the first output terminal VN of the input circuit 101 and the second output terminal VP of the input circuit 101, and the first reset circuit 1031 is configured to reset the voltage of the first output terminal VN of the input circuit 101 and the voltage of the second output terminal VP of the input circuit 101.

The first reset circuit 1031 includes a first clocking transistor 1032 and a second clocking transistor 1033, a second terminal of the first clocking transistor 1032 is connected to the first output terminal VN of the input circuit 101, a second terminal of the second clocking transistor 1033 is connected to the second output terminal VP of the input circuit 101, and a first terminal of the second clocking transistor 1033 is connected to the first terminal of the first clocking transistor 1032 and the rear power supply.

The control terminals of the first and

second clocking transistors

1032, 1033 are configured to receive a clock signal, and when the clock signal is at a low level, the control terminals are turned on to pull the first and second output terminals VN, VP of the input circuit 101 to a high level.

In one embodiment, the comparator further includes a second reset circuit 1034 and a third reset circuit 1035, the second reset circuit 1034 is connected to the first output terminal of the output circuit, and the third reset circuit is connected to the second output terminal of the output circuit. The second reset circuit 1034 is used to reset the voltage of the first output terminal ON of the output circuit 102. The third reset circuit 1035 is for resetting the voltage of the second output terminal OP of the output circuit.

The second reset circuit 1034 includes a third clocked transistor 1036, and a second terminal of the third clocked transistor 1036 is connected to the first output terminal ON of the output circuit 102. A control terminal of the third clocked transistor 1036 is for receiving the clock signal and for pulling the first output terminal ON of the output circuit 102 to a high level when the clock signal is at a low level.

The third reset circuit 1035 includes a fourth clocked transistor 1037, and a second terminal of the fourth clocked transistor 1037 is connected to the second output terminal OP of the output circuit 102. A control terminal of the fourth clocked transistor 1037 is configured to receive the clock signal, and is configured to pull the second output terminal OP of the output circuit 102 to a high level when the clock signal is at a low level.

Compared with the second reset circuit and the third reset circuit which realize reset by pulling the voltages of the two output ends of the input circuit through the output circuit, the first reset circuit is arranged to directly pull the voltages of the two output ends of the input circuit 101 to realize reset, the reset time is shorter, and the response rate of the comparator is improved.

In one embodiment, the first, second, third, and

fourth clocking transistors

1032, 1033, 1036, 1037 are of the same type to enable pulling the two outputs of the input circuit and the two outputs of the output circuit to the same level.

In one embodiment, when the first feedback transistor 1043, the second feedback transistor 1044, the first input transistor 1011, and the second input transistor 1012 are all N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

In one embodiment, when the first output transistor 1021 and the second output transistor 1022 are both N-type transistors, the drain of the N-type transistor is a first terminal, and the gate of the N-type transistor is a control terminal;

when the third output transistor 1023 and the fourth output transistor 1024 are both P-type transistors, and the first clocked transistor 1032 to the fourth clocked transistor 1037 are both P-type transistors, the source of the P-type transistor is a first terminal, and the gate of the P-type transistor is a control terminal.

In one embodiment, the first feedback transistor 1043 and the second feedback transistor 1044 are the same in size, the first input transistor 1011 and the second input transistor 1012 are the same in size, and the size of the first feedback transistor 1043 is smaller than one-half of the size of the first input transistor 1011. The first feedback transistor and the second feedback transistor are prevented from influencing the sensing input signal and the reference signal of the first input transistor and the second input transistor, and therefore the accuracy of the output result of the comparator is improved.

The operation of the comparator shown in fig. 4 is described below in connection with four operating phases of the comparator:

in the reset stage, the clock signal is at a low level, the third input transistor N3 is turned off, the input circuit 101 and the output circuit 102 stop operating, the first clocked transistor P5 and the second clocked transistor P6 are turned ON, the first reset circuit 1031 operates, and the voltages of the first output terminal ON and the second output terminal OP of the input circuit are pulled up to a high level. The third clocked transistor P3 and the fourth clocked transistor P4 are closed, and the second reset circuit 1034 and the third reset circuit 1035 operate to pull the drain voltages of the third output transistor P1 and the fourth output transistor P2 to the high level.

In the sampling phase, the clock signal is at a high level, the first to fourth clocking transistors P5 to P4 are turned off, and the first to third reset circuits 1031 to 1035 stop operating. The third input transistor N3 is closed, the input circuit collects an input signal through the first input terminal IP, the input circuit collects a reference signal through the second input terminal IN, the input signal pulls the drain voltage of the first input transistor N1 downward, and the reference signal pulls the drain voltage of the second input transistor N2 downward. The drain of the first input transistor N1 pulls down the drain voltage of the first output transistor N4, and the drain of the second input transistor N2 pulls down the drain voltage of the second output transistor N5.

When the reference signal is small, for example: the reference signal and the input signal are both less than 0.7V, and the first input transistor N1 and the second input transistor N2 both need to be turned on for a long time, that is, the pulling rate of the voltages at the two output ends of the input circuit is slow, and the time for generating the differential signal at the two output ends of the input circuit is long.

When there is a slight voltage difference between the two outputs of the input circuit, for example: when the input signal is smaller than the reference signal, the voltage of the first output end of the input circuit is slightly higher than the voltage of the second output end of the input circuit, so that the capability of the first feedback transistor N6 for pulling the voltage of the second output end of the input circuit downwards is higher than the capability of the second feedback transistor N7 for pulling the voltage of the first output end of the input circuit downwards, namely the voltage drop rate of the first output end of the input circuit is smaller than the voltage drop rate of the second output end of the input circuit, the voltage difference of the two output ends is further amplified through the two feedback transistors, a differential circuit is presented on the two output ends of the input circuit, the time of the comparator in a sampling stage is shortened, the response rate of the comparator is improved, and the power consumption of the comparator is reduced.

In the regeneration stage, due to the pull-down action of the first input transistor N1 and the second input transistor N2, the drain voltage of the first output transistor N4 and the drain voltage of the second output transistor N5 reach the inversion voltage, when the drain voltage of the first input transistor N1 is higher than the drain voltage of the second input transistor N2, the first output transistor N4 and the fourth output transistor P2 are gradually turned off, the second output transistor P1 and the third output transistor N5 are gradually turned on, the capability of pulling down the drain voltage of the fourth output transistor P2 is increasingly stronger, and the capability of pulling up the drain voltage of the third output transistor P1 is increasingly stronger.

In the decision phase, the first output transistor N4 and the fourth output transistor P2 are turned off, the second output transistor P1 and the third output transistor N5 are turned on, the drain voltage of the fourth output transistor P2 is pulled down, the drain voltage of the third output transistor P1 is pulled up, and the drain voltages of the third output transistor P1 and the fourth output transistor P2 are maintained after the drain of the fourth output transistor P2 is pulled to a high level and the drain voltage of the third output transistor P1 is pulled to a low level.

At the next duty cycle, the clock signal goes low, and the drain voltages of the third output transistor P1 and the fourth output transistor P2 are reset to high by the third clocked transistor P3 and the fourth clocked transistor P4.

As shown in fig. 5, the dotted line represents the relationship between the input signal and the delay time in the regeneration stage when the reference signal is small in the comparator shown in fig. 1, and the solid line represents the relationship between the input signal and the delay time in the regeneration stage when the reference signal is small in the comparator shown in fig. 4. As can be seen from fig. 5, the comparator shown in fig. 1 is used when both the input signal and the reference signal are small, for example: the common mode input voltage is 0.5V, when the input signal is 0.1V and the reference signal is 0.5V, the delay time of the regeneration stage can reach 100 picoseconds. The comparator of fig. 4 reduces the delay of the regeneration phase to 80 picoseconds when the input signal is 0.1V and the reference signal is 0.5V.

As shown in fig. 6, the dotted line represents the relationship between the input signal and the power consumption of the comparator shown in fig. 1 when the reference signal is small, and the solid line represents the relationship between the input signal and the power consumption of the comparator shown in fig. 4 when the reference signal is small. As can be seen from fig. 6, the comparator shown in fig. 1 is used when both the input signal and the reference signal are small, for example: the common mode input voltage is 0.5V, when the input signal is 0.1V and the reference signal is 0.5V, the current reaches 730 microamperes. The comparator shown in fig. 4 reduces the current to below 690 microamps when the common mode input voltage is 0.5V, the input signal is 0.1V, and the reference signal is 0.5V.

In the technical scheme, the input circuit uses the N-type transistor, if the reference signal is small, the first feedback transistor and the second feedback transistor can pull the voltage of the output end at different rates when the reference signal and the input signal can only generate a small voltage difference at the output end of the input circuit in a short time, and the difference between the differential signals at the output end is accelerated, so that the time of the comparator in a sampling stage is shortened, and the power consumption of the comparator is reduced. In addition, the first reset circuit directly pulls the voltage of the output end of the input circuit to reset, so that the reset time of the output end of the input circuit can be shortened, and the response rate of the comparator is improved.

Fig. 7 is a specific circuit diagram of a comparator according to the present application, where the comparator includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104.

The input circuit 101 includes a first input transistor 1011, a second input transistor 1012 and a third input transistor 1013, and the connection relationship between the first input transistor 1011 and the third input transistor 1013 is the same as that in the embodiment shown in fig. 4, and is not described again here.

When the first to third input transistors 1011 to 1013 are P-type transistors, the drain of the P-type transistor is a first terminal, the source of the P-type transistor is a second terminal, and the gate of the P-type transistor is a control terminal. The second terminal of the third input transistor is connected with the power supply terminal.

The output circuit includes a first output transistor 1021, a second output transistor 1022, a third output transistor 1023, and a fourth output transistor 1024. The connection relationship between the first output transistor 1021 and the fourth input transistor 1024 is the same as that of the embodiment shown in fig. 4, and is not repeated here.

When the first output transistor 1021 and the second output transistor 1023 are P-type transistors, the drain of the P-type transistor is the first terminal and the gate of the P-type transistor is the control terminal. When the third output transistor 1023 and the fourth output transistor 1024 are N-type transistors, the drain of the N-type transistor is the second terminal and the gate of the N-type transistor is the control terminal.

The positive feedback circuit 104 includes a first feedback unit 1041 and a second feedback unit 1042, and the connection relationship between the first feedback unit 1041 and the second feedback unit 1042 is the same as that in fig. 4, and is not described herein again. The first feedback unit 1041 includes a first feedback transistor 1043, and the second feedback unit 1042 includes a second feedback transistor 1044. The connection relationship between the first feedback transistor 1043 and the second feedback transistor 1044 is the same as that in fig. 4, and is not described herein again.

When the first feedback transistor 1043 and the second feedback transistor 1044 are P-type transistors, the drain of the P-type transistor is a first terminal, and the gate of the P-type transistor is a control terminal.

The connection relationship among the transistors in the input circuit, the transistors in the output circuit, and the transistors in the positive feedback circuit has been described in detail in the embodiment shown in fig. 4, and is not described again here.

The comparator further includes a first reset circuit 1031, a second reset circuit 1032, and a third reset circuit 1033. The first reset circuit 1031 includes a first clocking transistor 1032 and a second clocking transistor 1033. The connection relationship between the first clocked transistor 1032 and the second clocked transistor 1033 is the same as that in fig. 4, and is not described again.

The second reset circuit 1034 includes a third clocked transistor 1036, which is connected to the output circuit in the same manner as in fig. 4, and is not described herein again. The third reset circuit 1035 includes a fourth clocked transistor 1037, and the connection relationship between the fourth clocked transistor and the transistors in the output circuit is the same as that in fig. 4, and is not described herein again.

It should be noted that, when the first clocked transistor 1032 to the fourth clocked transistor 1034 are N-type transistors, the drain of the N-type transistor is the second terminal, the gate of the N-type transistor is the control terminal, the source of the N-type transistor is the first terminal, and the source of the N-type transistor is the ground terminal.

in the reset stage, the clock signal is at a low level, the control terminal of the third input transistor P3 is at a high level, the third input transistor is turned off, the input circuit 101 and the output circuit 102 stop operating, the control terminals of the first clocked transistor N5 and the second clocked transistor N6 are at a high level, the first clocked transistor N5 and the second clocked transistor N6 are turned ON, the first reset circuit 1031 operates, and the voltages of the first output terminal ON and the second output terminal OP of the input circuit are pulled up to a low level. The control terminals of the third clocked transistor N3 and the fourth clocked transistor N4 are also at a high level, the third clocked transistor N3 and the fourth clocked transistor N4 are turned on, and the second reset circuit 1034 and the third reset circuit 1035 operate to pull the voltages of the drain of the third output transistor N1 and the drain of the fourth output transistor N2 to a low level.

In the sampling phase, the clock signal is at a high level, the control terminals of the first to fourth clocked transistors N5 to N4 are at a low level, the first to fourth clocked transistors N5 to N4 are turned off, and the first to third reset circuits 1031 to 1035 stop operating. The control terminal of the third input transistor P3 is at a low level, the third input transistor P3 is closed, the input circuit 101 collects an input signal through the first input terminal IP, the input circuit 101 collects a reference signal through the second input terminal IN, the input signal pulls the drain voltage of the first input transistor P1 upward, and the reference signal pulls the drain voltage of the second input transistor P2 upward. The drain of the first input transistor P1 pulls the drain voltage of the first output transistor P4 up, and the drain of the second input transistor P2 pulls the drain voltage of the second output transistor P5 up.

When the reference signal is relatively large, for example: the reference signal and the input signal are both greater than 0.3V, and the first input transistor P1 and the second input transistor P2 both need to be turned on for a long time, that is, the pulling rate of the voltages of the two output ends of the input circuit is slow, and the time for generating the differential signal at the two output ends of the input circuit is long.

When there is a slight voltage difference between the two outputs of the input circuit, for example: when the input signal is smaller than the reference signal, the voltage of the first output end of the input circuit is slightly higher than the voltage of the second output end of the input circuit, so that the capability of the first feedback transistor P6 for pulling the voltage of the second output end of the input circuit upwards is smaller than the capability of the second feedback transistor P7 for pulling the voltage of the first output end of the input circuit upwards, namely the voltage rising rate of the first output end of the input circuit is higher than the voltage falling rate of the second output end of the input circuit, the voltage difference of the two output ends is further amplified through the two feedback transistors, a differential circuit is presented on the two output ends of the input circuit, the time of the comparator in a sampling stage is shortened, the response rate of the comparator is improved, and the power consumption of the comparator is reduced.

In the regeneration stage, due to the pull-up action of the first input transistor P1 and the second input transistor P2, the drain voltage of the first output transistor P4 and the drain voltage of the second output transistor P5 reach the inversion voltage, when the drain voltage of the first input transistor P1 is higher than the drain voltage of the second input transistor P2, the first output transistor P4 and the fourth output transistor N2 are closed, the second output transistor N1 and the third output transistor P5 are opened, the drain voltage of the fourth output transistor N2 is pulled down, and the drain voltage of the third output transistor N1 is pulled up.

In the decision phase, the first output transistor P4 and the fourth output transistor N2 are closed, the second output transistor N1 and the third output transistor P5 are opened, the drain voltage of the fourth output transistor N2 is pulled down, the drain voltage of the third output transistor N1 is pulled up, and the drain voltages of the third output transistor N1 and the fourth output transistor N2 are maintained after the drain of the third output transistor N1 is pulled to a high level and the drain voltage of the fourth output transistor N2 is pulled to a low level.

At the next duty cycle, the clock signal becomes low level, and the drain voltages of the third output transistor N1 and the fourth output transistor N2 are reset to low level by the third clocking transistor N3 and the fourth clocking transistor N4.

As shown in fig. 8, the dotted line represents the relationship between the input signal and the delay time of the regeneration stage when the reference signal is relatively large in the comparator shown in fig. 1, and the solid line represents the relationship between the input signal and the delay time of the regeneration stage when the reference signal is relatively large in the comparator shown in fig. 7. As can be seen from fig. 8, when both the input signal and the reference signal are relatively large, the comparator shown in fig. 1 is, for example: the input common mode voltage is 0.8V, when the input signal is 0.6V, and the reference signal is 0.8V, the delay time of the regeneration stage can reach 110 picoseconds. Fig. 7 shows that the delay in the regeneration phase is reduced to less than 80 picoseconds when the input common mode voltage is 0.8V, the comparator input signal is 0.6V, and the reference signal is 0.8V.

In the above embodiment, the input circuit uses the P-type transistor, if the reference signal is large, the reference signal and the input signal can only generate a small voltage difference at the output end of the input circuit in a short time, the first feedback transistor and the second feedback transistor pull the voltage at the output end at different rates, and the difference between the differential signals at the output end is accelerated, so that the time of the comparator in the sampling stage is shortened, and the power consumption of the comparator is reduced. In addition, the first reset circuit directly pulls the voltage of the output end of the input circuit to reset, so that the reset time of the output end of the input circuit can be shortened, and the response rate of the comparator is improved.

Fig. 9 is a block diagram of a comparator according to the present application, and as shown in fig. 9, the comparator includes an input circuit 101, an output circuit 102, and a positive feedback circuit 104.

The input circuit 101 has two output terminals, which are denoted as a first output terminal VN and a second output terminal VP, and the positive feedback circuit 104 includes at least one controllable positive feedback module 1040, where each feedback unit includes a first feedback unit 1041, a second feedback unit 1042, a first switch 1043, and a second switch 1044. The first feedback unit 1041 and the second feedback unit 1042 are both provided with a control end and a first end.

A control end of the first feedback unit 1041 is connected to the first output end VN of the input circuit 101 through the first switch 1043, and a first end of the first feedback unit 1041 is connected to the second output end VP of the input circuit 101. The control terminal of the second feedback unit 1042 is connected to the second output terminal VP of the input circuit 101 through the second switch 1044, and the first terminal of the second feedback unit 1042 is connected to the first output terminal VN of the input circuit 101.

The first switch 1043 is used to control whether the first feedback unit 1041 generates positive feedback, and the second switch 1044 is used to control whether the second feedback unit 1042 generates positive feedback. By controlling the on and off of the first switch 1043 and the second switch 1044, it can be controlled whether the controllable positive feedback module 1040 generates positive feedback. When the first switch 1043 and the second switch 1044 are both closed, the controllable positive feedback module 1040 may accelerate the difference between the differential signals at the output terminals of the input circuit through a positive feedback mechanism. When the first switch 1043 and the second switch 1044 are both turned off, the controllable positive feedback module 1040 is turned off from the input circuit, and a positive feedback mechanism cannot be generated at the output end of the input circuit.

When the comparator works, the quantity of the controllable positive feedback modules generating positive feedback can be controlled, and the capacity of the positive feedback circuit for pulling the difference value between the differential signals is further controlled. Therefore, on one hand, the time of the comparator in the sampling phase is controlled, and the response rate of the comparator is guaranteed. On the other hand, the capability of the positive feedback circuit for pulling the voltage of the output end of the input circuit and the capability of the input signal and the reference signal for pulling the voltage of the output end of the input circuit can be balanced, and the comparator can accurately output a comparison result according to the input signal and the reference signal.

Fig. 10 and 11 are specific circuit diagrams based on the comparator shown in fig. 9, wherein the structures of the input circuit 101 and the output circuit 102 are the same as the comparator shown in fig. 4, and are not repeated here. The comparator further includes a first reset circuit 1031, a second reset circuit 1034, and a third reset circuit 1035. The three reset circuits have also been described in detail in the embodiment shown in fig. 4, and are not described again here.

The specific circuit structure of each controllable positive feedback module in the positive feedback circuit is described below with reference to fig. 11. The first feedback unit 1041 includes a first feedback transistor 1043, a control terminal of the first feedback transistor 1043 serves as an input terminal of the first feedback unit 1041, and a first terminal of the first feedback transistor 1043 serves as an output terminal of the first feedback unit 1041.

A control terminal of the first feedback transistor 1043 is connected to a first terminal of the first input transistor 1011 via a first switch 1045. The first switch 1045 includes a first transmission gate G1, the first transmission gate G1 is controlled by a first enable signal EN1, and the first enable signal EN1 is generated according to an operating frequency of the comparator, an input common mode range of the comparator, and the test mode signal.

The second feedback unit 1042 includes a first feedback transistor 1044, a control terminal of the second feedback transistor 1044 is an input terminal of the second feedback unit 1042, and a first terminal of the second feedback transistor 1044 is an output terminal of the second feedback unit 1042.

A control terminal of the second feedback transistor 1044 is connected to the first terminal of the second input transistor 1012 through a second switch 1046. The second switch 1046 includes a second transmission gate G2, the second transmission gate G2 is controlled by a second enable signal EN2, and the second enable signal EN2 is generated according to the operating frequency of the comparator, the input common mode range of the comparator, and the test mode signal.

The on-off states of the first transmission gate G1 and the second transmission gate G2 are controlled by the enable signal, so as to control whether the first feedback transistor 1043 and the second feedback transistor 1044 provide a positive feedback mechanism, and thus the number of controllable positive feedback modules participating in positive feedback can be adjusted.

In an embodiment, the positive feedback circuit further includes a first zero switch 1047 and a zero-th switch 1048, the control terminal of the first feedback unit 1041 is further connected to the ground terminal through the first zero switch 1047, and the first zero switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, so that the transistor in the first feedback unit 1041 does not float, and interference of external interference on the comparator is reduced. The control terminal of the second feedback unit 1042 is further connected to the ground terminal through a zero-th switch 1048, and the first zero switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, so that the transistor in the second feedback unit 1042 does not float, and interference of external interference on the comparator is reduced.

In one embodiment, if the first feedback transistor 1043, the second feedback transistor 1044, the first zero switch 1047 and the zero-th zero switch 1048 are N-type transistors, the drain of the N-type transistor is a first terminal, the source of the N-type transistor is a second terminal, and the gate of the N-type transistor is a control terminal. The first terminal of the first zero switch 1047 is connected to the control terminal of the first feedback transistor 1043, the first terminal of the zero-th switch 1048 is connected to the control terminal of the second feedback transistor 1044, and the second terminals of the first zero switch 1047 and the zero-th switch 1048 are connected to ground, so as to pull down the first feedback transistor 1043 to a low level when the first transmission gate G1 is turned off and pull down the second feedback transistor 1044 to a low level when the second transmission gate G2 is turned off.

Fig. 12 and 13 are specific circuit diagrams based on the comparator shown in fig. 9, wherein the structures of the input circuit 101 and the output circuit 102 are the same as the comparator shown in fig. 7, and are not repeated here. The connection relationship among the first feedback unit, the second feedback unit, the first switch, and the second switch of each controllable module in the forward feedback circuit has already been described in the description of the structure of fig. 11, and is not repeated here.

Here, if the first feedback transistor and the second feedback transistor are P-type transistors, the drain of the P-type transistor is a first terminal, the source of the P-type transistor is a second terminal, and the gate of the P-type transistor is a control terminal.

In an embodiment, the positive feedback circuit further includes a first zero switch 1047 and a zero-th zero switch 1048, the control terminal of the first feedback unit 1041 is further connected to the power supply terminal through the first zero switch 1047, and the first zero switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, so that the transistor in the first feedback unit 1041 does not float, and interference of external interference on the comparator is reduced. The control terminal of the second feedback unit 1042 is further connected to a power supply terminal through a zero-th switch 1048, and the first zero switch 1047 is configured to be turned on when the first transmission gate G1 is turned off, so that the transistor in the second feedback unit 1042 does not float, and interference of external interference on the comparator is reduced.

The first zero switch 1047 and the zero-th switch 1048 are also P-type transistors, a first end of the first zero switch 1047 is connected to a control end of the first feedback transistor, a first end of the zero-th switch 1048 is connected to control of the second feedback transistor, and second ends of the first zero switch 1047 and the zero-th switch 1048 are connected to power supply ends, so that the first feedback transistor 1043 is pulled up to a high level when the first transmission gate G1 is closed, and the second feedback transistor 1044 is pulled up to a high level when the second transmission gate G2 is closed.

In the above embodiment, the positive feedback circuit includes a plurality of controllable positive feedback modules, and the capability of the positive feedback circuit to pull the voltages of the two output ends of the input circuit is adjusted by controlling the number of the controllable positive feedback modules providing the positive feedback mechanism, so as to control the time of the comparator in the sampling stage, balance the pulling capability of the positive feedback circuit, the input signal and the reference signal to the output end of the input circuit, and improve the response rate and accuracy of the comparator.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A comparator, comprising:

and the output circuit is connected with the output end of the input circuit and is used for carrying out amplification processing and latch processing on the voltage signal of the output end of the input circuit in a regeneration stage so as to output a comparison result.

2. The comparator of claim 1, wherein the input circuit has two output terminals, and wherein the positive feedback circuit comprises:

a first feedback unit, a control end of which is connected with a first output end of the input circuit, and a first end of which is connected with a second output end of the input circuit;

3. The comparator of claim 2, wherein:

the first feedback unit includes: a first feedback transistor, a control terminal of which is an input terminal of the first feedback unit, and a first terminal of which is an output terminal of the first feedback unit;

4. The comparator of claim 3, wherein the input circuit comprises:

a first input transistor, a control terminal of which is used for receiving the input signal, a first terminal of which is used as a first output terminal of the input circuit, and a second terminal of which is connected with a second terminal of the first feedback transistor;

a second input transistor, a control terminal of which is used for receiving the reference signal, a first terminal of which is used as a second output terminal of the input circuit, and a second terminal of which is connected with a second terminal of the second feedback transistor;

and a control terminal of the third input transistor is used for receiving a clock signal, a first terminal of the third input transistor is connected with the second terminal of the first input transistor, the second terminal of the second input transistor, the second terminal of the first feedback transistor and the second terminal of the second feedback transistor, and a second terminal of the third input transistor is connected with a ground terminal or a power supply terminal.

5. The comparator of claim 4, wherein the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are of the same type.

6. The comparator of claim 5, wherein:

when the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all N-type transistors, the drain electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end;

7. The comparator according to claim 1, further comprising:

8. The comparator of claim 7, further comprising:

9. The comparator of claim 8, wherein the first reset circuit comprises:

and a second clocked transistor having a control terminal receiving the clock signal, a second terminal connected to the second output terminal of the input circuit, and a first terminal connected to the first terminal of the first clocked transistor.

10. The comparator of claim 9, wherein:

the second reset circuit includes: a third clock transistor, the control end of which receives the clock signal, and the second end of which is connected with the first output end of the output circuit;

11. The comparator according to claim 8 or 10, wherein the first clocked transistor, the second clocked transistor, the third clocked transistor, and the fourth clocked transistor are of the same type.

12. The comparator of claim 1, wherein the output circuit comprises:

a second output transistor, a second terminal of which is a second input terminal of the output circuit;

a third output transistor, a control end of which is connected with the control end of the first output transistor, and a control end of which is also connected with a second end of a fourth output transistor, wherein the second end of the third output transistor is used as a first output end of the output circuit;

13. The comparator of claim 12, wherein:

the first output transistor and the second output transistor are both N-type transistors, the drain electrode of each N-type transistor is a first end, and the grid electrode of each N-type transistor is a control end;

14. The comparator of claim 12, wherein:

the first input transistor and the second output transistor are both P-type transistors, the drain electrode of each P-type transistor is a first end, and the grid electrode of each P-type transistor is a control end;

the third output transistor and the fourth output transistor are both N-type transistors, the first clock-controlled transistor to the fourth clock-controlled transistor are both N-type transistors, a source electrode of each N-type transistor is a first end, and a grid electrode of each N-type transistor is a control end.

15. The comparator of claim 5, wherein the first feedback transistor and the second feedback transistor are the same size, the first input transistor and the second input transistor are the same size, and the first feedback transistor is smaller than one-half of the first input transistor size.

16. The comparator according to claim 1, wherein the input circuit is provided with two output terminals, and the positive feedback circuit comprises at least one controllable positive feedback module; wherein each controllable positive feedback module comprises:

a first feedback unit, wherein the control end of the first feedback unit is connected with the first output end of the input circuit through a first switch, and the first end of the first feedback unit is connected with the second output end of the input circuit;

17. The comparator of claim 16, wherein:

the second feedback unit includes: and the control end of the second feedback transistor is the input end of the second feedback unit, and the first end of the second feedback transistor is the output end of the second feedback unit.

18. The comparator of claim 16, wherein:

the first switch comprises a first transmission gate controlled by a first enable signal generated according to the operating frequency of the comparator, the input common mode range of the comparator and a test mode signal;

the second switch includes a second transmission gate controlled by a second enable signal generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

19. The comparator as claimed in claim 16, wherein the control terminal of the first feedback unit is further connected to a ground terminal or a power terminal through a first zero switch; the control end of the second feedback unit is also connected with a grounding end or a power end through a zeroth switch.