CN115412068A

CN115412068A - Comparator and decision feedback equalization circuit

Info

Publication number: CN115412068A
Application number: CN202110584491.9A
Authority: CN
Inventors: 谷银川
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2022-11-29

Abstract

The application provides a comparator and decision feedback equalizer circuit, the comparator includes: the first-stage main circuit is connected with a power supply end and a grounding end, is provided with a first pair of transistors and a second pair of transistors which are different in type, is used for receiving a first input signal and a first reference signal, and is also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage; the first-stage auxiliary circuit is connected with a power supply end or a grounding end, is provided with a third pair of transistors and a fourth pair of transistors which are different in type, is used for receiving a second input signal and a second reference signal, and is also used for generating a second differential signal according to the second input signal and the second reference signal; and the second-stage circuit is used for amplifying and latching the voltage signal at the output end of the first-stage main circuit and the voltage signal at the output end of the first-stage auxiliary circuit in a regeneration stage so as to output a comparison result. The comparator provided by the application can eliminate intersymbol interference, enlarge the range of the reference signal and has lower working voltage.

Description

Comparator and decision feedback equalization circuit

Technical Field

The present disclosure relates to integrated circuits, and more particularly, to a comparator and a decision feedback equalizer circuit.

Background

Nowadays, the demand of people for mobile devices such as mobile phones, tablet computers and various wearable accessories is greatly increased, which greatly enriches our daily lives and works.

However, since the battery life is limited, a higher requirement is imposed on the power consumption of each component in the mobile device, and a Dynamic Random Access Memory (DRAM) is an indispensable component in the mobile device, so that the DRAM is also required to realize a lower operating voltage and a lower power consumption. The comparator is an important device for realizing data reading and writing of the DRAM, and the existing comparator cannot meet the current use requirement.

Disclosure of Invention

The application provides a comparator and a decision feedback equalization circuit, aiming at eliminating intersymbol interference of the comparator, reducing the working voltage of the comparator and expanding the range of a reference signal of the comparator.

In a first aspect, the present application provides a comparator comprising:

the first-stage main circuit is connected with a power supply end and a grounding end and is provided with a first pair of transistors and a second pair of transistors, the types of the first pair of transistors and the second pair of transistors are different, the first pair of transistors and the second pair of transistors are used for receiving a first input signal and a first reference signal and are also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage;

the first-stage auxiliary circuit is connected with a power supply end or a grounding end and is provided with a third pair of transistors and a fourth pair of transistors, the types of the third pair of transistors and the fourth pair of transistors are different, the third pair of transistors and the fourth pair of transistors are used for receiving a second input signal and a second reference signal and are also used for generating a second differential signal according to the second input signal and the second reference signal in a sampling stage;

and the second-stage circuit is connected with the first-stage main circuit and is used for amplifying and latching the voltage signal at the output end of the first-stage main circuit and the voltage signal at the output end of the first-stage auxiliary circuit in a regeneration stage so as to output a comparison result.

In a second aspect, the present application provides a decision feedback equalization circuit, including four comparators related to the first aspect and the alternative, which are sequentially labeled as a first comparator, a second comparator, a third comparator, and a fourth comparator;

a first comparator having a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the fourth comparator, and a fourth input terminal connected to the second output terminal of the fourth comparator;

a second comparator having a first input terminal for receiving a first input signal, a second input terminal for receiving a first reference signal, a third input terminal connected to the first output terminal of the first comparator, and a fourth input terminal connected to the second output terminal of the first comparator;

a third comparator, a first input terminal of which is used for receiving the first input signal, a second input terminal of which is used for receiving the first reference signal, a third input terminal of which is connected with the first output terminal of the second comparator, and a fourth input terminal of which is connected with the second output terminal of the second comparator;

a fourth comparator having a first input for receiving the first input signal, a second input for receiving the first reference signal, a third input connected to the first output of the third comparator, and a fourth input connected to the second output of the third comparator.

The application provides a comparator decision feedback equalization circuit, wherein the comparator comprises a first-stage main circuit, a first-stage auxiliary circuit and a second-stage circuit. The first-stage main circuit is provided with a first pair of transistors and a second pair of transistors and is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, and because the first pair of transistors and the second pair of transistors are different in type, namely the pulling capacities of the first pair of transistors and the second pair of transistors on voltage are opposite, when the first input signal and the first reference signal enable the pulling capacities of the first pair of transistors and the second pair of transistors on voltage to be unbalanced, even if the difference between the first input signal and the first reference signal is very small, two groups of transistors can also sense accurately, and therefore the sensing precision of the comparator is improved. Because the first stage circuit includes two sets of geminate transistors with different types, when the value range of the first reference signal is wider, for example: the voltage can be changed from 0.3V to 0.9V, and differential signals can be generated in two groups of pair transistors, so that the working range of the comparator is expanded. The main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, the auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage, and the second-stage circuit is used for amplifying and latching the first differential signal and the second differential signal in a regeneration stage so as to output a comparison result. When intersymbol interference occurs to enable the first-stage main circuit to be incapable of accurately sensing and outputting the differential signal, the second differential signal output by the first-stage auxiliary circuit can adjust the first differential signal, so that intersymbol interference is eliminated, and the accuracy of the comparator is improved. Through the two-stage circuit arrangement, namely the first-stage circuit generates a differential signal, and the second-stage circuit generates a comparison result according to the differential signal, the number of transistors in the same circuit path can be reduced, and therefore the working voltage of the comparator is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.

Fig. 1 is a specific circuit diagram of a comparator provided in the present application;

FIG. 2 is a timing diagram illustrating operation of a comparator provided herein;

fig. 3 is a block diagram of a comparator according to the present application;

FIG. 4 is a specific circuit diagram based on the comparator provided in FIG. 3;

FIG. 5 is another specific circuit diagram based on the comparator provided in FIG. 3;

fig. 6 is a block diagram of a decision feedback equalizer circuit according to the present application;

fig. 7 is a schematic diagram illustrating an effect of a decision feedback equalization circuit provided in the present application;

fig. 8 is an operation timing diagram of the decision feedback equalization circuit provided in the present application.

Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

As shown in fig. 1, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3, the transistor N1 and the transistor N2 constitute a differential transistor pair, a gate of the transistor N1 and a gate of the transistor N2 constitute a first input terminal IN and a second input terminal IN of the input circuit, and a drain of the transistor N1 and a drain of the transistor N2 constitute two output terminals of the input circuit.

The output circuit 102 includes a transistor P1, a transistor P2, a transistor N4, and a transistor N5, the four transistors form a cross-coupled transistor pair, drains of the transistor P1 and the transistor N4 form a first output terminal ON of the output circuit 102, and drains of the transistor P2 and the transistor N5 form a second output terminal OP of the output circuit 102. The reset circuit 103 includes a transistor P3 and a transistor P4.

The working process of the comparator is divided into four stages, namely a reset stage, a sampling stage, a regeneration stage and a decision stage. The operation of the comparator shown in fig. 1 is described below with reference to fig. 2:

in the reset phase, i.e. from time t0 to time t1, the clock signal is at low level, the transistor N3 is turned off, the input circuit and the output circuit stop operating, the transistors P3 and P4 are turned on, and the reset circuit operates to pull the drain voltages of the transistor N4 and the transistor N5 to high level.

During the sampling period, i.e. from time t1 to time t2, the clock signal is high, the transistors P3 and P4 are turned off, and the reset circuit stops operating. The transistor N3 is closed, the input circuit collects input signals through the first input end IN, the input circuit collects reference signals through the second input end IN, the input signals pull the drain voltage of the transistor N1 downwards, and the reference signals pull the drain voltage of the transistor N2 downwards. The drain of transistor N1 pulls the drain voltage of transistor N4 down and the drain of transistor N2 pulls the drain voltage of transistor N5 down. Since the input signal is higher than the reference signal, the rate at which the input signal pulls the drain voltage of the transistor N1 is faster, so that the drain voltage of the transistor N4 is lower than the drain voltage of the transistor N5.

During the regeneration phase, i.e. from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the inversion voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually turned off, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

In the decision phase, i.e. from time t3 to time t4, the transistors P2 and N4 are turned on, the transistors P1 and N5 are turned off, the drain voltage of the transistor N5 continues to be pulled up, the drain voltage of the transistor N4 continues to be pulled down, and the drain voltages of the transistors N4 and N5 are maintained after the drain of the transistor N5 is pulled to a low level and the drain voltage of the transistor N4 is pulled to a high level.

At the next duty cycle, the clock signal goes low, and the drain voltages of the transistors N4 and N5 are reset to high by the transistors P1 and P2.

As shown in fig. 3, an embodiment of the present application provides a comparator, which includes a first primary circuit 201, a first secondary circuit 202, and a second secondary circuit 203. Wherein, first order circuit 201 and first order auxiliary circuit 202 all are equipped with the output, and second level circuit 203 is equipped with the input. The output terminal of the first stage circuit 201 is connected to the output terminal of the first stage auxiliary circuit 202, and then connected to the input terminal of the second stage circuit 203.

The first-stage main circuit 201 connects a power supply terminal and a ground terminal so that transistors in the first-stage main circuit 201 form a current path. The first-stage auxiliary circuit 202 is connected to a power terminal and a ground terminal so that transistors in the first-stage auxiliary circuit 202 form a current path. The second stage circuit 203 is connected to a power supply terminal or a ground terminal so that the transistors in the second stage circuit 203 form another current path. By so doing, the number of transistors in each current path can be reduced, thereby reducing the operating voltage of the comparator, as compared to a comparator structure including only one stage of circuit.

In one embodiment, the first stage 201 and the second stage 202 have the same number of transistors in their respective current paths, so that the operating voltages of the first stage 201 and the second stage 202 are the same, the number of power supply terminals required for the comparator is reduced, and the circuit of the comparator is simplified.

The first stage main circuit 201 is provided with a first pair of transistors and a second pair of transistors for receiving a first input signal and a first reference signal. That is, a first transistor of the first pair of transistors is configured to receive the first input signal and a second transistor of the first pair of transistors is configured to receive the first reference signal. A first transistor of the second pair of transistors is for receiving a first input signal and a second transistor of the second pair of transistors is for receiving a first reference signal. The first pair of transistors and the second pair of transistors are further configured to generate a first differential signal from the first input signal and the first reference signal during the sampling phase.

Since the first pair of tubes and the second pair of tubes have different transistor types, their pull directions to the voltage are different. The first input signal and the first reference signal are used to control the pull capability of the first pair of transistors and the second pair of transistors to the voltage. If the first input signal and the first reference signal make the voltage pulling capacities of the first pair of transistors and the second pair of transistors unbalanced, even if the difference between the first input signal and the first reference signal is very tiny, the first differential signal can be generated between the first pair of transistors and the second pair of transistors, so that the precision of the comparator is improved.

For example: the first transistor pair includes a first input transistor P1 and a second input transistor P2, the second transistor pair includes a third input transistor N1 and a fourth input transistor N2, and the first reference signal equalizes the ability of the second input transistor P2 to pull a voltage up and the ability of the fourth input transistor N2 to pull a voltage down. When the first input signal is slightly larger than the first reference signal, the first input signal unbalances the ability of the first input transistor P1 to pull up the voltage and the ability of the third input transistor N1 to pull down the voltage, and a first differential signal is generated on the first pair of transistors and the second pair of transistors.

It should be noted that, because the first pair of transistors and the second pair of transistors of different types are used to receive the first input signal and the first reference signal, the value of the first reference signal may be changed from 0.3V to 0.9V, and both the first pair of transistors and the second pair of transistors may generate the first differential signal, thereby expanding the selection range of the reference voltage of the comparator.

The first-stage auxiliary circuit is provided with a third pair of transistors and a fourth pair of transistors, the types of the third pair of transistors and the fourth pair of transistors are different, and the third pair of transistors and the fourth pair of transistors are used for receiving a second input signal and a second reference signal and are also used for generating a second differential signal according to the second input signal and the second reference signal. The circuit structure of the first-stage auxiliary circuit is similar to that of the first-stage main circuit, and the description of the first-stage auxiliary circuit is not repeated herein, and specific reference may be made to the description of the first-stage main circuit.

The first-stage main circuit 201 and the first-stage auxiliary circuit 202 are each provided with two output terminals, both labeled as a first output terminal and a second output terminal. The second stage 203 has two inputs, labeled a first input and a second input. The first output end of the first-stage main circuit 201 is connected with the first output end of the first-stage auxiliary circuit 202 and then connected with the first input end of the second-stage circuit 203, and the second output end of the first-stage main circuit 201 is connected with the second output end of the first-stage auxiliary circuit 202 and then connected with the second input end of the second-stage circuit 202. The first-stage main circuit is used for generating a first differential signal according to a first input signal and a first reference signal in a sampling stage, and the first-stage auxiliary circuit is used for generating a second differential signal according to a second input signal and a second reference signal in the sampling stage. The second stage circuit is used for carrying out amplification processing and latch processing on the first differential signal and the second differential signal in a regeneration stage so as to output a comparison result.

The comparator comprises a first-stage main circuit and a first-stage auxiliary circuit, the first-stage main circuit generates a first differential signal, the first-stage auxiliary circuit generates a second differential signal, and when intersymbol interference occurs to enable the first-stage main circuit to be incapable of accurately sensing and outputting the differential signal, the first differential signal can be adjusted by the second differential signal output by the first-stage auxiliary circuit, so that the second-stage circuit generates a comparison result according to the adjusted first differential signal, intersymbol interference is eliminated, and accuracy of the comparator is improved.

As shown in fig. 4, an embodiment of the present application provides a specific circuit of a comparator, which includes a first primary circuit 201, a first secondary circuit 202, and a second secondary circuit 203.

The first stage circuit includes a first input transistor P1, a second input transistor P2, a third input transistor N1, a fourth input transistor N2, and a fifth input transistor N3. The first input transistor P1 and the second input transistor P2 constitute a first pair of transistors. The third input transistor N1 and the fourth input transistor N2 form a second pair of transistors.

The control terminal of the first input transistor P1 is configured to receive a first input signal In1, the first terminal of the first input transistor P1 is connected to the power supply terminal, and the second terminal of the first input transistor P1 is used as the first output terminal of the first-stage main circuit.

The control terminal of the second input transistor P2 is configured to receive the first reference signal Vr1, the first terminal of the second input transistor P2 is connected to the power supply terminal, and the second terminal of the second input transistor P2 serves as the second output terminal of the first-stage main circuit.

The control end of the third input transistor N1 is configured to receive a first input signal In1, the first end of the third input transistor N1 is connected to the second end of the first input transistor P1 to form a first output end of the first-stage main circuit, and the control end of the third input transistor N1 is connected to the control end of the first input transistor P1 to form a first input end of the comparator.

The control end of the fourth input transistor N2 is configured to receive the second reference signal Vr1, the first end of the fourth input transistor N2 is connected to the second end of the second input transistor P2 to form a second output end of the first primary circuit, and the control end of the fourth input transistor N2 is connected to the control end of the second input transistor P2 to form a second input end of the comparator.

A control terminal of the fifth input transistor N3 is configured to receive a clock signal, a first terminal of the fifth input transistor N3 is connected to the second terminal of the third input transistor N1 and the second terminal of the fourth input transistor N2, and a second terminal of the fifth input transistor N3 is connected to the ground terminal.

The fifth input transistor N3 is used to control the operating state of the first stage main circuit. In the reset stage, the fifth input transistor N3 is turned off, the first-stage main circuit stops working, and in the sampling stage, the regeneration stage, and the decision stage, the first-stage main circuit works. In the sampling phase, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 generate a first differential signal under the control of the first input signal and the first reference signal.

The first-stage auxiliary circuit 102 includes at least one equalizing module 1020 connected in parallel, each equalizing module 1020 is provided with a first output end and a second output end, the first output ends of the equalizing modules 1020 are connected to each other to form the first output end of the first-stage auxiliary circuit 102, and the second output ends of the equalizing modules 1020 are connected to each other to form the second output end of the first-stage auxiliary circuit 102.

Each equalizing module 1020 includes a sixth input transistor P3, a seventh input transistor P4, an eighth input transistor N4, a ninth input transistor N5, and a tenth input transistor N6. Each input transistor is provided with a control terminal, a first terminal and a second terminal.

The control ends of the sixth input transistor P3 and the eighth input transistor N4 of each equalization module are connected, and then the control end of the sixth input transistor P3 and the control end of the eighth input transistor N4 of each equalization module are connected to each other to form a third input end of the comparator.

The control end of the seventh input transistor P4 of each equalizing module is connected, the control end of the ninth input transistor N5 of each equalizing module is connected, and then the control end of the seventh input transistor P4 of each equalizing module and the control end of the ninth input transistor N5 of each equalizing module are connected to form a fourth input end of the comparator.

A second end of the sixth input transistor P3 and a first end of the eighth input transistor N4 are connected to serve as a first output end of the equalizing module 1020, and a control end of the sixth input transistor P3 and a control end of the eighth input transistor N4 are configured to receive the second input signal In2.

A second terminal of the seventh input transistor P4 and a first terminal of the ninth input transistor N5 are connected to serve as a second output terminal of the equalizing module 1020, and a control terminal of the seventh input transistor P4 and a control terminal of the ninth input transistor N5 are configured to receive the second reference signal Vr2.

A first terminal of the tenth input transistor N6 is connected to the second terminals of the eighth input transistor N4 and the ninth input transistor N5, and a second terminal of the tenth input transistor N6 is connected to the ground terminal.

The tenth input transistor N6 is used to control the operating state of the first-stage auxiliary circuit. In the reset phase, the tenth input transistor N6 is turned off, the first-stage auxiliary circuit stops working, and in the sampling phase, the regeneration phase, and the decision phase, the first-stage auxiliary circuit works. During the sampling phase, the sixth input transistor P3, the seventh input transistor P4, the eighth input transistor N4 and the ninth input transistor N5 generate a second differential signal under the control of the second input signal and the second reference signal.

The output circuit 105 includes a first output transistor N7, a second output transistor N8, a third output transistor P5, and a fourth output transistor P6. A first terminal of the first output transistor N7 is connected to a second terminal of the third output transistor P5, and a first terminal of the second output transistor N8 is connected to a second terminal of the fourth output transistor P6. The control terminal of the first output transistor N7 is connected to the control terminal of the third output transistor P5, and then to the second terminal of the fourth output transistor P6. The control terminal of the second output transistor N8 is connected to the control terminal of the fourth output transistor P6, and then to the second terminal of the third output transistor P5.

A second terminal of the first output transistor N7 is a first input terminal of the output circuit 105, and a second terminal of the second output transistor N8 is a second input terminal of the output circuit 105. A second terminal of the third output transistor P5 serves as a first output terminal PB of the comparator, and a second terminal of the fourth output transistor P6 serves as a second output terminal P of the comparator.

After the first-stage main circuit and the first-stage auxiliary circuit generate the first differential signal and the second differential signal, respectively, the voltages of the first terminal of the first output transistor N7 and the first terminal of the second output transistor N8 are pulled down. The transistor is turned on when the voltage is pulled down to the flipping voltage. That is, the first output transistor N7 and the fourth output transistor P6 are turned on, or the second output transistor N8 and the third output transistor P5 are turned on, so as to pull the voltages at the two output ends of the comparator in different directions, thereby amplifying and latching the voltage signals at the output ends of the first-stage main circuit and the first-stage auxiliary circuit, and outputting the comparison result.

In an embodiment, the comparator further comprises a reset circuit for resetting the voltages at the two outputs of the comparator. The reset circuit includes a first reset transistor P7 and a second reset transistor P8. The first terminal of the first reset transistor P7 is connected to the power supply terminal, and the second terminal of the first reset transistor P7 is connected to the second terminal of the third output transistor P5, so as to pull the second terminal of the third output transistor P5 to a high level after the conduction in the reset phase.

The first terminal of the second reset transistor P8 is connected to the power supply terminal, and the second terminal of the second reset transistor P8 is connected to the second terminal of the fourth output transistor P6, so that the second terminal of the fourth output transistor P6 is pulled to a high level after being turned on in the reset phase.

In one embodiment, the first input transistor P1, the second input transistor P2, the sixth input transistor P3, and the seventh input transistor P4 are of the same type, and the third input transistor N1, the fourth input transistor N2, the fifth input transistor N3, the eighth input transistor N4, the ninth input transistor N5, and the tenth input transistor N6 are of the same type.

If the first input transistor P1, the second input transistor P2, the sixth input transistor P3 and the seventh input transistor P4 are P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal. If the third input transistor N1, the fourth input transistor N2, the fifth input transistor N3, the eighth input transistor N4, the ninth input transistor N5, and the tenth input transistor N6 are N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal.

In one embodiment, the first input transistor P1 and the second input transistor P2 are the same size, the sixth input transistor P3 and the seventh input transistor P4 are the same size, and the size of the sixth input transistor P3 is less than one-half of the size of the first input transistor P1.

The third input transistor N1 and the fourth input transistor N2 are the same in size, the eighth input transistor N4 and the ninth input transistor N5 are the same in size, and the size of the eighth input transistor N4 is smaller than one-half of the size of the third input transistor N1.

Through the above arrangement, it is possible to avoid the first-stage auxiliary circuit pair from being influenced too much to cause the inversion of the first differential signal, for example: the first input signal and the first reference signal make the first terminal voltage of the first input transistor N1 greater than the first terminal voltage of the second input transistor N2, and the first differential signal is inverted due to the intervention of the second differential signal, that is, the first terminal voltage of the first input transistor N1 is made less than the first terminal voltage of the second input transistor N2.

In one embodiment, the first output transistor N7 and the second output transistor N8 have the same transistor type, and the third output transistor P5 and the fourth output transistor P6 have the same transistor type.

If the first output transistor N7 and the second output transistor N8 are both N-type transistors, the drain of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal, and if the third output transistor P5 and the fourth output transistor P6 are both P-type transistors, the source of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

The first-stage main circuit is connected to the ground terminal through a fifth input transistor N3 and to the power terminal through the first input transistor P1 or the second input transistor P2. Each current path in the first stage main circuit includes 3 transistors, for example: a current path formed by the third input transistor N1, the fifth input transistor N3, and the first input transistor P1.

The second stage circuit is connected to a power supply terminal through the third output transistor P5 or the fourth output transistor P6. Each current path in the second stage circuit includes 4 transistors, for example: a current path formed by the third output transistor P5, the first output transistor N7, the third input transistor N1, and the fifth input transistor N3.

Through setting up as above, adopt the structure of first level circuit and second level circuit, compare in the comparator that adopts the primary structure, the operating voltage of comparator is lower, and application scope is wider.

Table 1 below illustrates that the comparator can implement rail-to-rail detection, that is, the variation range of the first reference voltage is relatively large, and the range of the first reference signal can be varied from 0.3V to 0.9V, taking the power supply terminal voltage VDD as 1.2V as an example.

TABLE 1 working principle of the sampling phase of the comparator

In case 3, the first input transistor P1, the second input transistor P2 and the third input transistor N1 are all turned on, the pull-up capability of the first input transistor P1 is smaller than that of the second input transistor P2, and the third input transistor N1 also pulls down the voltage of the first input transistor P1, so VP1 < VP2.

In case 6, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 are all turned on, the pull-up capability of the first input transistor P1 is greater than that of the second input transistor P2, and the capability of the third input transistor N1 to pull down the voltage of the first input transistor P1 is less than that of the fourth input transistor N2 to pull down the voltage of the second input transistor P2, so VP1 > VP2.

For the analysis of other cases, reference may be made to the analysis of cases 3 and 6, which are not described herein again.

That is, when the first reference voltage changes from 0.3V to 0.9V, the first differential signal is generated on the first input transistor P1 and the second input transistor P2, and then the second stage circuit generates the comparison result according to the first differential signal and the second differential signal, so as to implement the rail-to-rail detection.

The principle of the comparator for eliminating the inter-symbol interference is described below with reference to table 2, where the values of the second input signal and the second reference signal at the time t1 are determined according to the values of the first input signal and the first reference signal at the time t0, and if the first input signal at the time t0 is greater than the first reference signal at the time t0, the second input signal at the time t1 is smaller than the value of the second reference signal, and vice versa.

TABLE 2 cases of intersymbol interference

As can be seen from table 2, in the first case, the inter-symbol interference makes the voltage of the first input transistor N1 and the voltage of the second input transistor N2 equal, but the voltage of the fourth input transistor N4 is smaller than the voltage of the fifth input transistor N5, so that the voltage of the first output terminal O1 of the first-stage main circuit is smaller than the voltage of the second output terminal O2, and the inter-symbol interference is eliminated as the result of the absence of inter-symbol interference. It should be noted here that, since the size of each transistor in the auxiliary circuit is smaller than one half of the size of each transistor in the main circuit, even in the case of VN1 < VN2, VN4 > VN5, where VN1, VN2, VN4 and VN5 represent the drain voltages of the first input transistor N1, the second input transistor N2, the third input transistor N3 and the fourth input transistor N4, respectively, but the pull-in capability of the fourth input transistor N4 and the fifth input transistor N5 to the voltage is smaller than that of the first input transistor N1 and the second input transistor N2, respectively, so that the voltage VO1 of the first output terminal of the first-stage main circuit is still smaller than the voltage VO2 of the second output terminal of the first-stage main circuit, and as a result of the absence of intersymbol interference is the same, the intersymbol interference is eliminated.

As shown in fig. 5, an embodiment of the present application provides a specific circuit of a comparator, which includes a first primary circuit 201, a first secondary circuit 202, and a second secondary circuit 203.

The first stage circuit includes a first input transistor N1, a second input transistor N2, a third input transistor P1, a fourth input transistor P2, and a fifth input transistor P3. The first input transistor N1 and the second input transistor N2 constitute a first transistor pair. The third input transistor P1 and the fourth input transistor P2 form a second pair of transistors.

The control terminal of the first input transistor N1 is configured to receive a first input signal In1, the first terminal of the first input transistor N1 is connected to the ground terminal, and the second terminal of the first input transistor N1 is used as the first output terminal of the first-stage main circuit.

The control terminal of the second input transistor N2 is configured to receive the first reference signal Vr1, the first terminal of the second input transistor N2 is connected to the ground terminal, and the second terminal of the second input transistor N2 is used as the second output terminal of the first-stage main circuit.

A control end of the third input transistor P1 is configured to receive the first input signal In1, a first end of the third input transistor P1 is connected to a second end of the first input transistor N1 to form a first output end of the first-stage main circuit, and a control end of the third input transistor P1 is connected to a control end of the first input transistor N1 to form a first input end of the comparator.

The control end of the fourth input transistor P2 is configured to receive the second reference signal Vr1, the first end of the fourth input transistor P2 is connected to the second end of the second input transistor N2 to form a second output end of the first primary circuit, and the control end of the fourth input transistor P2 is connected to the control end of the second input transistor N2 to form a second input end of the comparator.

A control terminal of the fifth input transistor P3 is configured to receive the clock signal, a first terminal of the fifth input transistor P3 is connected to the second terminal of the third input transistor P1 and the second terminal of the fourth input transistor P2, and a second terminal of the fifth input transistor P3 is connected to the power supply terminal.

The fifth input transistor P3 is used to control the operating state of the first stage main circuit. In the reset phase, the fifth input transistor P3 is turned off, the first-stage main circuit stops working, and in the sampling phase, the regeneration phase and the decision phase, the first-stage main circuit works. In the sampling phase, the first input transistor N1, the second input transistor N2, the third input transistor P1 and the fourth input transistor P2 generate a first differential signal under the control of the first input signal and the first reference signal.

The first-stage auxiliary circuit 102 includes at least one equalization module 1020 connected in parallel, each equalization module 1020 has a first output end and a second output end, the first output ends of the equalization modules 1020 are connected to each other to form the first output end of the first-stage auxiliary circuit 102, and the second output ends of the equalization modules 1020 are connected to each other to form the second output end of the first-stage auxiliary circuit 102.

Each equalization module 1020 includes a sixth input transistor N3, a seventh input transistor N4, an eighth input transistor P4, a ninth input transistor P5, and a tenth input transistor P6. Each input transistor is provided with a control terminal, a first terminal and a second terminal.

The control ends of the sixth input transistor N3 and the eighth input transistor P4 of each equalizing module are connected, and the control ends of the sixth input transistor N3 and the eighth input transistor P4 of each equalizing module are connected to form a third input end of the comparator.

The control terminal of the seventh input transistor N4 of each equalization module is connected, the control terminal of the ninth input transistor P5 of each equalization module is connected, and then the control terminal of the seventh input transistor N4 of each equalization module and the control terminal of the ninth input transistor P5 of each equalization module are connected to each other to form the fourth input terminal of the comparator.

A second end of the sixth input transistor N3 and a first end of the eighth input transistor P4 are connected to serve as a first output end of the equalizing module 1020, and a control end of the sixth input transistor N3 and a control end of the eighth input transistor P4 are configured to receive the second input signal In2.

A second terminal of the seventh input transistor N4 and a first terminal of the ninth input transistor P5 are connected to serve as a second output terminal of the equalizing module 1020, and a control terminal of the seventh input transistor N4 and a control terminal of the ninth input transistor P5 are configured to receive the second reference signal Vr2.

A first terminal of the tenth input transistor P6 is connected to the second terminals of the eighth and ninth input transistors P4 and P5, and a second terminal of the tenth input transistor P6 is connected to the power source terminal.

The tenth input transistor P6 is used to control the operating state of the first stage auxiliary circuit. In the reset phase, the tenth input transistor P6 is turned off, the first-stage auxiliary circuit stops working, and in the sampling phase, the regeneration phase, and the decision phase, the first-stage auxiliary circuit works. During the sampling phase, the sixth input transistor N3, the seventh input transistor N4, the eighth input transistor P4 and the ninth input transistor P5 generate a second differential signal under the control of the second input signal and the second reference signal.

The output circuit 105 includes a first output transistor P7, a second output transistor P8, a third output transistor N5, and a fourth output transistor N6. A first terminal of the first output transistor P7 is connected to a second terminal of the third output transistor N5, and a first terminal of the second output transistor P8 is connected to a second terminal of the fourth output transistor N6. The control terminal of the first output transistor P7 is connected to the control terminal of the third output transistor N5, and then to the second terminal of the fourth output transistor N6. The control terminal of the second output transistor P8 is connected to the control terminal of the fourth output transistor N6, and then to the second terminal of the third output transistor N5.

A second terminal of the first output transistor P7 is a first input terminal of the output circuit 105, and a second terminal of the second output transistor P8 is a second input terminal of the output circuit 105. A second terminal of the third output transistor N5 serves as a first output terminal PB of the comparator, and a second terminal of the fourth output transistor N6 serves as a second output terminal P of the comparator.

After the first-stage main circuit and the first-stage auxiliary circuit generate the first differential signal and the second differential signal, respectively, the voltages of the first terminal of the first output transistor P7 and the first terminal of the second output transistor P8 are pulled down. The transistor is turned on when the voltage is pulled down to the flipping voltage. That is, the first output transistor P7 and the fourth output transistor N6 are turned on, or the second output transistor P8 and the third output transistor N5 are turned on, so as to pull the voltages at the two output ends of the comparator in different directions, thereby amplifying and latching the voltage signals at the output ends of the first-stage main circuit and the first-stage auxiliary circuit, and outputting the comparison result.

In an embodiment, the comparator further comprises a reset circuit for resetting the voltages at the two outputs of the comparator. The reset circuit comprises a first reset transistor N7 and a second reset transistor N8, wherein the first end of the first reset transistor N7 is connected with the ground end, and the second end of the first reset transistor N7 is connected with the second end of the third output transistor N5, so that the second end of the third output transistor N5 is pulled to a high level after the conduction in the reset stage.

The first end of the second reset transistor N8 is connected to the ground terminal, and the second end of the second reset transistor N8 is connected to the second end of the fourth output transistor N6, so that the second end of the fourth output transistor N6 is pulled to a high level after being turned on in the reset stage.

In one embodiment, the first input transistor N1, the second input transistor N2, the sixth input transistor N3, and the seventh input transistor N4 are of the same type, and the third input transistor P1, the fourth input transistor P2, the fifth input transistor P3, the eighth input transistor P4, the ninth input transistor P5, and the tenth input transistor P6 are of the same type.

If the types of the first input transistor N1, the second input transistor N2, the sixth input transistor N3, and the seventh input transistor N4 are N-type transistors, the source of the N-type transistor is the first terminal, and the gate of the N-type transistor is the control terminal. If the third input transistor P1, the fourth input transistor P2, the fifth input transistor P3, the eighth input transistor P4, the ninth input transistor P5 and the tenth input transistor P6 are P-type transistors, the drain of the P-type transistor is the first terminal, and the gate of the P-type transistor is the control terminal.

In one embodiment, the first input transistor N1 and the second input transistor N2 are the same size, the sixth input transistor N3 and the seventh input transistor N4 are the same size, and the size of the sixth input transistor N3 is less than one-half of the size of the first input transistor N1.

The third input transistor P1 and the fourth input transistor P2 are the same size, and the eighth input transistor P4 and the ninth input transistor P5 are the same size; the size of the eighth input transistor P4 is smaller than half the size of the third input transistor P1.

Through the above arrangement, it is possible to avoid the first-stage auxiliary circuit pair from being influenced too much to cause the inversion of the first differential signal, for example: the first input signal and the first reference signal make the first terminal voltage of the first input transistor P1 greater than the first terminal voltage of the second input transistor P2, and the first differential signal is inverted due to the intervention of the second differential signal, that is, the first terminal voltage of the first input transistor P1 is less than the first terminal voltage of the second input transistor P2.

In one embodiment, the first output transistor P7 and the second output transistor P8 have the same transistor type, and the third output transistor N5 and the fourth output transistor N6 have the same transistor type.

If the first output transistor P7 and the second output transistor P8 are both P-type transistors, the drains of the P-type transistors are first terminals, and the gates of the P-type transistors are control terminals, and if the third output transistor N5 and the fourth output transistor N6 are both N-type transistors, the sources of the N-type transistors are first terminals, and the gates of the N-type transistors are control terminals.

The first-stage main circuit is connected with a power supply end through a fifth input transistor P3 and is connected with a grounding end through a first input transistor N1 or a second input transistor N2. Each current path in the first stage main circuit includes 3 transistors, for example: a current path formed by the third input transistor P1, the fifth input transistor P3, and the first input transistor N1.

The second stage circuit is connected to the ground terminal through the third output transistor N5 or the fourth output transistor N5. Each current path in the second stage circuit includes 4 transistors, for example: a current path formed by the third output transistor N5, the first output transistor P7, the third input transistor P1, and the fifth input transistor P3.

The principle of the comparator for realizing rail-to-rail detection is the same as that in table 1, and is not described herein again.

The principle of the comparator for eliminating the inter-symbol interference is described below with reference to table 3, where the setting manner of the second reference signal and the second input signal is the same as that in table 2, and is not repeated here.

TABLE 3 intersymbol interference situation

As can be seen from table 3, in the first case, the inter-symbol interference makes the voltage of the first input transistor P1 and the voltage of the second input transistor P2 equal, but the voltage of the fourth input transistor P4 is smaller than the voltage of the fifth input transistor P5, so that the voltage of the first output terminal O1 of the first stage circuit is smaller than the voltage of the second output terminal O2, and the inter-symbol interference is eliminated as the result of the absence of inter-symbol interference. It should be noted here that, since the size of each transistor in the auxiliary circuit is smaller than one-half of the size of each transistor in the main circuit, VP1 < VP2, and VP4 > VP5 even in case 2, where VP1, VP2, VP4, and VP5 represent the drain voltages of the first input transistor P1, the second input transistor P2, the third input transistor P3, and the fourth input transistor P4, respectively, but the voltage pulling capabilities of the fourth input transistor P4 and the fifth input transistor P5 are smaller than the voltage pulling capabilities of the first input transistor P1 and the second input transistor P2, respectively, so that the voltage VO1 at the first output terminal of the first stage circuit is still smaller than the voltage VO2 at the second output terminal of the first stage circuit, and the inter-symbol interference is eliminated as a result of the absence of inter-symbol interference is the same.

As shown in fig. 6, an embodiment of the present application provides a decision feedback equalization circuit, which includes four comparators described in the foregoing embodiments, which are sequentially labeled as a first comparator 100, a second comparator 200, a third comparator 300, and a fourth comparator 400.

The third input terminal In2 of the first comparator 100 is connected to the first output terminal P270B of the fourth comparator 400, and the fourth input terminal Vr2 of the first comparator 100 is connected to the second output terminal P270 of the fourth comparator 400. The third input terminal In2 of the second comparator 200 is connected to the first output terminal P0B of the first comparator 100, and the fourth input terminal Vr2 of the second comparator 200 is connected to the second output terminal P0 of the first comparator 100. The third input terminal In2 of the third comparator 300 is connected to the first output terminal P90B of the second comparator 200, and the fourth input terminal Vr2 of the third comparator 300 is connected to the second output terminal P90 of the second comparator 200. The third input terminal In2 of the fourth comparator 400 is connected to the first output terminal P270B of the third comparator 300, and the fourth input terminal Vr2 of the fourth comparator 400 is connected to the second output terminal P270 of the third comparator 300.

First input terminals In1 of the first to fourth comparators 100 to 400 all receive the first input signal, and second input terminals Vref1 of the first to fourth comparators 100 to 400 all receive the first reference signal.

Assuming that the fourth register 400 outputs a digital "1" when the first input signal is greater than the first reference signal at the previous time, at the current time, the third input terminal In2 of the first register 100 receives a low level, and the fourth input terminal Vr2 of the first register 100 receives a high level, that is, the signal of the third input terminal In2 is smaller than the signal of the fourth input terminal Vr2, assuming that the first input signal is also greater than the first reference signal at the current time, the intersymbol interference still makes the first input signal greater than the first reference signal, and the first register 100 still outputs the digital "1".

Assuming that the fourth register 400 outputs a digital "1" when the first input signal is greater than the first reference signal at the previous time, at the current time, the signal at the third input terminal In2 of the first register is smaller than the signal at the fourth input terminal Vr2, and assuming that the first input signal is smaller than the first reference signal at the current time, if the first input signal is equal to or slightly larger than the first reference signal due to the inter-symbol interference, the first register 100 still outputs a digital "0" because the signal at the third input terminal In2 is smaller than the signal at the fourth input terminal Vr2.

Assuming that the fourth register 400 outputs a digital "0" when the first input signal is smaller than the first reference signal at the previous time, the signal at the third input terminal In2 of the first register 100 is larger than the signal at the fourth input terminal Vr2 at the current time, and assuming that the first input signal is also smaller than the first reference signal at the current time, the inter-symbol interference still causes the first input signal to be smaller than the first reference signal, and the first register 100 still outputs the digital "0".

Assuming that the fourth register 400 outputs a digital "0" when the first input signal is smaller than the first reference signal at the previous time, at the current time, the signal In2 at the third input terminal of the first register 100 is larger than the signal at the fourth input terminal Vr2, assuming that the first input signal is larger than the first reference signal at the current time, if the first input signal is equal to or slightly smaller than the first reference signal due to the inter-symbol interference, the first register 100 still outputs a digital "1" because the signal at the third input terminal is larger than the signal at the fourth input terminal.

The operation principle of the second register 200 to the fourth register 400 is the same as that of the first register 100, and the description thereof is omitted.

The decision feedback equalizer circuit shown in fig. 6 belongs to a first-order circuit, and in order to achieve better intersymbol interference elimination, a multi-order circuit is usually used. Fig. 7 is a schematic diagram illustrating the effect of a 4-order decision feedback equalization circuit, and tap1 to tap4 sequentially represent a first-order decision feedback equalization circuit to a fourth-order decision feedback equalization circuit. As shown in fig. 7, the actual waveform of the first input signal under intersymbol interference is shown in curve 1, and the falling edge is relatively gentle when the first input signal switches from the high level to the low level, that is, there is a case where the first input signal is erroneously recognized as the high level. The four-order decision feedback equalization circuit can effectively eliminate intersymbol interference, so that the equivalent waveform of a first input signal input into the decision feedback equalization circuit is shown as a curve 2, and the falling edge becomes steep.

In an embodiment, the phase of the first clock signal of the first comparator 100 is 90 ° earlier than the phase of the second clock signal of the second comparator 200, the phase of the first clock signal of the first comparator 100 is 180 ° earlier than the phase of the third clock signal of the third comparator 300, and the phase of the first clock signal of the first comparator 100 is 270 ° earlier than the phase of the fourth clock signal of the fourth comparator 400.

In one embodiment, the voltage transition time from the output terminal of the first comparator 100 to the output terminal of the fourth comparator 400 _FB Are smaller than the time interval 1U1 between the first clock signal and the second clock signal, as shown in fig. 8, taking the fourth comparator as an example for illustration, when the flip time of the output voltage of the fourth comparator 400 is smaller than 1U1, 1UI represents the time interval between the first clock signal and the second clock signal, it can be ensured that when the clock signal of the first comparator 100 arrives, the fourth comparator 400 has stably output the comparison result, and the fourth comparator 400 maintains the comparison result, so that the first comparator 100 can eliminate the inter-symbol interference according to the comparison result of the fourth comparator 400.

In one embodiment, the decision feedback equalization circuit further comprises four registers, which are sequentially labeled as a first register 500, a second register 600, a third register 700, and a fourth register 800. The input of the first register 500 is connected to two outputs of the first comparator 100, the input of the second register 600 is connected to two outputs of the second comparator 200, the input of the third register 700 is connected to two outputs of the third comparator 300, and the input of the fourth register 800 is connected to two outputs of the fourth comparator 400. The four registers are respectively used for storing the comparison result output by the four corresponding comparators, D0 is the result output by the first register 500, D90 is the result output by the second register 600, D180 is the result output by the third register 700, and D270 is the result output by the fourth register 800.

In the technical scheme, two output ends of the fourth register are connected with two input ends of the first register, two output ends of the first register are connected with two input ends of the second register, and so on, to form the decision feedback equalization circuit, the other two input ends of the four registers receive the first input signal and the first reference signal, and the intersymbol interference caused by continuous input of the first input signal in the registers can be effectively eliminated under the control of the output end signals of the four registers.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A comparator, comprising:

the first-stage main circuit is connected with a power supply end and a ground end and is provided with a first pair of transistors and a second pair of transistors, the first pair of transistors and the second pair of transistors are different in type, the first pair of transistors and the second pair of transistors are used for receiving a first input signal and a first reference signal and are also used for generating a first differential signal according to the first input signal and the first reference signal in a sampling stage;

the first-stage auxiliary circuit is connected with a power supply end or a ground end and is provided with a third pair of transistors and a fourth pair of transistors, the third pair of transistors and the fourth pair of transistors are different in type, and the third pair of transistors and the fourth pair of transistors are used for receiving a second input signal and a second reference signal and are also used for generating a second differential signal according to the second input signal and the second reference signal in a sampling stage;

and the second-stage circuit is connected with the first-stage main circuit and the first-stage auxiliary circuit and is used for amplifying and latching the voltage signal at the output end of the first-stage main circuit and the voltage signal at the output end of the first-stage auxiliary circuit in a regeneration stage so as to output a comparison result.

2. The comparator of claim 1, wherein the first stage main circuit, the first stage auxiliary circuit, and the second stage circuit have the same number of transistors on respective current paths.

3. The comparator according to claim 1 or 2, wherein the first stage main circuit comprises:

a first input transistor, a control terminal of which is used for receiving the first input signal, and a second terminal of which is used as a first output terminal of the first-stage main circuit;

a second input transistor, a control terminal of which is used for receiving the first reference signal, and a second terminal of which is used as a second output terminal of the first-stage main circuit;

a third input transistor, a control terminal of which is used for receiving the first input signal, and a first terminal of which is connected with a second terminal of the first input transistor;

a fourth input transistor, a control terminal of which is used for receiving the first reference signal, and a first terminal of which is connected with a second terminal of the second input transistor;

and a control terminal of the fifth input transistor is used for receiving a clock signal, a first terminal of the fifth input transistor is connected with the second terminal of the third input transistor and the second terminal of the fourth input transistor, and a second terminal of the fifth input transistor is connected with a ground terminal or a power supply terminal.

4. The comparator of claim 3, wherein the first stage auxiliary circuit comprises at least one regulation module, each regulation module comprising:

a sixth input transistor, a control terminal of which is used for receiving the second input signal, and a second terminal of which is used as a first output terminal of the first-stage auxiliary circuit;

a seventh input transistor, a control terminal of which is used for receiving the second reference signal, and a second terminal of which is used as a second output terminal of the first-stage auxiliary circuit;

an eighth input transistor, a control terminal of which is used for receiving the second input signal, and a first terminal of which is connected with a second terminal of the sixth input transistor;

a ninth input transistor having a control terminal for receiving the second reference signal and a first terminal connected to the second terminal of the seventh input transistor;

and a tenth input transistor having a control terminal for receiving a clock signal, a first terminal connected to the second terminal of the eighth input transistor and the second terminal of the ninth input transistor, and a second terminal connected to ground or a power terminal.

5. The comparator of claim 4, wherein:

the first input transistor, the second input transistor, the sixth input transistor, and the seventh input transistor are of the same type;

the third, fourth, fifth and eighth input transistors are of the same type as the ninth and tenth input transistors.

6. The comparator of claim 5, wherein:

the first input transistor and the second input transistor are the same in size, the sixth input transistor and the seventh input transistor are the same in size, and the size of the sixth input transistor is smaller than one-half of the size of the first input transistor;

the third input transistor and the fourth input transistor are the same size, and the eighth input transistor and the ninth input transistor are the same size; the size of the eighth input transistor is less than one-half the size of the third input transistor.

7. The comparator of claim 5, wherein:

when the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are P-type transistors, a source electrode of the P-type transistor is a first end, and a grid electrode of the P-type transistor is a control end;

when the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor, and the tenth input transistor are N-type transistors, a drain of the N-type transistor is a first terminal, and a gate of the P-type transistor is a control terminal.

8. The comparator of claim 5, wherein:

when the first input transistor, the second input transistor, the sixth input transistor and the seventh input transistor are N-type transistors, a source electrode of the N-type transistor is a first end, and a grid electrode of the N-type transistor is a control end;

when the third input transistor, the fourth input transistor, the fifth input transistor, the eighth input transistor, the ninth input transistor, and the tenth input transistor are P-type transistors, a drain of the P-type transistor is a first terminal, and a gate of the P-type transistor is a control terminal.

9. The comparator of claim 1, wherein the second stage circuit comprises:

a first output transistor, a second end of which is a first input end of the second stage circuit;

a second output transistor, a second end of which is a second input end of the second stage circuit;

a control end of the third output transistor is connected with the control end of the first output transistor and then connected with a second end of the fourth output transistor, and the second end of the third output transistor is used as a first output end of the second-stage circuit;

and a control end of the fourth output transistor is connected with the control end of the second output transistor and then connected with a second end of the third output transistor, and the second end of the fourth output transistor is used as a second output end of the second-stage circuit.

10. The comparator of claim 9, wherein:

if the first output transistor and the second output transistor are both N-type transistors, the drain electrode of the N-type transistor is a first end, and the grid electrode of the N-type transistor is a control end;

if the third output transistor and the fourth output transistor are both P-type transistors, the source electrode of the P-type transistor is a first end, and the grid electrode of the P-type transistor is a control end.

11. The comparator of claim 9, wherein:

if the first output transistor and the second output transistor are both P-type transistors, the drain electrode of the P-type transistor is a first end, and the grid electrode of the P-type transistor is a control end;

and if the third output transistor and the fourth output transistor are both N-type transistors, the source electrode of the N-type transistor is a first end, and the grid electrode of the P-type transistor is a control end.

12. A decision feedback equalizer circuit comprising four comparators as claimed in any one of claims 1 to 11, labeled first, second, third and fourth comparators in sequence;

a first input end of the first comparator is used for receiving a first input signal, a second input end of the first comparator is used for receiving a first reference signal, a third input end of the first comparator is connected with a first output end of the fourth comparator, and a fourth input end of the first comparator is connected with a second output end of the fourth comparator;

the first input end of the second comparator is used for receiving a first input signal, the second input end of the second comparator is used for receiving a first reference signal, the third input end of the second comparator is connected with the first output end of the first comparator, and the fourth input end of the second comparator is connected with the second output end of the first comparator;

a first input end of the third comparator is used for receiving a first input signal, a second input end of the third comparator is used for receiving a first reference signal, a third input end of the third comparator is connected with a first output end of the second comparator, and a fourth input end of the third comparator is connected with a second output end of the second comparator;

the first input end of the fourth comparator is used for receiving the first input signal, the second input end of the fourth comparator is used for receiving the first reference signal, the third input end of the fourth comparator is connected with the first output end of the third comparator, and the fourth input end of the fourth comparator is connected with the second output end of the third comparator.

13. The decision feedback equalization circuit of claim 12 wherein:

the phase of the first clock signal of the first comparator is 90 ° earlier than the phase of the second clock signal of the second comparator;

the phase of the first clock signal of the first comparator is 180 ° earlier than the phase of the third clock signal of the third comparator;

the phase of the first clock signal of the first comparator is 270 ° earlier than the phase of the fourth clock signal of the fourth comparator.

14. The decision feedback equalization circuit of claim 13 wherein:

the voltage reversal time of the output end of the first comparator to the voltage reversal time of the output end of the fourth comparator is smaller than the time interval between the first clock signal and the second clock signal.

15. The decision feedback equalization circuit of any of claims 12-14 further comprising: the four registers are sequentially marked as a first register, a second register, a third register and a fourth register;

the input end of the first register is connected with two output ends of the first comparator;

the input end of the second register is connected with two output ends of the second comparator;

the input end of the third register is connected with two output ends of the third comparator;

and the input end of the fourth register is connected with two output ends of the fourth comparator.