CN115412071A

CN115412071A - Comparator with a comparator circuit

Info

Publication number: CN115412071A
Application number: CN202110587219.6A
Authority: CN
Inventors: 谷银川
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2022-11-29

Abstract

The comparator comprises a first-stage circuit, a second-stage circuit and a positive feedback circuit, wherein the first-stage circuit is connected with a power supply end and a grounding end and is provided with a first pair of tubes and a second pair of tubes, the first pair of tubes and the second pair of tubes are different in type, the first pair of tubes and the second pair of tubes are used for receiving input signals and reference signals and generating differential signals according to the input signal signals and the reference signals in a sampling stage, the positive feedback circuit is connected with the output end of the first-stage circuit and is used for accelerating the difference between the differential signals, and the second-stage circuit is connected with the power supply end and the grounding end and is connected with the output end of the first-stage circuit and is used for amplifying and latching voltage signals at the output end of the first-stage circuit in a regeneration stage so as to output a comparison result. The comparator provided by the scheme has high response speed, low power consumption and low working voltage.

Description

Comparator with a comparator circuit

Technical Field

The present application relates to integrated circuits, and more particularly, to a comparator.

Background

Nowadays, people's demand for mobile devices such as cell-phones, panel computers and various wearable accessories greatly increases, and this has greatly richened our daily life and work.

However, due to the limited battery life, a higher requirement is imposed on the power consumption of each component in the mobile device, and a Dynamic Random Access Memory (DRAM) is an essential component in the mobile device. The comparator is an important device for realizing data reading and writing of the DRAM, and the existing comparator cannot meet the current use requirement.

Disclosure of Invention

The application provides a comparator, aims at promoting the response rate of comparator, reduces the consumption of comparator and the operating voltage of comparator.

In a first aspect, the present application provides a comparator comprising:

the first-stage circuit is connected with a power supply end and a grounding end and is provided with a first pair of transistors and a second pair of transistors, the types of the first pair of transistors and the second pair of transistors are different, the first pair of transistors and the second pair of transistors are used for receiving an input signal and a reference signal and generating a differential signal according to the input signal and the reference signal in a sampling stage;

the positive feedback circuit is connected with the output end of the first-stage circuit and is used for accelerating the difference between the differential signals;

and the second-stage circuit is connected with the power supply end and the grounding end, is connected with the output end of the first-stage circuit, and is used for amplifying and latching the voltage signal of the output end of the first-stage circuit in the regeneration stage so as to output a comparison result.

In a second aspect, the present application provides a comparator comprising:

the first stage circuit is provided with an output end and is used for generating a differential signal according to an input signal and a reference signal in a sampling stage;

and the second-stage circuit is connected with the output end of the first-stage circuit and is used for amplifying and latching the voltage signal of the output end of the first-stage circuit in the regeneration stage so as to output a comparison result.

The application provides a comparator, the comparator includes first stage circuit, positive feedback circuit and second stage circuit, first stage circuit is equipped with first geminate transistor and second geminate transistor, first geminate transistor and second geminate transistor are used for receiving input signal and reference signal, first geminate transistor and second geminate transistor still are used for producing difference signal according to input signal and reference signal at the sampling stage, positive feedback circuit is used for accelerating the difference between the difference signal, the second stage circuit is used for carrying out amplification processing and latch processing to the voltage signal of input circuit's output in regeneration stage to output comparison result. Because the types of the first pair of transistors and the second pair of transistors are different, namely the pulling capacities of the first pair of transistors and the second pair of transistors to the voltages are opposite, when the pulling capacities of the first pair of transistors and the second pair of transistors to the voltages are unbalanced by the input signal and the reference signal, even if the difference between the input signal and the reference signal is very small, the two groups of transistors can also accurately sense the voltages, and therefore the sensing precision of the comparator is improved. The positive feedback circuit is used for accelerating the difference between the differential signals, and the time of the comparator in the sampling stage can be shortened, so that the response efficiency of the comparator is improved, and the power consumption of the comparator is reduced. Because the first stage circuit includes two groups of different types of geminate transistors, the two groups of geminate transistors receive the input signal and the reference signal, so that the reference signal selection is wide, for example: the voltage can be changed from 0.3V to 0.9V, and differential signals can be generated in two groups of pair transistors, so that the working range of the comparator is expanded. Through the arrangement of two stages of circuits, namely, the first stage circuit generates a differential signal, and the second stage circuit generates a comparison result according to the differential signal, the number of transistors in the same circuit path can be reduced, so that the working voltage of the comparator is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.

Fig. 1 is a specific circuit diagram of a comparator provided in the present application;

FIG. 2 is a timing diagram illustrating the operation of the comparator provided in the present application;

fig. 3 is a block diagram of a comparator according to the present application;

FIG. 4 is a specific circuit diagram based on the comparator provided in FIG. 3;

FIG. 5 is another specific circuit diagram based on the comparator provided in FIG. 3;

fig. 6 is a block diagram of a comparator according to the present application;

FIG. 7 is a specific circuit diagram based on the comparator provided in FIG. 6;

FIG. 8 is a specific circuit diagram based on the positive feedback circuit in the comparator provided in FIG. 7;

FIG. 9 is a specific circuit diagram based on the comparator provided in FIG. 6;

FIG. 10 is a specific circuit diagram based on the positive feedback circuit in the comparator provided in FIG. 9;

FIG. 11 is a specific circuit diagram of a comparator provided in the present application;

FIG. 12 is a specific circuit diagram based on the positive feedback circuit in the comparator provided in FIG. 11;

FIG. 13 is a specific circuit diagram of a comparator provided in the present application;

fig. 14 is a specific circuit diagram of the positive feedback circuit in the comparator provided based on fig. 13.

Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims.

As shown in fig. 1, the comparator includes an input circuit 101, an output circuit 102, and a reset circuit 103. The output terminal of the input circuit 101 is connected to the input terminal of the output circuit 102. The reset circuit 103 is also connected to the output circuit 102.

The input circuit 101 includes a transistor N1, a transistor N2, and a transistor N3, the transistor N1 and the transistor N2 constitute a differential transistor pair, a gate of the transistor N1 and a gate of the transistor N2 constitute a first input terminal IP and a second input terminal IN of the input circuit, and a drain of the transistor N1 and a drain of the transistor N2 constitute two output terminals of the input circuit.

The output circuit 102 includes a transistor P1, a transistor P2, a transistor N4, and a transistor N5, the four transistors form a cross-coupled transistor pair, drains of the transistor P1 and the transistor N4 form a first output terminal ON of the output circuit 102, and drains of the transistor P2 and the transistor N5 form a second output terminal OP of the output circuit 102. The reset circuit 103 includes a transistor P3 and a transistor P4.

The working process of the comparator is divided into four stages, namely a reset stage, a sampling stage, a regeneration stage and a decision stage. The operation of the comparator shown in fig. 1 is described below with reference to fig. 2:

in the reset phase, i.e. from time t0 to time t1, the clock signal is at low level, the transistor N3 is turned off, the input circuit and the output circuit stop operating, the transistors P3 and P4 are turned on, and the reset circuit operates to pull the drain voltages of the transistor N4 and the transistor N5 to high level.

During the sampling period, i.e. from time t1 to time t2, the clock signal is high, the transistors P3 and P4 are turned off, and the reset circuit stops operating. The transistor N3 is closed, the input circuit collects input signals through the first input end IP, the input circuit collects reference signals through the second input end IN, the input signals pull the drain voltage of the transistor N1 downwards, and the reference signals pull the drain voltage of the transistor N2 downwards. The drain of transistor N1 pulls the drain voltage of transistor N4 down and the drain of transistor N2 pulls the drain voltage of transistor N5 down. Since the input signal is higher than the reference signal, the rate at which the input signal pulls the drain voltage of the transistor N1 is faster, so that the drain voltage of the transistor N4 is lower than the drain voltage of the transistor N5.

During the regeneration phase, i.e. from time t2 to time t3, the drain voltage of transistor N4 and the drain voltage of transistor N5 reach the inversion voltage, transistor P2 and transistor N4 are turned on, transistor P1 and transistor N5 are gradually turned off, transistor P2 pulls up the drain voltage of transistor N5, and transistor N4 pulls down the drain voltage of transistor N4.

In the decision phase, i.e. from time t3 to time t4, the transistors P2 and N4 are turned on, the transistors P1 and N5 are turned off, the drain voltage of the transistor N5 continues to be pulled up, the drain voltage of the transistor N4 continues to be pulled down, and the drain voltages of the transistors N4 and N5 are maintained after the drain of the transistor N5 is pulled to a low level and the drain voltage of the transistor N4 is pulled to a high level.

At the next duty cycle, the clock signal goes low, and the drain voltages of the transistors N4 and N5 are reset to high by the transistors P1 and P2.

However, when the selection of the reference signal is not appropriate, the time for the input signal and the reference signal to generate the differential signal at the output terminal of the input circuit is relatively long, which results in a reduction in the response rate of the comparator and also increases the power consumption of the comparator. For example, in the comparator shown in fig. 2, when the reference signal is small, the transistors N1 and N2 need to be turned on for a longer time, so that the charging current at the nodes VP and VN decreases, the transistors N1 and N2 pull the transistors N5 and N4 at a lower rate, the response rate of the comparator decreases, and the power consumption of the comparator also increases.

As shown in fig. 3, an embodiment of the present application provides a comparator, which includes a first stage circuit 201, a second stage circuit 203, and a positive feedback circuit 203. The first stage 201 is provided with an output end, and the second stage 203 and the positive feedback circuit 203 are both connected with the output end of the first stage 201.

The first stage 201 is connected to a power supply terminal and a ground terminal so that the transistors in the first stage 201 form a current path. The second stage 203 is connected to a power supply terminal and a ground terminal so that the transistors in the second stage 203 form another current path. By so doing, the number of transistors in each current path can be reduced, thereby reducing the operating voltage of the comparator, as compared to a comparator structure including only one stage of circuitry.

First stage circuit 201 is provided with a first pair of transistors and a second pair of transistors for receiving an input signal and a reference signal. That is, a first transistor of the first pair of transistors is configured to receive the input signal and a second transistor of the first pair of transistors is configured to receive the reference signal. A first transistor of the second pair of transistors is for receiving an input signal and a second transistor of the second pair of transistors is for receiving a reference signal. The first pair of transistors and the second pair of transistors are further configured to generate a differential signal from the input signal and the reference signal during the sampling phase.

Since the first pair of tubes and the second pair of tubes have different transistor types, their pull directions to the voltage are different. The input signal and the reference signal are used to control the pull capability of the first pair of transistors and the second pair of transistors to the voltage. If the input signal and the reference signal make the pulling capacity of the first pair of transistors and the second pair of transistors to the voltage unbalanced, even if the difference between the input signal and the reference signal is very tiny, the differential signal can be generated between the first pair of transistors and the second pair of transistors, so that the precision of the comparator is improved.

For example: the first transistor pair comprises a first input transistor P1 and a second input transistor P2, the second transistor pair comprises a third input transistor N1 and a fourth input transistor N2, and the reference signal balances the ability of the second input transistor P2 to pull a voltage up and the ability of the fourth input transistor N2 to pull a voltage down. When the input signal is slightly larger than the reference signal, the input signal unbalances the ability of the first input transistor P1 to pull up the voltage and the ability of the third input transistor N1 to pull down the voltage, and a differential signal is generated between the first pair of transistors and the second pair of transistors.

When the input signal and the reference signal generate differential signals on two sets of paired transistors, the positive feedback circuit 203 is used to accelerate the difference between the differential signals, and the first stage circuit 201 is further used to output the differential signals after accelerated processing. The second stage circuit 202 is used for performing amplification processing and latch processing on the voltage signal at the output terminal of the first stage circuit 201 in the regeneration stage.

It should be noted that, because the first pair of transistors and the second pair of transistors with different types are used to receive the input signal and the reference signal, the value of the reference signal can be changed from 0.3V to 0.9V, and both differential signals can be generated on the first pair of transistors and the second pair of transistors, so that the selection range of the reference voltage of the comparator is expanded.

Because the first stage circuit 201 uses two sets of pair transistors to receive the input signal and the reference signal, and the pulling capability of the two sets of pair transistors to different directions of voltage, the first stage circuit 201 needs a long time to present a differential signal with a large difference value at the output end, that is, the response time of the first stage circuit 201 is prolonged. The positive feedback circuit 203 accelerates the difference between the differential signals through a positive feedback mechanism, so as to shorten the time that the first-stage circuit 201 presents the differential signal with a larger difference at the output end, that is, the time that the comparator is in a sampling stage is shortened, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

In one embodiment, the first stage 201 and the second stage 202 have the same number of transistors in their respective current paths, so that the operating voltages of the first stage 201 and the second stage 202 are the same, the number of power supply terminals required for the comparator is reduced, and the circuit of the comparator is simplified.

In an embodiment, the positive feedback circuit 203 includes a first positive feedback module and a second positive feedback module, both the first positive feedback module and the second positive feedback module are connected to the output end of the first stage circuit, both the first feedback module and the second feedback module are used for pulling the voltage at the output end of the first stage circuit to accelerate the difference between the differential signals, and the direction in which the first feedback module pulls the voltage at the output end of the first stage circuit is different from the direction in which the second feedback module pulls the voltage at the output end of the first stage circuit. By using the two feedback modules with opposite pulling directions to pull the difference value of the differential signal, the amplitude of a larger voltage signal in the differential signal can be increased, the amplitude of a smaller voltage signal in the differential signal can be decreased, and the difference value of the differential signal can be further accelerated.

In one embodiment, the first stage circuit is provided with two outputs, and the two outputs are labeled as a first output and a second output. The first feedback module includes a first feedback unit 2031 and a second feedback unit 2032, and the first feedback unit 2031 and the second feedback unit 2032 are both provided with a control end and a first end.

The control terminal of the first feedback unit 2031 is connected to the first output terminal of the first stage circuit, and the first terminal of the first feedback unit 2031 is connected to the second output terminal of the first stage circuit, so as to pull the voltage of the second output terminal of the first stage circuit according to the voltage of the first output terminal of the first stage circuit.

A control terminal of the second feedback unit 2032 is connected to the second output terminal of the first stage circuit, and a first terminal of the second feedback unit 2032 is connected to the first output terminal of the first stage circuit, so as to pull the voltage of the first output terminal of the first stage circuit according to the voltage of the second output terminal of the first stage circuit.

The first feedback unit 2031 and the second feedback unit 2032 have the same voltage pulling direction, and if both are pulled upward, the larger the control end voltage of the first feedback unit is, the weaker the upward pulling capability is. If the first feedback unit and the second feedback unit are pulled downwards, the larger the voltage of the control end of the first feedback unit is, the stronger the downward pulling capacity is.

Taking the first feedback unit 2031 and the second feedback unit 2032 as an example, when the voltage of the first output end of the first-stage circuit is greater than the voltage of the second output end of the first-stage circuit, the ability of the first feedback unit 2031 to pull the voltage of the second output end upward is less than the ability of the second feedback unit 2032 to pull the voltage of the first output end upward, so that the difference between the voltage of the first output end of the first-stage circuit and the voltage of the second output end becomes larger and larger, and positive feedback is realized.

In an embodiment, the second feedback module includes a third feedback unit 2033 and a fourth feedback unit 2034, and each of the third feedback unit 2033 and the fourth feedback unit 2034 is provided with a control end and a first end.

The control end of the third feedback unit 2033 is connected to the first output end of the first stage circuit, the first end of the third feedback unit 2033 is connected to the second output end of the first stage circuit, and the third feedback unit 2033 is configured to pull the voltage of the second output end of the first stage circuit downward according to the voltage of the first output end of the first stage circuit.

The control end of the fourth feedback unit 2034 is connected to the second output end of the first stage circuit, the first end of the fourth feedback unit 2034 is connected to the first output end of the first stage circuit, and the fourth feedback unit 2034 is configured to pull the voltage of the first output end of the first stage circuit downwards according to the voltage of the second output end of the first stage circuit.

The third feedback unit 2033 and the fourth feedback unit 2034 have the same direction and capability of pulling the voltage as the first feedback unit 2031 and the second feedback unit 2032, and are not described again here.

Taking the third feedback unit 2033 and the fourth feedback unit 2034 for example to pull the voltage downwards, with the above arrangement, when the voltage of the first output end of the first-stage circuit is greater than the voltage of the second output end of the first-stage circuit, the ability of the fourth feedback unit 2034 to pull the voltage of the second output end downwards is greater than the ability of the second feedback unit 2032 to pull the voltage of the first output end upwards, so that the difference between the voltage of the first output end of the first-stage circuit and the voltage of the second output end is larger and larger, and positive feedback is realized.

In the above technical solution, the first feedback unit 2031 and the second feedback unit 2032 are used to jointly control two output ends of the first stage circuit, and the third feedback unit 2033 and the fourth feedback unit 2034 are used to jointly control two output ends of the first stage circuit, so as to implement a positive feedback mechanism, accelerate a difference value of a differential signal at the first stage output end, and shorten a time of the comparator in a sampling stage, thereby increasing a response rate of comparison and reducing power consumption of the comparator.

As shown in fig. 4, an embodiment of the present application provides a specific circuit of a comparator, where the comparator includes a first stage circuit, a second stage circuit, and a positive feedback circuit.

Wherein the first stage circuit includes a first input transistor P1 and a second input transistor P2. The first input transistor P1 and the second input transistor P2 constitute a first pair of transistors.

The control terminal of the first input transistor P1 is used for receiving the input signal In, the first terminal of the first input transistor P1 is connected to the power supply terminal, and the second terminal of the first input transistor P1 is used as the first output terminal of the first stage circuit.

The control terminal of the second input transistor P2 is configured to receive the reference signal Vr, the first terminal of the second input transistor P2 is connected to the power supply terminal, and the second terminal of the second input transistor P2 serves as the second output terminal of the first stage circuit.

The first stage circuit further includes a third input transistor N1, a fourth input transistor N2, and a fifth input transistor N3. The second input transistor N1 and the second input transistor N2 form a second pair of transistors.

The control end of the third input transistor N1 is used for receiving an input signal, and the first end of the third input transistor N1 is connected with the second end of the first input transistor P1 to form a first output end of the first stage circuit.

The control end of the fourth input transistor N2 is configured to receive a reference signal, and the first end of the fourth input transistor N2 is connected to the second end of the second input transistor P2 to form a second output end of the first stage circuit.

A control terminal of the fifth input transistor N3 is configured to receive a clock signal, a first terminal of the fifth input transistor N3 is connected to the second terminal of the third input transistor N1 and the second terminal of the fourth input transistor N2, and a second terminal of the fifth input transistor N3 is connected to the ground terminal.

The fifth input transistor N3 is used to control the operating state of the first stage circuit. In the reset stage, the fifth input transistor N3 is turned off, the first stage circuit stops working, and in the sampling stage, the regeneration stage, and the decision stage, the first stage circuit works. During the sampling phase, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 generate differential signals under the control of the input signal and the reference signal.

The second stage circuit includes a first output transistor N4, a second output transistor N5, a third output transistor N6, a fourth output transistor N7, a fifth output transistor P5, a sixth output transistor P6, and a seventh output transistor P7.

The control terminal of the first output transistor N4 is a first input terminal of the second stage circuit, and is connected to the second terminal of the first input transistor P1 in the first stage circuit. The first terminal of the first output transistor N4 is the first output terminal of the second stage circuit. The second terminal of the first output transistor N4 is connected to the ground terminal.

The control terminal of the second output transistor N5 is the second input terminal of the second stage circuit, and is connected to the second terminal of the second input transistor P2 in the first stage circuit. The first terminal of the second output transistor N5 is the first output terminal of the second stage circuit. The second terminal of the second output transistor N5 is connected to the ground terminal.

A first terminal of the third output transistor N6 is connected to the first terminal of the first output transistor N4, and a second terminal of the third output transistor N6 is connected to the second terminal of the first output transistor N4.

A first terminal of the fourth output transistor N7 is connected to a first terminal of the second output transistor N5, and a second terminal of the fourth output transistor N7 is connected to a second terminal of the second output transistor N5.

A second terminal of the fifth output transistor P5 is connected to the first terminal of the third output transistor N6, and a control terminal of the fifth output transistor P5 is connected to the control terminal of the third output transistor N6 and then connected to the first terminal of the fourth output transistor N7.

A second end of the sixth output transistor P6 is connected to the first end of the fourth output transistor N7, and a control end of the sixth output transistor P6 is connected to the control end of the fourth output transistor N7 and then connected to the first end of the third output transistor.

A control terminal of the seventh output transistor P7 is configured to receive the clock signal, a first terminal of the seventh output transistor P7 is connected to the power supply terminal, and a second terminal of the seventh output transistor P7 is connected to the first terminal of the fifth output transistor and the first terminal of the sixth output transistor.

The seventh output transistor P7 is used to control the operating state of the second stage circuit. In the reset phase, the seventh output transistor P7 is turned off, the second stage circuit stops working, and in the sampling phase, the regeneration phase and the decision phase, the seventh output transistor P7 works.

In the regeneration stage and the decision stage, the first output transistor N4 and the second output transistor N5 are used for amplifying the differential signal of the first stage circuit, and the third output transistor N6, the fourth output transistor N7, the fifth output transistor P5 and the sixth output transistor P6 form a latch for amplifying and latching the signals of the first ends of the first output transistor N4 and the second output transistor N5 to output the comparison result.

The first stage circuit is connected to a ground terminal through a fifth input transistor N3 and to a power supply terminal through a first input transistor P1 and a second input transistor P2. Each current path in the first stage circuit contains 3 transistors, for example: a current path formed by the first input transistor P1, the third input transistor N1, and the fifth input transistor N3.

The second stage circuit is connected to a ground terminal through any one of the first to fourth output transistors N4 to N7, and the second stage circuit is connected to a power supply terminal through the seventh output transistor P7. Each current path in the second stage circuit includes 3 transistors, for example: a current path formed by the first output transistor N4, the fifth input transistor P5, and the seventh input transistor P7.

Compared with a comparator adopting a one-level structure, the comparator has the advantages of lower working voltage and wider application range by adopting the structures of the first-level circuit and the second-level circuit.

In one embodiment, the first feedback unit includes a first feedback transistor P8, a control terminal of the first feedback transistor P8 is connected to the second terminal of the first input transistor P1, and a second terminal of the first feedback transistor P8 is connected to the second terminal of the second input transistor P2.

The second feedback unit includes a second feedback transistor P9, a control terminal of the second feedback transistor P9 is connected to the second terminal of the second input transistor P2, and a second terminal of the second feedback transistor P9 is connected to the second terminal of the first input transistor P1.

The third feedback unit includes a third feedback transistor N8, a control terminal of the third feedback transistor N8 is connected to the second terminal of the third input transistor N1, and a first terminal of the third feedback transistor N8 is connected to the first terminal of the fourth input transistor N2.

The fourth feedback unit includes a fourth feedback transistor N9, a control terminal of the third feedback transistor N9 is connected to the first terminal of the fourth input transistor N2, and a first terminal of the third feedback transistor N9 is connected to the second terminal of the third input transistor N1.

If the first feedback transistor P8 and the second feedback transistor P9 are P-type transistors, both the feedback transistors pull the voltage of the output end of the first-stage circuit upward, and the larger the control terminal voltage of the feedback transistors is, the smaller the capability of the feedback transistors to pull the voltage of the output end of the first-stage circuit downward is.

If the third feedback transistor N8 and the fourth feedback transistor N9 are N-type transistors, both the feedback transistors pull down the voltage of the output terminal of the first-stage circuit, and the larger the voltage of the control terminal of the feedback transistor is, the larger the ability of the feedback transistor to pull down the voltage of the output terminal of the first-stage circuit is.

In an embodiment, the first feedback transistor P8, the second feedback transistor P9, the first input transistor P1 and the second input transistor P2 are of the same type, and the third feedback transistor N8, the fourth feedback transistor N9, the third input transistor N1, the fourth input transistor N2 and the fifth input transistor N3 are of the same type.

If the first feedback transistor P8, the second feedback transistor P9, the first input transistor P1, and the second input transistor P2 are all P-type transistors, the drain of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

If the third feedback transistor N8, the fourth feedback transistor N9, the third input transistor N1, the fourth input transistor N2, and the fifth input transistor N3 are all N-type transistors, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

The second-stage circuit comprises a first output transistor N4, a second output transistor N5, a third output transistor N6 and a fourth output transistor N7 which are of the same type, and a fifth output transistor P5, a sixth output transistor P6 and a seventh output transistor P7 which are of the same type.

If the first output transistor N4, the second output transistor N5, the third output transistor N6, and the fourth output transistor N7 are all N-type transistors, the source of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

If the fifth output transistor P5, the sixth output transistor P6 and the seventh output transistor P7 are all P-type transistors, the drain of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

In one embodiment, the first feedback transistor P8 and the second feedback transistor P9 are the same size, the first input transistor P1 and the second input transistor P2 are the same size, and the size of the first feedback transistor P8 is less than one-half of the size of the first input transistor P1.

In one embodiment, the third feedback transistor N8 and the fourth feedback transistor N9 have the same size, the third input transistor N1 and the fourth input transistor N2 have the same size, and the size of the third feedback transistor N8 is smaller than one-half of the size of the fifth input transistor N1.

Through the size setting, the influence of the feedback transistor on the sensing of the input transistor on the input signal and the reference signal due to the fact that the pulling capacity of the feedback transistor on the voltage is too strong is avoided, and the accuracy of the output result of the comparator is guaranteed while the response rate of the comparator is improved.

Table 1 below illustrates that the comparator can implement rail-to-rail detection, that is, the variation range of the reference voltage is relatively large, and taking the power supply terminal voltage VDD as 1.2V as an example, the range of the reference signal can be varied from 0.3V to 0.9V.

TABLE 1 working principle of the sampling phase of the comparator

In case 3, the first input transistor P1, the second input transistor P2 and the third input transistor N1 are all turned on, the pull-up capability of the first input transistor P1 is smaller than that of the second input transistor P2, and the third input transistor N1 also pulls down the voltage of the first input transistor P1, so VP1 < VP2.

In case 6, the first input transistor P1, the second input transistor P2, the third input transistor N1 and the fourth input transistor N2 are all turned on, the pull-up capability of the first input transistor P1 is greater than that of the second input transistor P2, and the capability of the third input transistor N1 to pull down the voltage of the first input transistor P1 is less than that of the fourth input transistor N2 to pull down the voltage of the second input transistor P2, so VP1 > VP2.

For the analysis of other cases, reference may be made to the analysis of cases 3 and 6, which are not described herein again.

That is, when the reference voltage changes from 0V to 0.9V, a differential signal can be generated on the first input transistor P1 and the second input transistor P2, and then the difference of the differential signal is accelerated by the first feedback transistor P8, the second feedback transistor P9, the third feedback transistor N8 and the fourth feedback transistor N9 through a positive feedback mechanism, so that the sampling time can be shortened.

In one embodiment, the comparator further comprises a reset circuit for resetting the voltage at the output of the first stage circuit. More specifically, the reset circuit includes a first reset transistor P3 and a second reset transistor P4, a second terminal of the first reset transistor P3 is connected to a second terminal of the first input transistor P1, and a second terminal of the second reset transistor P4 is connected to a second terminal of the second input transistor P2.

The transistor types of the first reset transistor P3 and the second reset transistor P4 are the same as the type of the first input transistor P1, and when the first reset transistor P3 and the second reset transistor P4 are P-type transistors, the drains of the P-type transistors are second ends. In the reset phase, the first reset transistor P3 and the second reset transistor P4 are turned on, pulling up the voltages of the first input transistor P1 and the second input transistor P2 to a high level.

As shown in fig. 5, an embodiment of the present application provides a specific circuit of a comparator, where the comparator includes a first stage circuit, a second stage circuit, and a positive feedback circuit.

The first stage circuit includes a first input transistor N1 and a second input transistor N2. The first input transistor N1 and the second input transistor N2 constitute a first transistor pair.

The control terminal of the first input transistor N1 is configured to receive an input signal In, the first terminal of the first input transistor N1 is connected to the ground terminal, and the second terminal of the first input transistor N1 is used as the first output terminal of the first stage circuit.

The control terminal of the second input transistor N2 is configured to receive the reference signal Vr, the first terminal of the second input transistor N2 is connected to the ground terminal, and the second terminal of the second input transistor N2 is used as the second output terminal of the first stage circuit.

The first stage circuit further includes a third input transistor P1, a fourth input transistor P2, and a fifth input transistor P3. The second input transistor P1 and the second input transistor P2 form a second pair of transistors.

The control terminal of the third input transistor P1 is configured to receive the input signal In, and the first terminal of the third input transistor P1 is connected to the second terminal of the first input transistor N1 to form a first output terminal of the first stage circuit.

The control end of the fourth input transistor P2 is configured to receive the reference signal Vr, and the first end of the fourth input transistor P2 is connected to the second end of the second input transistor N2 to form a second output end of the first stage circuit.

The control terminal of the fifth input transistor P3 is configured to receive the clock signal CLKB, which represents the inverted clock signal, i.e., the clock signal is inverted and then input to the fifth input transistor P3, the first terminal of the fifth input transistor P3 is connected to the second terminal of the third input transistor P1 and the second terminal of the fourth input transistor P2, and the second terminal of the fifth input transistor P3 is connected to the power supply terminal.

The fifth input transistor P3 is used to control the operating state of the first stage circuit. In the reset phase, the fifth input transistor P3 is turned off, the first-stage circuit stops working, and in the sampling phase, the regeneration phase and the decision phase, the first-stage circuit works. In the sampling phase, the first input transistor N1, the second input transistor N2, the third input transistor P1 and the fourth input transistor P2 generate differential signals under the control of the input signal and the reference signal.

The second stage circuit includes a first output transistor P4, a second output transistor P5, a third output transistor P6, a fourth output transistor P7, a fifth output transistor N5, a sixth output transistor N6, and a seventh output transistor N7.

The control terminal of the first output transistor P4 is the first input terminal of the second stage circuit, and is connected to the second terminal of the first input transistor N1 in the first stage circuit. The first terminal of the first output transistor P4 is the first output terminal of the second stage circuit. The second terminal of the first output transistor P4 is connected to the power supply terminal.

The control terminal of the second output transistor P5 is the second input terminal of the second stage circuit, and is connected to the second terminal of the second input transistor N2 in the first stage circuit. The first terminal of the second output transistor P5 is the first output terminal of the second stage circuit. The second terminal of the second output transistor P5 is connected to the power supply terminal.

A first terminal of the third output transistor P6 is connected to the first terminal of the first output transistor P4, and a second terminal of the third output transistor P6 is connected to the second terminal of the first output transistor P4.

A first terminal of the fourth output transistor P7 is connected to a first terminal of the second output transistor P5, and a second terminal of the fourth output transistor P7 is connected to a second terminal of the second output transistor P5.

A second terminal of the fifth output transistor N5 is connected to the first terminal of the third output transistor P6, and a control terminal of the fifth output transistor N5 is connected to the control terminal of the third output transistor P6 and then to the first terminal of the fourth output transistor P7.

A second terminal of the sixth output transistor N6 is connected to the first terminal of the fourth output transistor P7, and a control terminal of the sixth output transistor N6 is connected to the first terminal of the third output transistor P6 after being connected to the control terminal of the fourth output transistor P7.

A control terminal of the seventh output transistor N7 is configured to receive the clock signal CLK, a first terminal of the seventh output transistor N7 is connected to the ground terminal, and a second terminal of the seventh output transistor N7 is connected to the first terminal of the fifth output transistor N5 and the first terminal of the sixth output transistor N6.

The seventh output transistor N7 is used to control the operating state of the second stage circuit. In the reset phase, the seventh output transistor N7 is turned off, the second stage circuit stops working, and in the sampling phase, the regeneration phase, and the decision phase, the seventh output transistor N7 works.

The functions of the transistors in the second stage circuit have been described in the above embodiments, and are not described in detail here.

The current paths of the first stage circuit and the second stage circuit have been described in the above embodiments, and are not described herein again.

In an embodiment, the first feedback unit includes a first feedback transistor N8, a control terminal of the first feedback transistor N8 is connected to the second terminal of the first input transistor N1, and a second terminal of the first feedback transistor N8 is connected to the second terminal of the second input transistor N2.

The second feedback unit includes a second feedback transistor N9, a control terminal of the second feedback transistor N9 is connected to the second terminal of the second input transistor N2, and a second terminal of the second feedback transistor N9 is connected to the second terminal of the first input transistor N1.

The third feedback unit includes a third feedback transistor P8, a control terminal of the third feedback transistor P8 is connected to the second terminal of the third input transistor P1, and a first terminal of the third feedback transistor P8 is connected to the first terminal of the fourth input transistor P2.

The fourth feedback unit includes a fourth feedback transistor P9, a control terminal of the third feedback transistor P9 is connected to the first terminal of the fourth input transistor P2, and a first terminal of the third feedback transistor P9 is connected to the second terminal of the third input transistor P1.

In one embodiment, if the first feedback transistor N8, the second feedback transistor N9, the first input transistor N1, and the second input transistor N2 are all N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

If the third feedback transistor P8, the fourth feedback transistor P9, the third input transistor P1, the fourth input transistor P2, and the fifth input transistor P3 are all P-type transistors, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

In one embodiment, if the first output transistor P4, the second output transistor P5, the third output transistor P6 and the fourth output transistor P7 are all P-type transistors, the source of the P-type transistor is the second terminal, and the gate of the P-type transistor is the control terminal.

If the fifth output transistor N5, the sixth output transistor N6 and the seventh output transistor N7 are all N-type transistors, the drain of the N-type transistor is the second terminal, and the gate of the N-type transistor is the control terminal.

In an embodiment, the comparator further includes a first reset transistor N3 and a second reset transistor N4, a second terminal of the first reset transistor N3 is connected to the second terminal of the first input transistor N1, and a second terminal of the second reset transistor N4 is connected to the second terminal of the second input transistor N2. When the first reset transistor N3 and the second reset transistor N4 are N-type transistors, the drains of the N-type transistors are second terminals. In the reset phase, the first reset transistor N3 and the second reset transistor N4 are turned on, pulling the voltages of the first input transistor N1 and the second input transistor N2 to a low level.

Fig. 6 is a block diagram of a comparator according to the present application, and as shown in fig. 6, the comparator includes a first stage circuit 201, a second stage circuit 202, and a positive feedback circuit 203.

The first stage 201 has two output terminals, which are denoted as a first output terminal and a second output terminal, and the positive feedback circuit 203 includes a first controllable feedback module 21 and a second controllable feedback module 22.

The first controllable feedback module 21 comprises at least one first controllable feedback sub-module 23, wherein each first controllable feedback sub-module 23 comprises a first feedback unit 2031, a second feedback unit 2032, a first switch 1001 and a second switch 1002. The first feedback unit 2031 and the second feedback unit 2032 are each provided with a control terminal and a first terminal.

A control terminal of the first feedback unit 2031 is connected to a first output terminal of the first stage circuit 201 through the first switch 1001, and a first terminal of the first feedback unit 2031 is connected to a second output terminal of the first stage circuit 201. A control terminal of the second feedback unit 2032 is connected to the second output terminal of the first stage circuit 201 through the second switch 1002, and a first terminal of the second feedback unit 2032 is connected to the first output terminal of the first stage circuit 201.

The first feedback unit 2031 is configured to pull the voltage of the second output terminal of the first stage circuit according to the voltage of the first output terminal of the first stage circuit under the control of the first switch 1001, and the second feedback unit 2032 is configured to pull the voltage of the first output terminal of the first stage circuit according to the voltage of the second output terminal of the first stage circuit under the control of the second switch 1002. By controlling the closing and opening of the first switch 1001 and the second switch 1002, it can be controlled whether the first controllable feedback sub-module generates feedback. When both the first switch 1001 and the second switch 1002 are closed, the first controllable feedback sub-module 23 may accelerate the difference between the differential signals at the output of the first stage 201 by a feedback mechanism. When both the first switch 1001 and the second switch 1002 are open, the first controllable feedback submodule 23 is disconnected from the first stage circuit 201, and a feedback mechanism cannot be generated at the output terminal of the first stage circuit 201.

The second controllable feedback module 22 comprises at least one second controllable feedback sub-module 24, wherein each second controllable feedback sub-module 24 comprises a third feedback unit 2033, a fourth feedback unit 2034, a third switch 1003 and a fourth switch 1004. The third feedback unit 2033 and the fourth feedback unit 2034 are each provided with a control terminal and a first terminal.

A control terminal of the third feedback unit 2033 is connected to the first output terminal of the first stage 201 through the third switch 1003, and a first terminal of the third feedback unit 2033 is connected to the second output terminal of the first stage 201. A control terminal of the fourth feedback unit 2034 is connected to the second output terminal of the first stage 201 through the third switch 1004, and a first terminal of the fourth feedback unit 2034 is connected to the first output terminal of the first stage 201.

The third feedback unit 2033 is configured to pull the voltage of the second output terminal of the first stage circuit according to the voltage of the first output terminal of the first stage circuit under the control of the third switch 1003, and the fourth feedback unit 2034 is configured to pull the voltage of the first output terminal of the first stage circuit according to the voltage of the second output terminal of the first stage circuit under the control of the fourth switch 1004. By controlling the closing and opening of the third switch 1003 and the fourth switch 1004, it may be controlled whether the second controllable feedback sub-module 23 generates feedback. When both the third switch 1003 and the fourth switch 1004 are closed, the second controllable feedback sub-module 23 may accelerate the difference between the differential signals at the output of the first stage 201 by a feedback mechanism. When both the third switch 1003 and the fourth switch 1004 are turned off, the second controllable feedback sub-module 23 is disconnected from the first stage 201, and a feedback mechanism cannot be generated at the output of the first stage 201.

When the comparator is in operation, the number of first controllable feedback sub-modules 23 and second controllable feedback sub-modules 24 that generate feedback can be controlled, and thus the ability of the first controllable feedback module 21 and the second controllable feedback module 22 to pull the difference between the differential signals. Therefore, on one hand, the time of the comparator in the sampling stage is controlled, and the response rate of the comparator is ensured. On the other hand, the ability of the feedback circuit 203 to pull the voltage of the output terminal of the first stage circuit 201 and the ability of the input signal and the reference signal to pull the voltage of the output terminal of the first stage circuit 201 can be balanced, so that the comparator can accurately output a comparison result according to the input signal and the reference signal.

Fig. 7 and 8 are specific circuit diagrams based on the comparator shown in fig. 6, wherein the structures of the first stage circuit 201 and the second stage circuit 202 are the same as the comparator shown in fig. 4, and are not repeated here.

The specific circuit structure of the first controllable feedback sub-module 23 and the second controllable feedback sub-module 24 of the feedback circuit 203 is described below with reference to fig. 8.

The first feedback unit 2031 comprises a first feedback transistor P8, and a control terminal of the first feedback transistor P8 is connected to the second terminal of the first input transistor P1 through a first switch 1001. A second terminal of the first feedback transistor P8 is connected to a second terminal of the second input transistor P2.

The second feedback unit 2032 comprises a second feedback transistor P9, and a control terminal of the second feedback transistor P9 is connected to the second terminal of the second input transistor P2 through a second switch 1002. A second terminal of the first feedback transistor P8 is connected to a second terminal of the first input transistor P1.

The third feedback unit 2033 comprises a third feedback transistor N8, and a control terminal of the third feedback transistor N8 is connected to the first terminal of the third input transistor N1 through the third switch 1003. A first terminal of the third feedback transistor N8 is connected to a first terminal of the fourth input transistor N2.

The fourth feedback unit 2034 comprises a fourth feedback transistor N9, and a control terminal of the fourth feedback transistor N9 is connected to the first terminal of the fourth input transistor N2 through a fourth switch 1004. A first terminal of the fourth feedback transistor N9 is connected to a first terminal of the third input transistor N1.

The first switch 1001 includes a first transmission gate G1, and the first transmission gate G1 is controlled by a first enable signal EN 1.

The second switch 1002 includes a second transmission gate G2, and the second transmission gate G2 is controlled by a second enable signal EN 2.

The third switch 1003 includes a third transmission gate G3, and the third transmission gate G3 is controlled by a third enable signal EN 3.

The fourth switch 1004 includes a fourth transmission gate G4, and the fourth transmission gate G4 is controlled by a fourth enable signal EN 4.

The first enable signal E1 to the fourth enable signal EN4 are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

When the first transmission gate G1 and the second transmission gate G2 are opened, the first feedback transistor N8 and the second feedback transistor N9 work together to generate positive feedback, and when the first transmission gate G1 and the second transmission gate G2 are closed, the first feedback transistor N8 and the second feedback transistor N9 stop working.

In an embodiment, the first controllable feedback sub-module 23 further includes a first zero switch K10 and a zero-th zero switch K00, the control terminal of the first feedback transistor P8 is connected to the power supply terminal through the first zero switch 201, and the first zero switch K10 is turned on when the first transmission gate G1 is turned off, so that the first feedback transistor P8 does not float, and external interference is reduced. The control end of the second feedback transistor P9 is connected with the power supply end through the zeroth switch K00, and the zeroth switch K00 is conducted when the second transmission gate G2 is closed, so that the second feedback transistor P9 is not floated, and the external interference is reduced.

In an embodiment, the second controllable feedback sub-module 24 further includes a zeroth switch K01 and a first switch K11, the control terminal of the third feedback transistor N8 is connected to the ground terminal through the zeroth switch K01, and the zeroth switch K11 is turned on when the third transmission gate G3 is turned off, so that the third feedback transistor N8 does not float, and external interference is reduced. The control end of the fourth feedback transistor N9 is connected to the ground end through the first switch K11, and the first switch K11 is turned on when the fourth transmission gate G4 is turned off, so that the fourth feedback transistor N9 does not float, and external interference is reduced.

In one embodiment, the first zero switch K10 and the zero-th switch K00 are P-type transistors, a drain of the first zero switch K10 is connected to a gate of the first feedback transistor P8, a drain of the zero-th switch K00 is connected to a control terminal of the second feedback transistor P9, sources of the first zero switch 201 and the zero-th switch 202 are connected to a power source terminal, and the first feedback transistor P8 and the second feedback transistor P9 are pulled to a high level when the first transmission gate G1 and the second transmission gate G2 are turned off.

In an embodiment, the zeroth switch K01 and the first switch K11 are N-type transistors, a drain of the zeroth switch K01 is connected to a gate of the third feedback transistor N8, a drain of the first switch K11 is connected to a gate of the fourth feedback transistor N9, sources of the zeroth switch K01 and the first switch K11 are connected to a ground terminal, and the third feedback transistor N8 and the fourth feedback transistor N9 are pulled to a low level when the third transmission gate G3 and the fourth transmission gate G4 are turned off.

Fig. 9 and fig. 10 are specific circuit diagrams of the comparator shown in the figures, wherein the structures of the first stage circuit 201, the second stage circuit 202 and the reset circuit are the same as the comparator shown in fig. 4, and are not repeated herein. The positive feedback circuit is similar to that of FIG. 8 and will not be described herein.

In the above embodiment, the positive feedback circuit 203 includes a plurality of first controllable feedback sub-modules and a plurality of second controllable positive feedback sub-modules, and the capability of the positive feedback circuit 203 to pull the voltages of the two output terminals of the first stage circuit 201 is adjusted by controlling the number of the controllable positive feedback sub-modules providing the positive feedback mechanism, so as to control the time of the comparator in the sampling stage, balance the pulling capability of the positive feedback circuit 203, the input signal, and the reference signal on the output terminals of the first stage circuit 201, and improve the response rate and accuracy of the comparator.

An embodiment of the present application provides a comparator, which includes a first stage circuit, a second stage circuit, and a positive feedback circuit. The first-stage circuit is provided with an output end, and the second-stage circuit and the positive feedback circuit are both connected with the output end of the first-stage circuit.

The first stage circuit is connected to a power supply terminal and a ground terminal, so that the transistors in the first stage circuit form a current path. The second stage circuit is connected to the power supply terminal and the ground terminal so that the transistor in the second stage circuit forms another current path. By so doing, the number of transistors in each current path can be reduced, thereby reducing the operating voltage of the comparator, as compared to a comparator structure including only one stage of circuit.

When the input signal and the reference signal generate differential signals in the first stage circuit, the positive feedback circuit is used for accelerating the difference between the differential signals, and the first stage circuit is also used for outputting the differential signals subjected to accelerated processing. The second stage circuit is used for carrying out amplification processing and latch processing on the voltage signal of the output end of the first stage circuit in the regeneration stage.

When the reference signal is not properly selected, the first-stage circuit needs a long time to present a differential signal with a large difference at the output end, that is, the response time of the first-stage circuit is prolonged. The positive feedback circuit accelerates the difference between the differential signals through a positive feedback mechanism, and further shortens the time of the first-stage circuit presenting the differential signals with larger difference at the output end, namely shortens the time of the comparator in the sampling stage, thereby improving the response rate of the comparator and reducing the power consumption of the comparator.

In one embodiment, the first stage circuit and the second stage circuit have the same number of transistors on respective current paths, so that the operating voltages of the first stage circuit and the second stage circuit are the same, the number of power supply terminals required by the comparator is reduced, and the circuit of the comparator is simplified.

In one embodiment, the first stage circuit is provided with two outputs, and the two outputs are labeled as a first output and a second output. The positive feedback circuit comprises at least one controllable feedback sub-module, wherein each controllable feedback sub-module comprises a third feedback unit, a fourth feedback unit, a third switch and a fourth switch. The third feedback unit and the fourth feedback unit are both provided with a control end and a first end.

The control end of the third feedback unit is connected with the first output end of the first-stage circuit through the third switch, and the first end of the third feedback unit is connected with the second output end of the first-stage circuit. The control end of the fourth feedback unit is connected with the second output end of the first-stage circuit through a fourth switch, and the first end of the fourth feedback unit is connected with the first output end of the first-stage circuit.

The third feedback unit is used for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the third switch, and the fourth feedback unit is used for pulling the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the fourth switch. By controlling the closing and opening of the third switch and the fourth switch, it is possible to control whether the first controllable feedback sub-module generates feedback. When the third switch and the fourth switch are both closed, the first controllable feedback sub-module may accelerate the difference between the differential signals at the output of the first stage circuit through a feedback mechanism. When the third switch and the fourth switch are both turned off, the first controllable feedback sub-module is turned off from the first-stage circuit, and a feedback mechanism cannot be generated at the output end of the first-stage circuit.

Fig. 11 and 12 are specific circuit diagrams of a comparator provided in the present application, and fig. 13 and 14 are specific circuit diagrams of another comparator provided in the present application. The second stage circuit and the reset circuit in the comparator shown in fig. 11 and 12 are the same as those in the comparator shown in fig. 4, and are not described again here.

Referring to fig. 11 and 12, the first stage circuit includes a third input transistor N1, a fourth input transistor N2, and a fifth input transistor N3, the three input transistors are N-type transistors, a gate of the N-type transistor is a control terminal, and a drain of the N-type transistor is a first terminal.

A control terminal of the third input transistor N1 is configured to receive an input signal, a control terminal of the fourth input transistor N2 is configured to receive a reference signal, a first terminal of the third input transistor N1 is used as a first output terminal of the first stage circuit, a first terminal of the fourth input transistor N2 is used as a second output terminal of the first stage circuit, a second terminal of the third input transistor N1 and a second terminal of the fourth input transistor N2 are connected to a first terminal of the fifth input transistor N3, and a second terminal of the fifth input transistor N3 is connected to the ground terminal.

The fifth input transistor N3 is used for controlling the working state of the first-stage circuit, when the fifth input transistor N3 is turned on, the first-stage circuit works, and when the fifth input transistor N3 is turned off, the first-stage circuit stops working. The third input transistor N1 and the fourth input transistor N2 are used to generate a differential signal from the input signal and the reference signal.

The structure of the controllable feedback sub-module in the positive feedback circuit shown in fig. 12 is the same as that of the second controllable feedback sub-module shown in fig. 8, and is not repeated here.

Referring to fig. 13 and 14, when the third input transistor P1, the fourth input transistor P2 and the fifth input transistor P3 are P-type transistors, the gate of the P-type transistor is the control terminal, and the drain of the P-type transistor is the first terminal. The structure of the controllable feedback sub-module in the positive feedback circuit shown in fig. 14 is the same as the structure of the second controllable feedback sub-module shown in fig. 10, and is not repeated herein.

In the above embodiment, the positive feedback circuit includes a plurality of controllable feedback sub-modules, and the capability of the positive feedback circuit to pull the voltages of the two output ends of the first stage circuit is adjusted by controlling the number of the controllable positive feedback sub-modules providing the positive feedback mechanism, so as to control the time of the comparator in the sampling stage, balance the pulling capability of the positive feedback circuit, the input signal and the reference signal on the output end of the first stage circuit, and improve the response rate and accuracy of the comparator.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A comparator, comprising:

and the second-stage circuit is connected with a power supply end and a grounding end, is connected with the output end of the first-stage circuit, and is used for amplifying and latching the voltage signal of the output end of the first-stage circuit in a regeneration stage so as to output a comparison result.

2. The comparator of claim 1, wherein the first stage circuit and the second stage circuit have the same number of transistors on respective current paths.

3. The comparator as claimed in claim 1 or 2, wherein the positive feedback circuit comprises:

the first feedback module is connected with the output end of the first-stage circuit and used for pulling the voltage of the output end of the first-stage circuit to accelerate the difference between the differential signals;

and the second feedback module is connected with the output end of the first-stage circuit and used for pulling the voltage of the output end of the first-stage circuit to accelerate the difference between the differential signals.

4. The comparator as claimed in claim 3, wherein the first stage circuit has two output terminals, and the first feedback module comprises:

a first feedback unit, a control end of which is connected with the first output end of the first stage circuit, a first end of which is connected with the second output end of the first stage circuit, and is used for pulling the voltage of the second output end of the first stage circuit according to the voltage of the first output end of the first stage circuit;

and the control end of the second feedback unit is connected with the second output end of the first-stage circuit, the first end of the second feedback unit is connected with the first output end of the first-stage circuit, and the second feedback unit is used for pulling the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit.

5. The comparator of claim 4, wherein:

the first feedback unit includes: a first feedback transistor, a control terminal of which is a control terminal of the first feedback unit, and a second terminal of which is a first terminal of the first feedback unit;

the second feedback unit includes: and a control end of the second feedback transistor is a control end of the second feedback unit, and a second end of the second feedback transistor is a first end of the second feedback unit.

6. The comparator as claimed in claim 5, wherein the first stage circuit has two output terminals, and the second feedback module comprises:

a control end of the third feedback unit is connected with the first output end of the first-stage circuit, a first end of the third feedback unit is connected with the second output end of the first-stage circuit, and the third feedback unit is used for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit;

and the control end of the fourth feedback unit is connected with the second output end of the first-stage circuit, the first end of the fourth feedback unit is connected with the first output end of the first-stage circuit, and the fourth feedback unit is used for pulling the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit.

7. The comparator of claim 6, wherein:

the third feedback unit includes: a third feedback transistor, a control terminal of which is a control terminal of the third feedback unit, and a first terminal of which is a first terminal of the third feedback unit;

the fourth feedback unit includes: and a control end of the fourth feedback transistor is a control end of the fourth feedback unit, and a first end of the fourth feedback transistor is a first end of the fourth feedback unit.

8. The comparator of claim 7, wherein the first stage circuit comprises:

a first input transistor, a control terminal of which is used for receiving the input signal, a second terminal of which is used as a first output terminal of the first stage circuit, a second terminal of which is connected with a second terminal of the first feedback transistor, a first terminal of which is connected with a first terminal of the first feedback transistor, and a first terminal of which is also connected with a first power supply terminal or a ground terminal;

and a second input transistor, a control terminal of which is used for receiving the reference signal, a second terminal of which is used as a second output terminal of the first stage circuit, a second terminal of which is connected with a second terminal of the second feedback transistor, a first terminal of which is connected with a first terminal of the second feedback transistor, and a first terminal of which is also connected with the first power supply terminal or the ground terminal.

9. The comparator of claim 8, wherein the first stage circuit further comprises:

a third input transistor, a control terminal of which is used for receiving the input signal, a first terminal of which is connected with the second terminal of the first input transistor, and a first terminal of which is connected with the first terminal of the third feedback transistor;

a fourth input transistor having a control terminal for receiving the reference signal, a first terminal connected to the second terminal of the second input transistor, and a first terminal connected to the first terminal of the fourth feedback transistor;

a fifth input transistor, having a control terminal for receiving a clock signal, a first terminal connected to the second terminal of the third input transistor, the second terminal of the fourth input transistor, the second terminal of the third feedback transistor, and the second terminal of the fourth feedback transistor, and a second terminal connected to a ground terminal or a power terminal.

10. The comparator of claim 9, wherein:

the first feedback transistor, the second feedback transistor, the first input transistor, and the second input transistor are of the same type;

the third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor, and the fifth input transistor are of the same type.

11. The comparator of claim 10, wherein:

when the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all P-type transistors, the drain of the P-type transistor is a second end, and the gate of the P-type transistor is a control end;

the third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor and the fifth input transistor are all N-type transistors, a source electrode of each N-type transistor is a second end, and a grid electrode of each N-type transistor is a control end;

or alternatively

When the first feedback transistor, the second feedback transistor, the first input transistor and the second input transistor are all N-type transistors, the drain electrode of the N-type transistor is a second end, and the grid electrode of the N-type transistor is a control end;

the third feedback transistor, the fourth feedback transistor, the third input transistor, the fourth input transistor and the fifth input transistor are all P-type transistors, a source electrode of each P-type transistor is a second end, and a grid electrode of each P-type transistor is a control end.

12. The comparator of claim 10, wherein:

the first feedback transistor and the second feedback transistor have the same size, the first input transistor and the second input transistor have the same size, and the size of the first feedback transistor is smaller than one half of the size of the first input transistor;

the third feedback transistor and the fourth feedback transistor have the same size, the third input transistor and the fourth input transistor have the same size, and the size of the third feedback transistor is smaller than one half of the size of the fifth input transistor.

13. The comparator of claim 1, wherein the second stage circuit comprises:

a first output transistor, a control terminal of which is a first input terminal of the second stage circuit, a first terminal of which is a first output terminal of the second stage circuit, and a second terminal of which is connected to a ground terminal or a power supply terminal;

a second output transistor, a control terminal of which is a second input terminal of the second stage circuit, a first terminal of which is a second output terminal of the second stage circuit, and a second terminal of which is connected to a ground terminal or a power supply terminal;

a third output transistor having a first terminal connected to the first terminal of the first output transistor and a second terminal connected to the second terminal of the first output transistor;

a fourth output transistor having a first terminal connected to the first terminal of the second output transistor and a second terminal connected to the second terminal of the second output transistor;

a fifth output transistor, a second end of which is connected to the first end of the third output transistor, a control end of which is connected to the control end of the third output transistor, and a control end of which is further connected to the first end of the fourth output transistor;

a second end of the sixth output transistor is connected with the first end of the fourth output transistor, a control end of the sixth output transistor is connected with the control end of the fourth output transistor, and the control end of the sixth output transistor is also connected with the first end of the third output transistor;

and a seventh output transistor having a control terminal for receiving a clock signal, a first terminal connected to a power supply terminal or a ground terminal, and a second terminal connected to the first terminal of the fifth output transistor and the first terminal of the sixth output transistor.

14. The comparator of claim 13, wherein:

the first output transistor to the fourth output transistor are all N-type transistors, the drain electrode of each N-type transistor is a first end, and the grid electrode of each N-type transistor is a control end;

the fifth output transistor to the seventh output transistor are all P-type transistors, a source electrode of each P-type transistor is a first end, and a grid electrode of each P-type transistor is a control end;

or alternatively

The first output transistor to the fourth output transistor are all P-type transistors, the drain electrode of each P-type transistor is a first end, and the grid electrode of each P-type transistor is a control end;

the fifth output transistor to the seventh output transistor are all N-type transistors, a source electrode of each N-type transistor is a first end, and a grid electrode of each N-type transistor is a control end.

15. The comparator of claim 3, wherein:

the first feedback module comprises at least one first controllable feedback sub-module, each first controllable feedback sub-module comprising:

a first feedback unit, a control end of which is connected with a first output end of the first-stage circuit through a first switch, and a first end of which is connected with a second output end of the first-stage circuit, for pulling a voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the first switch;

a second feedback unit, a control end of which is connected with the second output end of the first-stage circuit through a second switch, and a first end of which is connected with the first output end of the first-stage circuit, and is used for pulling the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the second switch;

the second feedback module comprises at least one second controllable feedback sub-module, each first controllable feedback sub-module comprising:

a third feedback unit, a control end of which is connected with the first output end of the first-stage circuit through a third switch, and a first end of which is connected with the second output end of the first-stage circuit, and is used for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the third switch;

and the control end of the fourth feedback unit is connected with the second output end of the first-stage circuit through a fourth switch, and the first end of the fourth feedback unit is connected with the first output end of the first-stage circuit and used for pulling the voltage of the first output end of the first-stage circuit under the control of the fourth switch according to the voltage of the second output end of the first-stage circuit.

16. The comparator of claim 15, wherein:

the second feedback unit includes: a second feedback transistor, a control terminal of which is a control terminal of the second feedback unit, and a second terminal of which is a first terminal of the second feedback unit;

17. The comparator of claim 15, wherein:

the first switch comprises a first transmission gate controlled by a first enable signal;

the second switch comprises a second transmission gate controlled by a second enable signal;

the third switch comprises a third transmission gate controlled by a third enable signal;

the fourth switch comprises a fourth transmission gate controlled by a fourth enable signal;

wherein the first to fourth enable signals are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

18. The comparator of claim 15, wherein:

the control end of the first feedback unit is also connected with a power end through a first zero switch;

the control end of the second feedback unit is also connected with a power end through a zeroth switch;

the control end of the third feedback unit is also connected with a grounding end through a zero first switch;

and the control end of the fourth feedback unit is also connected with the grounding end through a first switch.

19. A comparator, comprising:

the first-stage circuit is connected with a power supply end and a grounding end, is provided with an output end and is used for generating a differential signal according to an input signal and a reference signal in a sampling stage;

20. The comparator of claim 19, wherein the first stage circuit and the second stage circuit have the same number of transistors on the respective current paths.

21. The comparator as claimed in claim 20, wherein the first stage circuit has two outputs, the positive feedback circuit includes at least one controllable feedback sub-module, each controllable feedback sub-module includes:

a control end of the third feedback unit is connected with the first output end of the first-stage circuit through a third switch, a first end of the third feedback unit is connected with the second output end of the first-stage circuit, and the third feedback unit is used for pulling the voltage of the second output end of the first-stage circuit according to the voltage of the first output end of the first-stage circuit under the control of the third switch;

and the control end of the fourth feedback unit is connected with the second output end of the first-stage circuit through a fourth switch, the first end of the fourth feedback unit is connected with the first output end of the first-stage circuit, and the fourth feedback unit is used for pulling the voltage of the first output end of the first-stage circuit according to the voltage of the second output end of the first-stage circuit under the control of the fourth switch.

22. The comparator as claimed in claim 21, wherein:

23. The comparator of claim 21, wherein:

wherein the third enable signal and the fourth enable signal are generated according to an operating frequency of the comparator, an input common mode range of the comparator, and a test mode signal.

24. The comparator of claim 21, wherein: